Table of Contents
Advertisement
CPU Bits for Controlling the I-Cache
2
CPU Bits for Controlling the I-Cache
Figure 5.
CAFRZ, CAEN, and CACLR Bits in ST3_55
15
14
CAFRZ
CAEN
R/W-0
R/W-0
7
6
CBERR
MPNMC
2.1
CAEN Bit to Enable or Disable the I-Cache
2.2
CACLR Bit to Flush the I-Cache
16
Instruction Cache
Control of the I-Cache is maintained not only through the I-Cache registers but
also through three bits located in status register ST3_55 of the CPU. These
bits are highlighted in Figure 5. For more details about ST3_55, see the
TMS320C55x DSP CPU Reference Guide (SPRU371).
13
12
CACLR
HINT
R/W-0
5
4
SATA
Reserved
To enable the I-Cache, set the cache enable (CAEN) bit of ST3_55. To disable
the I-Cache, clear the CAEN bit. When disabled, the lines of the I-Cache data
arrays are not checked; instead, the I-Cache forwards instruction-fetch
requests directly to the external memory interface (EMIF).
For proper operation of the I-Cache, configure the I-Cache before enabling it
and disable the I-Cache before making any changes to its configuration.
A DSP reset forces CAEN = 0 (I-Cache disabled).
The flush operation is defined as the invalidation of all of the lines in the
I-Cache.
To flush the I-Cache, write 1 to the cache clear (CACLR) bit of ST3_55. In
response, all the line valid bits of the 2-way cache are cleared. The CACLR
bit remains 1 until the flush process is complete, at which time CACLR is
automatically reset to 0.
A DSP reset forces CACLR = 0 (no flush in process).
11
Reserved
3
2
CLKOFF
8
1
0
SMUL
SST
SPRU630C
Advertisement
Table of Contents
