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The following two operations are available to generate reset signals.
(1)
External reset input with RESET pin
(2)
Internal reset by program run-away time detected with watchdog timer
External and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each
hardware is set to the status shown in Table 12-1. Each pin has a high impedance during reset input or during
oscillation settling time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation settling time (2
cleared after reset, and program execution is started after the oscillation settling time (2
Figures 12-2 through 12-4).
Cautions 1. For an external reset, input a low level for 10 µ µ µ µ s or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
RESET
Count Clock
CHAPTER 12 RESET FUNCTION
15
/f
) has elapsed. The reset applied by the watchdog timer overflow is automatically
X
Figure 12-1. Block Diagram of Reset Function
Reset Control Circuit
User's Manual U11919EJ3V0UM00
Over-
flow
Watchdog Timer
Stop
15
/f
) has elapsed (see
X
Reset Signal
Interrupt Function
175
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