NEC mPD789026 Subseries User Manual page 118

(2) Watchdog timer mode register (WDTM)
This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
<7> 6
Symbol
WDTM RUN 0
RUN
0 Stops counting.
1 Clears counter and starts counting.
WDTM4 WDTM3
0 0
0 1
1 0
1 1
Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting 1 to RUN, the actual overflow time is up
to 0.8% shorter than the time set by timer clock select register 2 (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of
interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2
is selected under the condition where TMIF4 is 1, a non-maskable interrupt occurs at
the completion of rewriting.
118
CHAPTER 8 WATCHDOG TIMER
Figure 8-3. Watchdog Timer Mode Register Format
5 4 3
0 WDTM4 WDTM3
Selects Operation of Watchdog Timer
Selects Operation Mode of Watchdog Timer
Operation stop
Interval timer mode (overflow and maskable interrupt occur)
Watchdog timer mode 1 (overflow and non-maskable interrupt occur)
Watchdog timer mode 2 (overflow occurs and reset operation started)
User's Manual U11919EJ3V0UM00
2 1 0 Address
0 0 0 FFF9H
Note 1
Note 3
After Reset R/W
00H R/W
Note 2