Table of Contents
Advertisement
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the low-order-5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can
refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.
[Illustration]
Instruction Code
Effective Address
Effective Address + 1
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
rp
PC
62
CHAPTER 3 CPU ARCHITECTURE
7
6
5
0
1
ta
4-0
15
0
0
0
0
0
7
Memory (Table)
Low Addr.
High Addr.
15
PC
7
A
15
User's Manual U11919EJ3V0UM00
1
0
0
8
7
6
5
0
0
0
0
1
0
8
7
0
7
X
8
7
1
0
0
0
0
0
Advertisement
Chapters
Table of Contents
