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Theory of Operation
ADDER
RAM DAC
CONTROLLER
Others
A40 CPU board
3-4
U565, U570, and U575 constitute a triple buffer. The data from VARIABLE
PERSISTENCE can be written into the RAM without dead time.
U585 is a SAVE&DISP RAM. While SAVE&DISP is not in execution, U585 is
continuously writing the data into the VRAM from the inside of VARIABLE
PERSISTENCE running cycle. When the front panel's SAVE&DISP button is
pressed, U585 stops the write operation, and enters the read mode in which data
is read through the triple buffer's serial port. The data is transferred to ADDER
(U600) in synchronization with one of the triple buffer RAMs.
U580 is controlling the above RAMs, and is generating the horizontal and
vertical synchronous pulses of VGA.
When SAVE&DISP is not working, ADDER selects the RAM the contents of
which are being read through the serial port of the triple buffer (VRAM). It then
sends the data of this RAM to RAM DAC.
When the front panel's SAVE&DISP button is pressed, ADDER adds the U585
serial data to the selected data above before sending the result to RAM DAC.
RAM DAC produces the intensity signal based on the data used in ADDER.
INTENSITY can be updated by rewriting the data within the internal palette of
RAM DAC.
The main functions are (1) generating the address used to switch the coefficient
of the GF9101 within INTERPOLATE, (2) controlling the clock that will be
added to the DOUBLER controller, and (3) generating the strobe of the effective
data.
This control starts when EMPTY FLAG is negated after the data enters the FIFO.
Since this board uses reconfigurable FPGA 10K10 and 10K30, the contents of
FPGA vary with the mode.
This rule applies also to X-RAM and Y-RAM.
The A40 CPU board consists of the 68303 CPU, 128K-byte ROM, 256K-byte
RAM (with battery backup), and 8M-byte FLASH ROM.
This board has an RS-232C port, which facilitates program modification.
WFM 1125 Option 0A/0B/0C/0D Service Manual
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