Hitachi Hidic EH-150 Applications Manual page 84

Preliminary Rev.03
Error Clear Control 3 Register (EC3CR)
Bit
+8
This register is used for to clear the bits related to connection error.
Bit 15, 14, 7 and 6: Reserved
These bits are reserved bits. Please set "0" always.
Bit 13-8: SNE[6:1]clear bit (SNC[6:1])
These bits request to clear Send timeout error bit (SNE[6:1]) in Connection n error status register (CnESR).
Bit13-8: SNC[6:1]
0
1
Bit 5-0: RCE[6:1] clear bit (RCC[6:1])
These bits request to clear Open error bit (RCE[6:1]) in Connection n error status register.
Bit5-0: RCC[6:1]
0
1
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15 14 13 12 11
- -
SNC6 SNC5 SNC4 SNC3 SNC2 SNC1
Nothing is done.
Request to clear SNE[6:1] bits.
Nothing is done.
Request to clear RCE[6:1] bits.
10 9 8 7 6
- -
Description
Description
8-15
Chapter 8 Register Structure
5 4 3 2 1
RCC6 RCC5 RCC4 RCC3 RCC2 RCC1
(Initial set)
(Initial set)
0