Hitachi Hidic EH-150 Applications Manual page 83

Preliminary Rev.03
Error Clear Control 2 Register (EC2CR)
Bit
+7
This register is used for to clear the bits related to connection error.
Bit 15, 14, 7 and 6: Reserved
These bits are reserved bits. Please set "0" always.
Bit 13-8: RAE[6:1]clear bit (RAC[6:1])
These bits request to clear Send timeout error bit (RAE[6:1]) in Connection n error status register (CnESR).
Bit13-8: RAC[6:1]
0
1
Bit 5-0: DIS[6:1] clear bit (DIC[6:1])
These bits request to clear Open error bit (DIS[6:1]) in Connection n error status register.
Bit5-0: DIC[6:1]
0
1
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15 14 13 12 11
- -
RAC6 RAC5 RAC4 RAC3 RAC2 RAC1
Nothing is done.
Request to clear RAE[6:1] bits.
Nothing is done.
Request to clear DIS[6:1] bits.
10 9 8 7 6
- -
Description
Description
8-14
Chapter 8 Register Structure
5 4 3 2 1
DIC6 DIC5 DIC4 DIC3 DIC2 DIC1
(Initial set)
(Initial set)
0