Hitachi Hidic EH-150 Applications Manual page 82

Preliminary Rev.03
Error Clear Control 1 Register (EC1CR)
Bit
+6
This register is used for to clear the bits related to connection error.
Bit 15, 14, 7 and 6: Reserved
These bits are reserved bits. Please set "0" always.
Bit 13-8: STE[6:1]clear bit (TEC[6:1])
These bits request to clear Send timeout error bit (STE[6:1]) in Connection n error status register (CnESR).
Bit13-8: TEC[6:1]
0
1
Bit 5-0: OE[6:1] clear bit (OEC[6:1])
These bits request to clear Open error bit (OE[6:1]) in Connection n error status register.
Bit5-0: OEC[6:1]
0
1
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15 14 13 12 11
- -
TEC6 TEC5 TEC4 TEC3 TEC2 TEC1
Nothing is done.
Request to clear STE[6:1] bits.
Nothing is done.
Request to clear OE[6:1] bits.
10 9 8 7 6
- -
Description
Description
8-13
Chapter 8 Register Structure
5 4 3 2 1
OEC6 OEC5 OEC4 OEC3 OEC2 OEC1
(Initial set)
(Initial set)
0