Table of Contents
Advertisement
CSI Camera Connector
SBC-C20 with NXP iMX8M Processor includes an Image Processing Subsystem, that can be used for video applications, like video-preview,
video recording and frame grabbing.
It is possible to access to the video input port through an FFC/FPC connector, type HIROSE p/n FH12-18S-0.5SH(55) which is able to
accept 18 poles 0.5mm pitch FFC cables.
CSI Camera Connector
Pin
Signal
Pin
1
CSI_P1_DN3
10
2
CSI_P1_DP3
11
3
CSI_P1_DN2
12
4
CSI_P1_DP2
13
5
CSI_P1_DN1
14
6
CSI_P1_DP1
15
7
CSI_P1_CKN
16
8
CSI_P1_CKP
17
9
GND
18
MIPI_CSI0_I2C0_SCL: general purpose I2C Bus clock line. Output signal, electrical level VDD_3P3V with a 2k2
I2C controller #2.
MIPI_CSI0_I2C0_SDA: general purpose I2C Bus data line. Bidirectional signal, electrical level VDD_3P3V with a 2k2
processor s I2C controller #2.
MIPI_CSI0_RST_B: External camera module reset signal output, it is an active low signal.
SBC-C20
SBC-C20 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. -Copyright © 2020 SECO S.p.A.
The pinout of this connector is shown in the table on the left. All CSI differential pairs are managed
CN28
Signal
CSI_P1_DP0 / CSI_P1_DN0: CSI2 Camera serial input, Receiving Input Differential pair #0.
CSI_P1_DN0
CSI_P1_DP1 / CSI_P1_DN1: CSI2 Camera serial input, Receiving Input Differential pair #1.
CSI_P1_DP0
CSI_P1_DP2 / CSI_P1_DN2: CSI2 Camera serial input, Receiving Input Differential pair #2.
GND
CSI_P1_DP3 / CSI_P1_DN3: CSI2 Camera serial input, Receiving Input Differential pair #3.
MIPI_CSI0_EN
CSI_P1_CKP / CSI_P1_CKN: CSI Camera, Clock input differential pair.
MIPI_CSI0_MCKL_OUT
MIPI_CSI0_EN: External camera module Power enable signal. It is an active high signal with electrical
MIPI_CSI0_I2C0_SCL
level VDD_3P3V.
MIPI_CSI0_I2C0_SDA
MIPI_CSI0_MCKL_OUT: Master Clock, it is managed by i.MX8M GPIO_15 pin. It is suggested,
MIPI_CSI0_RST_B
however, to use camera modules with onboard crystal / oscillator, and avoid using this signal.
Indeed, it could cause problems for EMI compliance requirements.
VDD_3P3V
-up resistor. It is managed by i.MX8M processor s
-up resistor. It is managed by i.MX8M
31
Advertisement
Table of Contents
