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M.2 Socket 2 Key B Slot
M.2 WWAN Slot (Socket 2 Key B type 3042/2260- CN26)
Pin
Signal
Pin
1
---
2
3
GND
4
5
GND
6
7
USB_P2-
8
9
USB_P2+
10
11
GND
20
21
---
22
23
---
24
25
---
26
27
GND
28
29
---
30
31
---
32
33
GND
34
35
---
36
37
---
38
39
GND
40
41
PCIe1_Rx0+
42
43
PCIe1_Rx0-
44
45
GND
46
47
PCIe1_Tx0-
48
49
PCIe1_Tx0+
50
51
GND
52
53
DIF1#_REF_CLK
54
55
DIF1_REF_CLK
56
57
GND
58
SBC-C20
SBC-C20 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. -Copyright © 2020 SECO S.p.A.
SBC-C20 provide a M.2 WWAN Slot, which allow the
connection of Connectivity modules, using PCI-e
interface or USB 2.0 interface.
Signal
The connector used for the M.2 WWAN slot is CN26,
VDD_3P3V
which is a standard 75 pin M.2 Key B connector, type
VDD_3P3V
LOTES p/n APCI0087-P001A, H=8.5mm, with the
---
pinout shown in the table on the left.
W_DISABLE1#
It is possible to place directly modules in 2260 size, buy
---
using the tallest Threaded Spacer mounted onboard.
It is possible to place also modules in 2242 / 3042 size,
---
by using a M/F Spacer which allow fixing the module on the lower spacer soldered on the PCB,
---
deemed for the fixing of shorter modules.
---
Here following the signals related to the PCI-e interface:
---
PCIe1_Tx0+/PCIe1_Tx0-: PCI Express port #1 lane #0, Transmitting Output Differential pair
---
PCIe1_Rx0+/PCIe1_Rx0-: PCI Express port #1 lane #0, Receiving Input Differential pair
UIM_RESET
UIM_CLK
DIF1#_REF_CLK / DIF1_REF_CLK: PCI Express Reference Clock for lane #0, Differential Pair
UIM_DATA
PCIE_RST#: Reset Signal that is sent from the i.MX8M processor to the PCI-e devices available
UIM_PWR
on the module. It is a VDD_3P3V active-low signal.
---
PCIe_CLQREQ#: PCI Express Clock Request Input, active low signal, electrical level
---
VDD_3P3V. This signal shall be driven low by any module inserted in the connectivity slot, in
---
order to ensure that the SoC makes available the reference clock.
---
---
the Connectivity module plugged in the slot when it requires waking up the system.
---
Here following the signals related to the USB interface:
PCIE_RST#
USB_P2+/USB_P2-: USB 2.0 Port #2 differential pair. It is managed by the optional SMSC
PCIe_CLQREQ#
PCIe_WAKE#
---
---
VDD_3P3V active low signal. It must be externally driven by
2.
29
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