Dual Alternate Trigger Mode; Description; Example Of Application; Figure 11. Dual Alternate Trigger Mode - ST STM32 Application Note

AN3116
With T = 13.5 cycles, the maximum allowed impedance of the source (R
s
the source has an impedance R
With a single ADC and with T
not satisfied. By using two ADCs, we have thus extended the impedance margin from
1.2 k to 19 k.
With the dual slow interleaved ADC mode, the 1 Msamples/second sampling rate is
achieved with higher input impedances.
2.4

Dual alternate trigger mode

2.4.1

Description

The dual alternate trigger ADC mode can be used only on an injected channel group. In this
mode, ADC1 and ADC2 alternately convert the injected channels on the same external
trigger. When the first trigger occurs, all injected group channels in ADC1 are converted.
When the second trigger happens, all injected group channels in ADC2 are converted and
so on. The maximum number of injected channels in the group is 4 for each ADC.
Note: An example of firmware is provided with this application note: Dual_AlternateTrigger.

Figure 11. Dual alternate trigger mode

2.4.2

Example of application

The dual alternate trigger mode makes it possible to have sampling points as close as
possible to each other (down to 1.5 ADC cycles). This is interesting for instance in motor
control applications, where a single-shunt sensor is used for three-phase current reading. In
some cases, the PWM duty cycle of the power stage has to be limited to maintain a
minimum time slot for two consecutive conversions. If the sampling points are as close as
possible, the PWM duty cycle is maximized, which increases the voltage applied to the
motor.
= 10 k < 19 k the impedance condition is respected.
AIN
= 1.5 (corresponding to 1.2 k), the impedance condition is
s
Doc ID 16840 Rev 1
Dual modes
) is 19 k. Since
AIN
13/18