ABB Relion 650 Series Operation Manual page 19

1MRK 500 096-UUS B
IEC 61850 or Function ANSI
name
ZCPSCH 85
ZCRWPSCH 85
ZCWSPSCH 85
ZCLCPLAL
ECPSCH 85
ECRWPSCH 85
Logic
SMPPTRC 94
SPTPTRC 94
TMAGGIO
OR
INVERTER
PULSETIMER
GATE
XOR
LOOPDELAY
TimerSet
AND
SRMEMORY
RSMEMORY
ANDQT
ORQT
INVERTERQT
XORQT
SRMEMORYQT
RSMEMORYQT
TIMERSETQT
PULSETIMERQT
INVALIDQT
INDCOMBSPQT
INDEXTSPQT
FXDSIGN
B16I
B16IFCVI
IB16A
IB16FCVB
TEIGGIO
Monitoring
Table continues on next page
650 series
Operation manual
Function description
Scheme communication logic with delta based blocking scheme signal transmit
Current reversal and WEI logic for distance protection, 3-phase
Current reversal and WEI logic for distance protection, phase segregated
Local acceleration logic
Scheme communication logic for residual overcurrent protection
Current reversal and weak end infeed logic for residual overcurrent protection
Tripping logic, common 3-phase output
Tripping logic, phase segregated output
Trip matrix logic
Configurable logic blocks, OR
Configurable logic blocks, inverter
Configurable logic blocks, PULSETIMER
Configurable logic blocks, controllable gate
Configurable logic blocks, exclusive OR
Configurable logic blocks, loop delay
Configurable logic blocks, timer
Configurable logic blocks, AND
Configurable logic blocks, set-reset memory
Configurable logic blocks, reset-set memory
Configurable logic Q/T, ANDQT
Configurable logic Q/T, ORQT
Configurable logic Q/T, INVERTERQT
Configurable logic Q/T, XORQT
Configurable logic Q/T, set-reset with memory
Configurable logic Q/T, reset-set with memory
Configurable logic Q/T, settable timer
Configurable logic Q/T, pulse timer
Configurable logic Q/T, INVALIDQT
Configurable logic Q/T, single-indication signal combining
Configurable logic Q/T, single-indication signal extractor
Fixed-signal function block
Boolean 16 to Integer conversion
Boolean 16 to Integer conversion with logic node representation
Integer to Boolean 16 conversion
Integer to boolean 16 conversion with logic node representation
Elapsed time integrator with limit transgression and overflow supervision
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Section 1
Introduction
13