Exception Stack Frame Definition - Freescale Semiconductor ColdFire MCF5213 Reference Manual

ColdFire Core
Vector
Number(s)
0
1
2
3
4
5
6–7
8
9
10
11
12
13
14
15–23
24
25–31
32–47
48–63
64–255
1
Fault refers to the PC of the instruction that caused the exception; Next refers to the PC
of the next instruction that follows the instruction that caused the fault.
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR)
that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine which services multiple interrupt
requests with different interrupt levels. For more details see ColdFire Family Programmer's Reference
Manual.
3.4.1

Exception Stack Frame Definition

Figure 3-9 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
3-10
Table 3-5. Exception Vector Assignments
Stacked
Vector
Program
Offset (Hex)
Counter
0x000 —
0x004 —
0x008 Fault
0x00C Fault
0x010 Fault
0x014 Fault
0x018–0x01C —
0x020 Fault
0x024 Next
0x028 Fault
0x02C Fault
0x030 Next
0x034 —
0x038 Fault
0x03C–0x05C —
0x060 Next
0x064–0x07C —
0x080–0x0BC Next
0x0C0–0x0FC —
0x100–0x3FC Next
Assignment
Initial supervisor stack pointer
Initial program counter
Access error
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-a opcode
Unimplemented line-f opcode
Debug interrupt
Reserved
Format error
Reserved
Spurious interrupt
Reserved
Trap # 0-15 instructions
Reserved
Device-specific interrupts
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