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Freescale Semiconductor MC9S12DJ128E User Manual

Mc9s12dt128 device hcs12 microcontrollers
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MC9S12DT128
Device User Guide
Covers MC9S12DT128E, MC9S12DG128E,
MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,
MC9S12DB128, MC9S12A128, SC515846, SC515847,
SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204,
SC102205
HCS12
Microcontrollers
9S12DT128DGV2/D
V02.16
12 APR 2008
freescale.com

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Summary of Contents for Freescale Semiconductor MC9S12DJ128E

  • Page 1 MC9S12DT128 Device User Guide Covers MC9S12DT128E, MC9S12DG128E, MC9S12DJ128E, MC9S12DG128, MC9S12DJ128, MC9S12DB128, MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, SC102205 HCS12 Microcontrollers 9S12DT128DGV2/D V02.16 12 APR 2008 freescale.com...
  • Page 2 Improved BDM with sync and acknowledge capabilities New Part ID number Improvements: Significantly improved NVM reliability data Corrections: Interrupt vector Table 01 Feb 01 Feb Updated Block User Guide versions in preface V02.01 2002 2002 Updated Appendix A Electrical Characteristics Freescale Semiconductor...
  • Page 3 Table 5.1 Interrupt Vector Locations Section HCS12 Core Block Description: mentioned alternate clock of BDM to be equivalent to oscillator clock Added new section: “Oscillator (OSC) Block Description” Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz Freescale Semiconductor...
  • Page 4 Characteristics” Added part numbers MC9S12DT128E, MC9S12DG128E, and 26 Feb 26 Feb V02.08 MC9S12DJ128E in “Preface” and related part number references 2003 2003 Removed mask sets 0L40K and 2L40K from Table 1-3 Replaced references to HCS12 Core Guide by the individual HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;...
  • Page 5 Javg footnote concerning data retention 05 Oct 05 Oct Updated “NVM Reliability” table A-12 format with added data. V02.15 2005 2005 Added figure A-2 “Typical Endurance vs Temperature” 12 Apr 12 Apr V02.16 Added maskset 2L94R 2008 2008 Freescale Semiconductor...
  • Page 6 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 7 PH7 / KWH7 — Port H I/O Pin 7 ........67 Freescale Semiconductor...
  • Page 8 PS0 / RXD0 — Port S I/O Pin 0 ........72 Freescale Semiconductor...
  • Page 9 CPU Block Description ..........85 Freescale Semiconductor...
  • Page 10 Device-specific information..........88 Section 16 Pulse Width Modulator (PWM) Block Description Section 17 Flash EEPROM 128K Block Description Section 18 EEPROM 2K Block Description Section 19 RAM Block Description Freescale Semiconductor...
  • Page 11 Slave Mode ........... . 131 Freescale Semiconductor...
  • Page 12 80-pin QFP package..........139 Freescale Semiconductor...

  • Page 13: Table Of Contents

    Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Bondout ......59...
  • Page 14 Figure A-10 General External Bus Timing........134 Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) ....138 Freescale Semiconductor...
  • Page 15 $0110 - $011B EEPROM Control Register (eets2k) ............44 $011C - $011F Reserved for RAM Control Register ............45 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ........ 45 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..........46 Freescale Semiconductor...
  • Page 16 Table A-17 MSCAN Wake-up Pulse Characteristics ......127 Table A-18 SPI Master Mode Timing Characteristics......130 Freescale Semiconductor...
  • Page 17 Table A-19 SPI Slave Mode Timing Characteristics ......132 Table A-20 Expanded Bus Timing Characteristics ......135 Freescale Semiconductor...
  • Page 18 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 19 (Table 0-1) and (Table 0-2) show the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Derivative Differences MC9S12DT128E MC9S12DG128E MC9S12DJ128E MC9S12DT128 MC9S12DG128 MC9S12DJ128 Modules...

  • Page 20: Figure 0-1 Order Partnumber Example

    SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 is the same; MC9S12DB128, SC515846, and SC102202 have a different bond-out. 3. Part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E are associated with the mask set 1L40K. 4. Part numbers SC515846, SC515847, SC515848, and SC515849 are associated with the mask set 4L40K.
  • Page 21 – Do not write MODRR3 and MODRR2 Bit of Module Routing Register (PIM_9DTB128 Block User Guide), if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128, • MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Freescale Semiconductor...
  • Page 22 PM1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. Freescale Semiconductor...
  • Page 23 Byte Level Data Link Controller -J1850 (BDLC) Block User Guide S12BDLCV1/D Motorola Scalable CAN (MSCAN) Block User Guide S12MSCANV2/D Voltage Regulator (VREG) Block User Guide S12VREGV1/D Port Integration Module (PIM_9DTB128) Block User Guide S12DTB128PIMV2/D Byteflight (BF) Block User Guide S12BFV1/D Freescale Semiconductor...
  • Page 24 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 25 – BDM (Background Debug Module) • CRG (Clock and Reset Generator) – Choice of low current Colpitts oscillator or standard Pierce Oscillator – PLL – COP watchdog – real time interrupt – clock monitor • 8-bit and 4-bit ports with interrupt functionality Freescale Semiconductor...
  • Page 26 – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs • Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – Two Synchronous Serial Peripheral Interface (SPI) – Byteflight • Byte Data Link Controller (BDLC) Freescale Semiconductor...
  • Page 27 Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Freescale use only) – Special Peripheral Mode (Freescale use only) Low power modes • Stop Mode • Pseudo Stop Mode • Wait Mode Freescale Semiconductor...
  • Page 28 Device User Guide — 9S12DT128DGV2/D V02.16 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT128 device. Freescale Semiconductor...

  • Page 29: Figure 1-1 Mc9S12Dt128 Block Diagram

    KWP2 PWM3 KWP3 A/D Converter 5V & PWM4 KWP4 PLL 2.5V Voltage Regulator Reference PWM5 KWP5 PWM6 KWP6 DDPLL PWM7 KWP7 SSPLL MISO KWH0 MOSI KWH1 Voltage Regulator 5V & I/O KWH2 SPI1 KWH3 KWH4 KWH5 KWH6 KWH7 Freescale Semiconductor...
  • Page 30 $0000 – $07FF EEPROM array 2048 $0000 – $1FFF RAM array 8192 Fixed Flash EEPROM array $4000 – $7FFF 16384 incl. 0.5K, 1K, 2K or 4K Protected Sector at start $8000 – $BFFF Flash EEPROM Page Window 16384 Freescale Semiconductor...

  • Page 31: Figure 1-2 Mc9S12Dt128 Memory Map

    SINGLE CHIP SINGLE CHIP The address does not show the map after reset, but a useful map. After reset the map is: $0000 – $03FF: Register Space $0000 – $1FFF: 8K RAM $0000 – $07FF: 2K EEPROM (not visible) Freescale Semiconductor...
  • Page 32 INITRM RAM15 RAM14 RAM13 RAM12 RAM11 RAMHAL Write: Read: $0011 INITRG REG14 REG13 REG12 REG11 Write: Read: $0012 INITEE EE15 EE14 EE13 EE12 EE11 EEON Write: Read: $0013 MISC EXSTR1 EXSTR0 ROMHM ROMON Write: Read: $0014 Reserved Write: Freescale Semiconductor...
  • Page 33 Write: $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $001E INTCR IRQE IRQEN Write: Freescale Semiconductor...
  • Page 34 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0032 PORTK Bit 7 Bit 0 Write: Read: $0033 DDRK Bit 7 Bit 0 Write: Freescale Semiconductor...
  • Page 35 TCNT (hi) Write: Read: Bit 7 Bit 0 $0045 TCNT (lo) Write: Read: $0046 TSCR1 TSWAI TSFRZ TFFCA Write: Read: $0047 TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 Write: Read: $0048 TCTL1 Write: Read: $0049 TCTL2 Write: Freescale Semiconductor...
  • Page 36 Bit 15 Bit 8 Write: Read: $005F TC7 (lo) Bit 7 Bit 0 Write: Read: $0060 PACTL PAEN PAMOD PEDGE CLK1 CLK0 PAOVI Write: Read: $0061 PAFLG PAOVF PAIF Write: Read: $0062 PACN3 (hi) Bit 7 Bit 0 Write: Freescale Semiconductor...
  • Page 37 Bit 0 Write: Read: Bit 15 Bit 8 $0078 TC0H (hi) Write: Read: Bit 7 Bit 0 $0079 TC0H (lo) Write: Read: Bit 15 Bit 8 $007A TC1H (hi) Write: Read: Bit 7 Bit 0 $007B TC1H (lo) Write: Freescale Semiconductor...
  • Page 38 $008B ATD0STAT1 Write: Read: $008C Reserved Write: Read: $008D ATD0DIEN Bit 7 Bit 0 Write: Read: $008E Reserved Write: Read: Bit7 BIT 0 $008F PORTAD0 Write: Read: Bit15 Bit8 $0090 ATD0DR0H Write: Read: Bit7 Bit6 $0091 ATD0DR0L Write: Freescale Semiconductor...
  • Page 39 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Write: Read: $00A5 PWMCTL CON67 CON45 CON23 CON01 PSWAI PFRZ Write: Read: PWMTST $00A6 Test Only Write: Read: PWMPRSC $00A7 Test Only Write: Read: $00A8 PWMSCLA Bit 7 Bit 0 Write: Freescale Semiconductor...
  • Page 40 PWMDTY1 Bit 7 Bit 0 Write: Read: $00BE PWMDTY2 Bit 7 Bit 0 Write: Read: $00BF PWMDTY3 Bit 7 Bit 0 Write: Read: $00C0 PWMDTY4 Bit 7 Bit 0 Write: Read: $00C1 PWMDTY5 Bit 7 Bit 0 Write: Freescale Semiconductor...
  • Page 41 SBR11 SBR10 SBR9 SBR8 Write: Read: $00D1 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Write: Read: $00D2 SCI1CR1 LOOPS SCISWAI RSRC WAKE Write: Read: $00D3 SCI1CR2 TCIE ILIE Write: Read: TDRE RDRF IDLE $00D4 SCI1SR1 Write: Freescale Semiconductor...
  • Page 42 IBC1 IBC0 Write: Read: $00E2 IBCR IBEN IBIE MS/SL TX/RX TXAK IBSWAI Write: RSTA Read: IAAS RXAK $00E3 IBSR IBAL IBIF Write: Read: $00E4 IBDR Write: Read: $00E5 Reserved Write: Read: $00E6 Reserved Write: Read: $00E7 Reserved Write: Freescale Semiconductor...
  • Page 43 Bit0 Write: Read: $00F6 Reserved Write: Read: $00F7 Reserved Write: $00F8 - $00FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $00F8 - Reserved $00FF Write: Freescale Semiconductor...
  • Page 44 Read: $0114 EPROT EPOPEN EPDIS Write: Read: CCIF $0115 ESTAT CBEIF PVIOL ACCERR BLANK Write: Read: $0116 ECMD CMDB6 CMDB5 CMDB2 CMDB0 Write: Reserved for Read: $0117 Factory Test Write: Read: $0118 EADDRHI Bit 9 Bit 8 Write: Freescale Semiconductor...
  • Page 45 $012A Reserved Write: Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 $012B ATD1STAT1 Write: Read: $012C Reserved Write: Read: $012D ATD1DIEN Bit 7 Bit 0 Write: Read: $012E Reserved Write: Read: Bit7 BIT 0 $012F PORTAD1 Write: Freescale Semiconductor...
  • Page 46 BRP1 BRP0 Write: Read: $0143 CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 $0144 CAN0RFLG WUPIF CSCIF OVRIF Write: Read: $0145 CAN0RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Freescale Semiconductor...

  • Page 47: Table 1-2 Detailed Mscan Foreground Receive And Transmit Buffer Layout

    ID15 $xxx1 Standard ID Read: IDE=0 CANxRIDR1 Write: Extended ID Read: ID14 ID13 ID12 ID11 ID10 $xxx2 Standard ID Read: CANxRIDR2 Write: Extended ID Read: $xxx3 Standard ID Read: CANxRIDR3 Write: Read: $xxx4- CANxRDSR0 - $xxxB CANxRDSR7 Write: Freescale Semiconductor...
  • Page 48 LISTEN WUPM Write: Read: $0182 CAN1BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: $0183 CAN1BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 $0184 CAN1RFLG WUPIF CSCIF OVRIF Write: Freescale Semiconductor...
  • Page 49 Bit 1 Bit 0 Read: $01C0 - Reserved $01FF Write: $0200 - $023F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $020C - Reserved $023F Write: Freescale Semiconductor...
  • Page 50 PPSM3 PPSM2 PPSM1 PPSM0 Write: Read: $0256 WOMM WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 Write: Read: $0257 MODRR MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 Write: Read: $0258 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Write: Freescale Semiconductor...
  • Page 51 Read: $026C PERJ PERJ7 PERJ6 PERJ1 PERJ0 Write: Read: $026D PPSJ PPSJ7 PPSJ6 PPSJ1 PPSJ0 Write: Read: $026E PIEJ PIEJ7 PIEJ6 PIEJ1 PIEJ0 Write: Read: $026F PIFJ PIFJ7 PIFJ6 PIFJ1 PIFJ0 Write: Read: $0270 - Reserved $027F Write: Freescale Semiconductor...
  • Page 52 $0298 - CAN0IDAR4 - Read: $029B CAN0IDAR7 Write: $029C - CAN0IDMR4 - Read: $029F CAN0IDMR7 Read: FOREGROUND RECEIVE BUFFER see (Table 1-2) $02A0 - CAN4RXFG $02AF Write: Read: $02B0 - CAN4TXFG FOREGROUND TRANSMIT BUFFER see (Table 1-2) $02BF Write: Freescale Semiconductor...
  • Page 53 Reserved Write: Read: $0310 BFPCTLBF PMEREN PSLMEN PERREN PROKEN PSYNEN BFEN Write: Read: $0311 Reserved Write: TXBUFL RXBUFL Read: $0312 BFBUFLOCK Write: Read: $0313 Reserved Write: Read: $0314 BFFIDRJ FIDRJ7 FIDRJ6 FIDRJ5 FIDRJ4 FIDRJ3 FIDRJ2 FIDRJ1 FIDRJ0 Write: Freescale Semiconductor...
  • Page 54 LEN1 LEN0 Write: $0342 - BFFDATA0- Read: DATA 7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 $034D BFFDATA11 Write: Read: $034E - Reserved $034F Write: $0350 - BFBUFCTL0 - Read: ABTAK IFLG IENA LOCK ABTRQ $035F BFBUFCTL15 Write: Freescale Semiconductor...

  • Page 55: Table 1-3 Assigned Part Id Numbers

    The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details. Table 1-4 Memory size registers Register name Value MEMSIZ0 MEMSIZ1 Freescale Semiconductor...
  • Page 56 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 57 The MC9S12DT128 and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1, Figure 2-2, and Figure 2-3 show the pin assignments for different packages. Freescale Semiconductor...

  • Page 58: Figure 2-1 Pin Assignments 112 Lqfp For Mc9S12Dt128E, Mc9S12Dt128

    PA0/ADDR8/DATA8 Signals shown in Bold are not available on all the 80 pin package options Signals shown in Bold-Italics are not available on the MC9S12DJ128E, MC9S12DJ128, MC9S12DG128E, MC9S12DG128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 80 pin package options...

  • Page 59: Figure 2-2 Pin Assignments In 80 Qfp For Mc9S12Dg128E, Mc9S12Dg128

    80 QFP IOC6/PT6 PA7/ADDR15/DATA15 IOC7/PT7 PA6/ADDR14/DATA14 MODC/TAGHI/BKGD PA5/ADDR13/DATA13 ADDR0/DATA0/PB0 PA4/ADDR12/DATA12 ADDR1/DATA1/PB1 PA3/ADDR11/DATA11 ADDR2/DATA2/PB2 PA2/ADDR10/DATA10 ADDR3/DATA3/PB3 PA1/ADDR9/DATA9 ADDR4/DATA4/PB4 PA0/ADDR8/DATA8 Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Bondout Freescale Semiconductor...

  • Page 60: Figure 2-3 Pin Assignments In 80 Qfp For Mc9S12Db128, Sc515846, And Sc102202 Bondout

    (Table 2-1) summarizes the pin functionality. Signals shown in Bold are not available on all the 80-pin package options. Signals shown in Bold-Italics are not available on the MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 80-pin package options. Signals shown in Italics are not available on MC9S12DB128, SC515846, and SC102202 80-pin package options.

  • Page 61: Table 2-1 Signal Properties

    — — — VDDR PUPEE expanded modes Port E Input, — — — VDDR Maskable Interrupt Port E Input, Non XIRQ — — — VDDR Maskable Interrupt PERH/ KWH7 — — VDDR Disabled Port H I/O, Interrupt PPSH Freescale Semiconductor...
  • Page 62 SPI0 Port M I/O, TX of BF, PERM/ TX_BF TXCAN1 TXCAN0 VDDX Disabled CAN1, CAN0, SS of PPSM SPI0 Port M I/O, RX of BF, PERM/ RX_BF RXCAN1 RXCAN0 MISO0 VDDX Disabled CAN1, CAN0, MISO PPSM of SPI0 Freescale Semiconductor...
  • Page 63 Port S I/O, RXD of RXD0 — — — VDDX PPSS SCI0 PERT/ Port T I/O, Timer PT[7:0] IOC[7:0] — — — VDDX Disabled PPST channels NOTES: 1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide. Freescale Semiconductor...

  • Page 64: Figure 2-4 Pll Loop Filter Connections

    It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device. Freescale Semiconductor...
  • Page 65 If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL. Freescale Semiconductor...

  • Page 66: Figure 2-5 Colpitts Oscillator Connections (Pe7=1)

    XTAL VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 2-6 Pierce Oscillator Connections (PE7=0) EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) XTAL not connected Figure 2-7 External Clock Connections (PE7=0) Freescale Semiconductor...
  • Page 67 This will wake up the MCU from STOP or WAIT mode. 2.3.20 PH7 / KWH7 — Port H I/O Pin 7 PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. Freescale Semiconductor...
  • Page 68 STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial clock pin SCL of the IIC module. Freescale Semiconductor...
  • Page 69 Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). Freescale Semiconductor...
  • Page 70 PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. Freescale Semiconductor...
  • Page 71 Peripheral Interface 0 (SPI0). 2.3.50 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). Freescale Semiconductor...

  • Page 72: Table 2-2 Mc9S12Dt128 Power And Ground Connection Summary

    MC9S12DT128 power and ground pins are described below. Table 2-2 MC9S12DT128 Power and Ground Connection Summary Pin Number Nominal Mnemonic Description Voltage 112-pin QFP VDD1, 2 13, 65 2.5V Internal power and ground generated by internal regulator VSS1, 2 14, 66 Freescale Semiconductor...
  • Page 73 MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors. Freescale Semiconductor...
  • Page 74 NOTE: No load allowed except for bypass capacitors. 2.4.7 VREGEN — On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. Freescale Semiconductor...

  • Page 75: Figure 3-1 Clock Connections

    Consult the CRG Block User Guide for details on clock generation. HCS12 CORE MEBI core clock Flash EEPROM EXTAL ATD0, 1 bus clock SCI0, SCI1 oscillator clock SPI0, 1 XTAL CAN0, 1, 4 BDLC Figure 3-1 Clock Connections Freescale Semiconductor...
  • Page 76 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 77: Table 4-1 Mode Selection

    Normal Expanded Wide, BDM allowed For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide. Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS Description Colpitts Oscillator selected Pierce Oscillator/external clock selected Freescale Semiconductor...

  • Page 78: Table 4-3 Voltage Regulator Vregen

    4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. Freescale Semiconductor...
  • Page 79 The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks. 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. Freescale Semiconductor...
  • Page 80 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 81: Table 5-1 Interrupt Vector Locations

    SCICR2 $FFD4, $FFD5 SCI1 I-Bit (TIE, TCIE, RIE, ILIE) $FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $FFD0, $FFD1 ATD1 I-Bit ATDCTL2 (ASCIE) PIEJ $FFCE, $FFCF Port J I-Bit (PIEJ7, PIEJ6, PIEJ1, PIEJ0) $FFCC, $FFCD Port H I-Bit PIEH (PIEH7-0) Freescale Semiconductor...
  • Page 82 Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. Freescale Semiconductor...
  • Page 83 Refer to Table 2-1 for affected pins. 5.3.2 Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. Freescale Semiconductor...
  • Page 84 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 85 • MEMSIZ1 – Reset state: $80 6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module. 6.3.1 Device-specific information • PUCR – Reset state: $90 Freescale Semiconductor...
  • Page 86 Consult the OSC Block User Guide for information about the Oscillator module. 8.1 Device-specific information — The XCLKS input signal is active low (see 2.3.12 PE / NOACC / XCLKS Port E I/O Pin 7). Section 9 Enhanced Capture Timer (ECT) Block Description Freescale Semiconductor...
  • Page 87 Section 14 J1850 (BDLC) Block Description Consult the BDLC Block User Guide for information about the J1850 module. Section 15 Byteflight (BF) Block Description Consult the BF Block User Guide for information about the 10 Mbps Byteflight module. Freescale Semiconductor...
  • Page 88 Section 21 Port Integration Module (PIM) Block Description Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module. Section 22 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator. Freescale Semiconductor...

  • Page 89: Table 23-1 Suggested External Component Values

    C8, C11 and Q1 as small as possible. • Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. • Central power input should be fed in at the VDDA/VSSA pins. Freescale Semiconductor...

  • Page 90: Figure 23-1 Recommended Pcb Layout For 112Lqfp Colpitts Oscillator

    Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VSSA VSSX VDDA VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL Freescale Semiconductor...

  • Page 91: Figure 23-2 Recommended Pcb Layout For 80Qfp

    Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Colpitts Oscillator VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSR VDDR VSSPLL VDDPLL Freescale Semiconductor...

  • Page 92: Figure 23-3 Recommended Pcb Layout For 112Lqfp Pierce Oscillator

    Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VSSA VSSX VDDA VDD1 VSS1 VSS2 VDD2 VSSR VSSPLL VDDR VDDPLL Freescale Semiconductor...

  • Page 93: Figure 23-4 Recommended Pcb Layout For 80Qfp

    Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Pierce Oscillator VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSPLL VSSR VDDR VSSPLL VDDPLL Freescale Semiconductor...
  • Page 94 Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and SC102202) Pierce Oscillator VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSPLL VSSR VDDR VSSPLL VDDPLL Freescale Semiconductor...
  • Page 95 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 96 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 97 VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. Freescale Semiconductor...
  • Page 98 Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Freescale Semiconductor...

  • Page 99: Table A-1 Absolute Maximum Ratings

    All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. Freescale Semiconductor...

  • Page 100: Table A-2 Esd And Latch-Up Test Conditions

    This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature T and the junction temperature T . For power dissipation Freescale Semiconductor...

  • Page 101: Table A-4 Operating Conditions

    Power dissipation and thermal characteristics are closely related. The user must assure that the maximum ) in °C can be operating junction temperature is not exceeded. The average chip-junction temperature (T obtained from: P D Θ JA • Junction Temperature, [°C ] Ambient Temperature, [°C ] Freescale Semiconductor...
  • Page 102 (Table A-7) and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. ∑ ⋅ P IO R DSON I IO Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. Freescale Semiconductor...

  • Page 103: Table A-5 Thermal Package Characteristics

    2. PC Board according to EIA/JEDEC Standard 51-3 3. PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor...

  • Page 104: Table A-6 5V I/O Characteristics

    1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. Freescale Semiconductor...

  • Page 105: Table A-7 Supply Current Characteristics

    Pseudo Stop Current (RTI and COP enabled) -40°C 27°C 70°C µA DDPS 85°C 105°C 1200 125°C 1500 140°C Stop Current -40°C 27°C 70°C 85°C µA 1200 “C” Temp Option 100°C 105°C 1700 “V” Temp Option 120°C 125°C 5000 “M” Temp Option 140°C Freescale Semiconductor...
  • Page 106 Device User Guide — 9S12DT128DGV2/D V02.16 NOTES: 1. PLL off, Oscillator in Colpitts Mode 2. At those low power dissipation levels T can be assumed Freescale Semiconductor...

  • Page 107: Table A-8 Atd Operating Characteristics

    A.2.2.1 Source Resistance: Due to the input pin leakage current as specified in (Table A-6) in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R Freescale Semiconductor...

  • Page 108: Table A-9 Atd Electrical Characteristics

    Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Unit C Max input Source Resistance KΩ Total Input Capacitance Non Sampling Sampling C Disruptive Analog Input Current -2.5 C Coupling Ratio positive current injection C Coupling Ratio negative current injection Freescale Semiconductor...

  • Page 109: Table A-10 Atd Conversion Performance

    – – DNL i ( ) ----------------------- - 1 – 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: – ∑ INL n ( ) DNL i ( ) ------------------- - n – 1LSB Freescale Semiconductor...

  • Page 110: Figure A-1 Atd Accuracy Definitions

    10-Bit Transfer Curve 8-Bit Transfer Curve 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Figure A-1 ATD Accuracy Definitions NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10. Freescale Semiconductor...
  • Page 111 The time to program a whole row is: ⋅ 31 t brpgm swpgm bwpgm Row programming is more than 2 times faster than single word programming. A.3.1.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes: Freescale Semiconductor...

  • Page 112: Table A-11 Nvm Timing Characteristics

    4. Row Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block Freescale Semiconductor...
  • Page 113 The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Freescale Semiconductor...

  • Page 114: Table A-12 Nvm Reliability Characteristics

    3. Spec table quotes typical endurance evaluated at 25°C for this product family, typical endurance at various temperature can be estimated using the graph below. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. Freescale Semiconductor...

  • Page 115: Figure A-2 Typical Endurance Vs Temperature

    Device User Guide — 9S12DT128DGV2/D V02.16 Figure A-2 Typical Endurance vs Temperature Operating Temperature T [°C] ------ Flash ------ EEPROM Freescale Semiconductor...
  • Page 116 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 117: Table A-13 Voltage Regulator Recommended Load Capacitances

    The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Symbol Unit Load Capacitance on VDD1, 2 LVDD Load Capacitance on VDDPLL LVDDfcPLL Freescale Semiconductor...
  • Page 118 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 119: Table A-14 Startup Characteristics

    CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.5.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. Freescale Semiconductor...
  • Page 120 CQOUT internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time t . The device also features a clock monitor. A UPOSC Freescale Semiconductor...

  • Page 121: Table A-15 Oscillator Characteristics

    The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Freescale Semiconductor...

  • Page 122: Figure A-3 Basic Pll Functional Diagram

    50. ζ = 0.9 ensures a good transient response. 2 ζ f ⋅ ⋅ → ------------- - ζ < ------------------------------------------ < ----- - ⋅ 4 10 ⎛ ⎞ π ⋅ ζ ζ < 25kHz ⎝ ⎠ Freescale Semiconductor...
  • Page 123 Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. Freescale Semiconductor...

  • Page 124: Figure A-4 Jitter Definitions

    ⎟ max 1 – – -------------------- - -------------------- - ⋅ ⋅ ⎝ ⎠ For N < 100, the following equation is a good fit for the maximum jitter: ------- - J(N) Figure A-5 Maximum bus clock jitter approximation Freescale Semiconductor...

  • Page 125: Table A-16 Pll Characteristics

    C Jitter fit parameter 2 0.13 NOTES: 1. % deviation from target frequency 2. f = 4MHz, f = 25MHz equivalent f = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = Ω Freescale Semiconductor...
  • Page 126 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 127: Table A-17 Mscan Wake-Up Pulse Characteristics

    Device User Guide — 9S12DT128DGV2/D V02.16 A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Unit µs P MSCAN Wake-up dominant pulse filtered µs P MSCAN Wake-up dominant pulse pass Freescale Semiconductor...
  • Page 128 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...

  • Page 129: Figure A-6 Spi Master Timing (Cpha = 0)

    BIT 6 . . . 1 LSB OUT MSB OUT (OUTPUT) 1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6 SPI Master Timing (CPHA = 0) Freescale Semiconductor...

  • Page 130: Figure A-7 Spi Master Timing (Cpha =1)

    D Fall Time Inputs and Outputs NOTES: 1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in (Table A-19). Freescale Semiconductor...

  • Page 131: Figure A-8 Spi Slave Timing (Cpha = 0)

    (INPUT) (CPOL = 1) (INPUT) MISO BIT 6 . . . 1 SLAVE LSB OUT SLAVE MSB OUT (OUTPUT) MOSI MSB IN BIT 6 . . . 1 LSB IN (INPUT) Figure A-9 SPI Slave Timing (CPHA =1) Freescale Semiconductor...
  • Page 132 D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs Freescale Semiconductor...
  • Page 133 A.8.1 General Multiplexed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. Freescale Semiconductor...
  • Page 134 Device User Guide — 9S12DT128DGV2/D V02.16 1, 2 ECLK Addr/Data data data addr (read) PA, PB Addr/Data data data addr (write) PA, PB Non-Multiplexed Addresses PK5:0 LSTRB NOACC PIPO0 PIPO1, PE6,5 Figure A-10 General External Bus Timing Freescale Semiconductor...
  • Page 135 D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PW –t D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PW –t Freescale Semiconductor...
  • Page 136 D IPIPO[1:0] valid time to E rise (PW –t D IPIPO[1:0] delay time D IPIPO[1:0] valid time to E fall NOTES: 1. Affected by clock stretch: add N x t where N=0,1,2 or 3, depending on the number of clock stretches. Freescale Semiconductor...
  • Page 137 Device User Guide — 9S12DT128DGV2/D V02.16 Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DT128 packages. Freescale Semiconductor...
  • Page 138 11.000 BSC GAGE PLANE 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF θ 0.090 0.160 ° ° θ ° ° θ ° ° θ ° ° θ VIEW AB Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) Freescale Semiconductor...
  • Page 139 ° ° MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR 0.13 0.30 THE FOOT. 16.95 17.45 0.13 ° DETAIL C 16.95 17.45 0.35 0.45 1.6 REF Figure 1 80-pin QFP Mechanical Dimensions (case no. 841B) Freescale Semiconductor...
  • Page 140 Device User Guide — 9S12DT128DGV2/D V02.16 Freescale Semiconductor...
  • Page 141 Device User Guide — 9S12DT128DGV2/D V02.16 User Guide End Sheet Freescale Semiconductor...
  • Page 142 “Typicals” must be validated for each customer application by customer’s technical experts. Asia/Pacific: Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor H.K. Ltd. Freescale Semiconductor products are not designed, intended, or authorized for use as components...

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