Subscribe to Our Youtube Channel
Related Manuals for Freescale Semiconductor MCF52230 ColdFire
Summary of Contents for Freescale Semiconductor MCF52230 ColdFire
- Page 1 ® MCF52235 ColdFire Integrated Microcontroller Reference Manual Devices Supported: MCF52230 MCF52231 MCF52232 MCF52233 MCF52234 MCF52235 MCF52236 Document Number: MCF52235RM Rev. 6 07/2010...
- Page 2 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor China Ltd.
-
Page 3: Table Of Contents
Introduction ........................... 3-1 Memory Map/Register Description ....................3-2 Functional Description ........................3-8 Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) Introduction ........................... 4-1 Memory Map/Register Definition ....................4-3 Functional Description ........................4-8 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 4 IPS Bus Timeout Monitor ......................9-9 Functional Description ........................ 9-11 Chapter 10 Reset Controller Module 10.1 Introduction ..........................10-1 10.2 Features ............................10-1 10.3 Block Diagram ..........................10-1 10.4 Signals ............................10-2 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 5 14.7 Ports Interrupts .......................... 14-15 Chapter 15 Interrupt Controller Module 15.1 68K/ColdFire Interrupt Architecture Overview ................15-1 15.2 Memory Map ..........................15-4 15.3 Register Descriptions ........................15-5 15.4 Low-Power Wakeup Operation ....................15-17 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 6 21.1 Features ............................21-1 21.2 Modes of Operation ........................21-1 21.3 External Signal Description ......................21-2 21.4 Command Definition ........................21-3 21.5 Functional Description ........................ 21-7 21.6 Initialization/Application Information ..................21-8 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 7 26.3 Memory Map/Register Definition ....................26-3 26.4 Functional Description ......................26-16 26.5 Initialization/Application Information ..................26-26 Chapter 27 C Interface 27.1 Introduction ..........................27-1 27.2 Memory Map/Register Definition ....................27-3 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 8 32.2 External Signal Description ......................32-2 32.3 Memory Map/Register Definition ....................32-4 32.4 Functional Description ........................ 32-6 32.5 Initialization/Application Information ..................32-10 Appendix A Register Memory Map Quick Reference Appendix B Revision History MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 viii Freescale Semiconductor...
-
Page 9: Mcf52235 Coldfire® Integrated Microcontroller Reference Manual,
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 10 This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 11: Overview
112 LQFP 112 LQFP 112 LQFP MAPBGA MAPBGA The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the 80-pin package. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 12: Block Diagram
Figure 1-1. MCF52235 Block Diagram Part Numbers and Packaging Table 1-2 summarizes the features of the MCF52235 product family. Several speed/package options are available to match cost- or performance-sensitive applications. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 13: Features
16 × 16 → 32 or 32 × 32 → 32 operations — Cryptography Acceleration Unit (CAU) – Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions – FIPS-140 compliant random number generator MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 14 – Programmable bit rate up to 1 Mbit/sec — Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 15 — Minimum 1.125 μs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 16 Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down • Software watchdog timer — 32-bit counter — Low power mode support • Clock Generation Features MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 17 Chip integration module (CIM) — System configuration during reset — Selects one of three clock modes — Configures output pad drive strength — Unique part identification number and part revision number MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 18 To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 19 256 Kbytes of 32-bit flash memory. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The flash memory is ideal for program and data MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 1-10 Freescale Semiconductor...
- Page 20 C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices on a circuit board. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 1-11...
- Page 21 The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 1-12 Freescale Semiconductor...
- Page 22 It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 1-13...
-
Page 23: Memory Map Overview
DMA (Channel 1) 0x4000_0120 16 bytes DMA (Channel 2) 0x4000_0130 16 bytes DMA (Channel 3) 0x4000_0140 196 bytes Reserved 0x4000_0200 64 bytes UART0 0x4000_0240 64 bytes UART1 0x4000_0280 64 bytes UART2 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 1-14 Freescale Semiconductor... - Page 24 0x4015_0000 Programmable Interval Timer 0 0x4016_0000 Programmable Interval Timer 1 0x4017_0000 Reserved 0x4018_0000 Reserved 0x4019_0000 0x401a_0000 Timer 0x401b_0000 0x401c_0000 FlexCAN2 0x401d_0000 CFM (Flash) control registers 0x401e_0000 Ethernet Physical Transceiver MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 1-15...
- Page 25 Base Address (Hex) Size 0x401f_0000 Random Number Generator H/W Accelerator 0x4020_0000 Reserved 0x4400_0000 256K CFM (Flash) memory for IPS reads and writes 0x4408_0000 1G – 64M – 256K Reserved 0x8000_0000 Reserved MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 1-16 Freescale Semiconductor...
-
Page 26: Signal Descriptions
The term ‘negated’ indicates that a signal is inactive. Active-low signals, such as SRAS and TA, are indicated with an overbar. Overview Figure 2-1 shows the block diagram of the device with the signal interface. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 27 Port 2 To/From Interrupt Controller Figure 2-1. Block Diagram with Signal Interfaces Table 2-1 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 28 Table 2-1. Pin Functions by Primary and Alternate Purpose Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up/ Pin on 121 Pin on 112 Pin on 80 Pin Group Strength/ Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control — —...
- Page 29 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up/ Pin on 121 Pin on 112 Pin on 80 Pin Group Strength/ Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control Ethernet ACTLED —...
- Page 30 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up/ Pin on 121 Pin on 112 Pin on 80 Pin Group Strength/ Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control Interrupts IRQ15 —...
- Page 31 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up/ Pin on 121 Pin on 112 Pin on 80 Pin Group Strength/ Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control PWM7 —...
- Page 32 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Wired OR Pull-up/ Pin on 121 Pin on 112 Pin on 80 Pin Group Strength/ Function Function Function Function Control Pull-down MAPBGA LQFP LQFP Control UART 0 UCTS0 CANRX...
- Page 33 For secondary and GPIO functions only. RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended. For GPIO function. Primary Function has pull-up control within the GPT module. This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60...
-
Page 34: Reset Signals
VSS to prevent unintentional activation of test functions. External Interrupt Signals Table 2-5 describes the external interrupt signals. Table 2-5. External Interrupt Signals Signal Name Abbreviation Function External Interrupts IRQ[15:1] External interrupt sources. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 35: Queued Serial Peripheral Interface (Qspi)
Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable. Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active Chip Selects high or low. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 2-10 Freescale Semiconductor... -
Page 36: Fast Ethernet Controller Phy Signals
C module when the bus is in master mode or it becomes the clock input when the I C is in slave mode. Serial Data Open-drain signal that serves as the data input/output for the I interface. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 2-11... -
Page 37: Uart Module Signals
Function Analog Inputs AN[7:0] Inputs to the A-to-D converter. Analog Reference Reference voltage high and low inputs. Analog Supply Isolate the ADC circuitry from power supply noise — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 2-12 Freescale Semiconductor... -
Page 38: 2.13 General Purpose Timer Signals
Breakpoint. Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 2-13... -
Page 39: 2.16 Ezport Signal Descriptions
EzPort Serial Data In EZPD EZPD is sampled on the rising edge of EZPCK EzPort Serial Data Out EZPQ EZPQ transitions on the falling edge of EZPCK MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 2-14 Freescale Semiconductor... -
Page 40: 2.17 Power And Ground Pins
Pay particular attention to those pins which show only capacitor connections. CAUTION Avoid connecting power-supply voltage directly to pins in Figure 2 which show only capacitor connections, as doing so could damage the device severely. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 2-15... - Page 41 MCF52235 DDX1 DDX2 0.1µF SSX2 Pin numbering is shown for the 80-lead LQFP 0.22µF 0.22µF 0.22µF 0.22µF 0.22µF 12.4KΩ optional Figure 2. Suggested connection scheme for Power and Ground MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 2-16 Freescale Semiconductor...
-
Page 42: Coldfire Core
Figure 3-1. V2 ColdFire Core Pipelines The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), that decodes the MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 43: Memory Map/Register Description
— Four 48-bit accumulator registers partitioned as follows: – Four 32-bit accumulators (ACC0–ACC3) – Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 44: Features
MAC Accumulator 0,1 Extension Bytes Undefined 4.2.4/4-7 (ACCext01) 0x808 MAC Accumulator 2,3 Extension Bytes Undefined 4.2.4/4-7 (ACCext23) 0x80E Condition Code Register (CCR) Undefined 3.2.4/3-6 0x80F Program Counter (PC) Contents of 3.2.5/3-7 location 0x0000_0004 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 45 Figure 3-2. Data Registers (D0–D7) 3.2.2 Address Registers (A0–A6) These registers can be used as software stack pointers, index registers, or base address registers. They can also be used for word and longword operations. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 46 The USP must be initialized using the instruction before any move.l Ay,USP entry into user mode. The SSP is loaded during reset exception processing with the contents of location 0x0000_0000. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 47 Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 48 (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and before any compare (CMP), Bcc, or Scc instructions execute. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 49: Functional Description
The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional 32-bit data buses. This structure minimizes the core size without compromising performance to a large degree. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 50 IFP during the cycle. If the accessed data is not present in a local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 51 For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-10 Freescale Semiconductor...
- Page 52 Operand Execution Pipeline DSOC AGEX <ea>y Core Bus Address Opword Extension 1 Core Bus Extension 2 Write Data Core Bus Read Data Figure 3-12. V2 OEP Embedded-Load Part 1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-11...
- Page 53 <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax. For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-12 Freescale Semiconductor...
- Page 54 In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-13...
- Page 55 ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-14 Freescale Semiconductor...
- Page 56 (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-15...
- Page 57 Unimplemented line-A opcode 0x02C Fault Unimplemented line-F opcode 0x030 Next Debug interrupt 0x034 — Reserved 0x038 Fault Format error 15–23 0x03C–0x05C — Reserved 0x060 Next Spurious interrupt 25–31 0x064–0x07C — Reserved MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-16 Freescale Semiconductor...
- Page 58 There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 3-7. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-17...
- Page 59 All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-18 Freescale Semiconductor...
- Page 60 Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) Logical OR (OR) Subtract (SUB), Subtract Extended (SUBX) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-19...
- Page 61 PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-20 Freescale Semiconductor...
- Page 62 (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-21...
- Page 63 PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-22 Freescale Semiconductor...
- Page 64 FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-23...
- Page 65 Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. CLSZ 29–28 Configurable cache associativity. CCAS Four-way Direct mapped (This is the value used for this device) Else Reserved for future use MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-24 Freescale Semiconductor...
- Page 66 Each timing entry is presented as C(R/W) where: • C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-25...
- Page 67 MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-26 Freescale Semiconductor...
- Page 68 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-27...
- Page 69 <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ANDI.L #imm,Dx 1(0/0) — — — — — — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-28 Freescale Semiconductor...
- Page 70 #imm,Dx 1(0/0) — — — — — — — SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBX.L Dy,Dx 1(0/0) — — — — — — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-29...
- Page 71 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. PEA execution times are the same for (d16,PC). PEA execution times are the same for (d8,PC,Xn*SF). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-30 Freescale Semiconductor...
- Page 72 Effective address of (d16,PC) not supported Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 3-31...
- Page 73 — — 5(1/0) — — — — — Table 3-19. Bcc Instruction Execution Times Forward Forward Backward Backward Opcode Taken Not Taken Taken Not Taken 3(0/0) 1(0/0) 2(0/0) 3(0/0) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 3-32 Freescale Semiconductor...
-
Page 74: Enhanced Multiply-Accumulate Unit (Emac)
The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 4-1). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 75: Introduction
0 ( )x i ( ) b 1 ( )x i 1 b 2 ( )x i 2 b 3 ( )x i 3 Eqn. 4-2 – – – – MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 76: Memory Map/Register Definition
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-2. MAC Status Register (MACSR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 77 If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 78 ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 79 Figure 4-3. Mask Register (MASK) Table 4-4. MASK Field Descriptions Field Description 31–16 Reserved, must be set. 15–0 Performs a simple AND with the operand address for MAC instructions. MASK MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 80: Reset
Field Description 31–24 Accumulator 0 upper extension byte ACC0U 23–16 Accumulator 0 lower extension byte ACC0L 15–8 Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 81: Functional Description
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 82 Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 83 If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 4-10 Freescale Semiconductor...
- Page 84 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory This code performs the EMAC state restore: EMAC_state_restore: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 4-11...
- Page 85 Store MAC Mask Reg Writes the contents of the MASK to a CPU register move.l MASK,Rx Load Accumulator move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit Extensions 01 operand MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 4-12 Freescale Semiconductor...
- Page 86 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 4-13...
- Page 87 For the EMAC, assemblers support this syntax and no explicit reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 4-14 Freescale Semiconductor...
- Page 88 = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 4-15...
- Page 89 (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 4-16 Freescale Semiconductor...
- Page 90 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 4-17...
- Page 91 {MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 4-18 Freescale Semiconductor...
- Page 92 MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 4-19...
-
Page 93: Cryptographic Acceleration Unit (Cau)
Register File Hash Operand1 Command Datapath Decode Control Figure 5-1. Top Level CAU Block Diagram 5.1.2 Overview The CAU supports acceleration of the following algorithms: • • 3DES • • MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 94: Memory Map/Register Definition
General purpose register 2 (CA2) 0x0000_0000 5.2.3/5-4 General purpose register 3 (CA3) 0x0000_0000 5.2.3/5-4 General purpose register 4 (CA4) — — — 0x0000_0000 5.2.3/5-4 General purpose register 5 (CA5) — — — 0x0000_0000 5.2.3/5-4 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 95 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-3. CAU Accumulator Register (CAA) Table 5-3. CAA Field Descriptions Field Description 31–0 Accumulator. Stores results of various CAU commands. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 96: Functional Description
CAU supports a single command ( ) for store instructions and 21 commands for the load instructions. The CAU only supports longword operations. A CAU command can be issued every clock cycle. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 97 → CA1 <<< 30 CA2, → → CA3, CA3 → → cp0ld Message Digest Shift 0x140 CAA, CAA CA1, → → CA2, CA2 CA3, → cp0ld Illegal Command 0x1F0 CASR[0] MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 98 0x0102_0304 0xA0B0_C0D0 0xA4B3_C2D1 5.3.3.6 Add Register to Accumulator ( ADRA cp0ld.l #ADRA+CAx command adds CAx to CAA and stores the result in CAA. ADRA 5.3.3.7 Exclusive Or ( cp0ld.l <ea>,#XOR+CAx MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 99 <ea> on the AESIC contents of CAx followed by the AES inverse mix column operation on that result and stores the result back in CAx. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 100 CA0 and CA1. Table 5-9 defines the specific shift function performed based on the KSx field. Table 5-9. Key Shift Function Codes Shift Function Code Define KSL1 Left 1 KSL2 Left 2 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 101 SHA-1. The following source and destination assignments are made: CAA=CAA<<<5, CA0=CAA, CA1=CA0, CA2=CA1<<<30, CA3=CA2, CA4=CA3. 1.The DES algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 102: Application/Initialization Information
.set CA2,0x4 .set CA3,0x5 .set CA4,0x6 .set CA5,0x7 ; CAU Commands .set CNOP,0x000 .set LDR,0x010 .set STR,0x020 .set ADR,0x030 .set RADR,0x040 .set ADRA,0x050 .set XOR,0x060 .set ROTL,0x070 .set MVRA,0x080 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 5-10 Freescale Semiconductor... - Page 103 ; MD5 H(), SHA Parity() CA1^CA2^CA3 .set HFI,0x3 ; MD5 I() CA2^(CA1|~CA3) .set HFC,0x4 ; SHA Ch() CA1&CA2 ^ ~CA1&CA3 .set HFM,0x5 ; SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 5-11...
-
Page 104: Random Number Generator (Rng)
– Other entropy supplied directly by the user NOTE See Appendix D of the NIST Special Publication 800-90 “Recommendation for Random Number Generation Using Deterministic Random Bit Generators” for more information: http://csrc.nist.gov MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 105: Memory Map/Register Definition
Clear interrupt. Writing a 1 to this bit clears the error interrupt and RNGSR[EI]. This bit is self-clearing, 0 Do not clear error interrupt. 1 Clear error interrupt. Interrupt mask. 0 Error interrupt enabled. 1 Error interrupt masked. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 106 FIFO underflow. Signals FIFO underflow. Reset by reading RNGSR. 0 RNGOUT not read while empty since last read of RNGSR. 1 RNGOUT read while empty since last read of RNGSR. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 107 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-4. RNGOUT MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 108: Functional Description
This logic is brainless and must be controlled by the control block. The control block controls how the shift registers are configured and when the oscillator clocks are turned on. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 109: Initialization/Application Information
3. Write to the RNG control register and set the interrupt mask, high assurance, and GO bits. 4. Poll RNGSR[OFL] to check for random data in RNGOUT. 5. Read available random data from RNGOUT. 6. Repeat steps 3 and 4 as needed. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 110: Clock Module
PLL. The PLL reference can be a crystal oscillator or an external clock. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 111: Low-Power Mode Operation
In external clock mode, there are no wakeup periods for oscillator startup or PLL lock. Block Diagram Figure 7-1 shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in detail in Figure 7-2. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 112 DISCLK PPMRL[10] PPMRH[7] PITs PPMRL[9] PPMRH[4:3] UARTs Edge Port PPMRL[7:5] PPMRH[1] GPIO / Ports PPMRL[4] PPMRH[0] RNGA PPMRL[21] PPMRH[13] WDOG FlexCAN PPMRH[10] EPHY PPMRH[12] Figure 7-1. Clock Module Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 113: Signal Descriptions
Reset signal from reset controller 7.6.1 EXTAL This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 114: Memory Map And Registers
Addresses not assigned to a register and undefined register bits are reserved for expansion. Section 9.2.1, “Peripheral Power Management Registers (PPMRH, PPMRL).” 7.7.1 Register Descriptions This subsection provides a description of the clock module registers. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 115 PLL disabled. 0 No reset on loss of lock 1 Reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 116 Note: In external clock mode, the LOCEN bit has no effect Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low. DISCLK 0 CLKOUT enabled 1 CLKOUT disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 117 Indicates if an external oscillator is providing the reference clock source EXTOSC 0) Reference clock is not external oscillator 1 Reference clock is external oscillator 6–5 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 118 2 (where n is a number from 0 to 15 represented by the 4 bit field). The clock change takes effect with the next rising edge of the system clock. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 119 Figure 7-6. Clock Control High Register (CCHR) Table 7-7. CCHR Field Descriptions Field Description 7–3 Reserved, should be cleared. 2–0 Clock control pre-division factor (divides the PLL input clock by a factor of CCHR+1). CCHR MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-10 Freescale Semiconductor...
-
Page 120: Functional Description
PLL and switch between the PLL clock and the oscillator clock as the source of the system clock. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-11... - Page 121 Actual component values depend on crystal specifications. The following subsections describe each major block of the PLL. Refer to Figure 7-8 to see how these functional sub-blocks interact. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-12 Freescale Semiconductor...
- Page 122 The voltage across the loop filter controls the frequency of the VCO output. The frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four times the target system frequency. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-13...
- Page 123 Figure 7-9 shows the sequence for detecting locked and non-locked conditions. In external clock mode, the PLL is disabled and cannot lock. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-14 Freescale Semiconductor...
- Page 124 To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the LOLRE bit has no effect. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-15...
- Page 125 PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. The reference and the PLL must be functioning properly to exit reset. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-16 Freescale Semiconductor...
- Page 126 Off On 0 Lose lock Regain Block LOCKS from being cleared Lose reference Stuck — — — clock or no lock regain Lose reference Block LOCKS clock, from being regain cleared MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-17...
- Page 127 Off Off 0 Lose lock, Regain REF not entered f.b. clock, during stop; reference SCM entered clock during stop only during oscillator startup No regain Stuck — — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-18 Freescale Semiconductor...
- Page 128 On On X — — Lose lock or clock RESET — — — Reset immediately Off X Lose lock, RESET RESET — — — Reset f.b. clock, immediately reference clock MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-19...
- Page 129 Stuck — — — clock Off X Regain SCM Wakeup without disabled lock Off X Regain SCM disabled On On 0 — — Wakeup without lock Lose reference clock MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 7-20 Freescale Semiconductor...
- Page 130 1→LC = current value is 1 until clock is regained which then is the previous value before entering stop 1→ = current value is 1 until clock is regained but CLK is never expected to regain MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 7-21...
-
Page 131: Real-Time Clock
STATUS ADDRESS IPBUS DATA MINUTE STOPWATCH DECODE BUS CONTROL Figure 8-1. Real-Time Clock Block Diagram 8.1.2 Features The RTC module includes the following features: • Full clock—days, hours, minutes, seconds MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... -
Page 132: Memory Map/Register Definition
RTC Control Register (RTCCTL) read/write 0x03D4 RTC Interrupt Status Register (RTCISR) read/write 0x03D8 RTC Interrupt Enable Register (RTCIENR) read/write 0x03DC Stopwatch Minutes Register (STPWCH) read/write 0x03E0 RTC Days Counter Register (DAYS) read/write MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 133 After a write, the time changes to the new value. A power-on reset (POR) sets the RTC to the reset values shown in Figure 8-3. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 134 The alarm settings can be read or written at any time. IPSBAR Access: User read/write Offset: 0x03C8 (ALRM_HM) Reset HOURS MINUTES Reset Figure 8-4. RTC Hours and Minutes Alarm Register (ALRM_HM) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 135 Alarm seconds setting; can be set to any value between 0 and 59. SECONDS 8.2.5 RTC Control Register (RTCCTL) The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the reference frequency information for the prescaler. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 136 These bits are cleared by writing a 1 to them; this also clears the interrupt. Interrupts may occur while the system clock is idle or in sleep mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 137 1 A 1-minute interrupt has occurred Stopwatch flag bit. This bit indicates that the stopwatch countdown has timed out. 0 The stopwatch did not time out. 1 The stopwatch timed out. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 138 -1 until it is reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH register, an interrupt is posted on the next minute tick. Bit description 1 = Stopwatch interrupt is enabled. 0 = Stopwatch interrupt is disabled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 139 After a write, the time changes to the new value. This register cannot be reset because the real-time clock is always enabled at reset. Only 16-bit accesses to this register are allowed. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 140 The real-time clock day alarm (ALRM_DAY) register is used to configure the day for the alarm. The alarm settings can be read or written at any time. IPSBAR Access: User read/write Offset: 0x03E4 (ALRM_DAY) Reset DAYSAL Reset Figure 8-11. RTC Day Alarm Register (ALRM_DAY) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 8-10...
-
Page 141: Functional Description
-1, the interrupt occurs. The value of the register does not change until it is reprogrammed. The actual delay includes the seconds from setting the stopwatch to the next minute tick. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 8-11 Freescale Semiconductor... -
Page 142: Initialization/Application Information
Check RTC Interrupt Status Register Figure 8-12. Flow Chart of RTC Operation 8.4.3 Code Example for Initializing the Real-Time Clock Figure 8-13 shows sample code for initializing the RTC. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 8-12... - Page 143 MCF_CLOCK_RTCDR = 48000000; /* Device-dependent */ MCF_RTC_HOURMIN = MCF_RTC_HOURMIN_HOURS(((uint32)time_temp % 24)); MCF_RTC_HOURMIN = MCF_RTC_HOURMIN_MINUTES(((uint32)time_temp % 60)); MCF_RTC_SECONDS = MCF_RTC_SECONDS_SECONDS(((uint32)time_temp % 60)); Figure 8-13. Code Example for Initializing the Real-Time Clock MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 8-13 Freescale Semiconductor...
- Page 144 LPCR. The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 145: Power Management
PPMRH definition. IPSBAR 0x00_000C (PPMRH) Access: read/write Offset: Reset Reset CDRNGA CDEPHY CDCFM CDFCAN CDPWM CDGPT Reset CDADC CDPIT1 CDPIT0 CDEPORT CDPORTS Reset Figure 9-1. Peripheral Power Management Register High (PPMRH) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 146 0 EPORT module clock is enabled 1 EPORT module clock is disabled Disable clock to the Ports module. CDPORTS 0 Ports module clock is enabled 1 Ports module clock is disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 147 Disable clock to the DTIM3 module. CDTMR3 TMR3 module clock is enabled TMR3 module clock is disabled Disable clock to the DTIM2 module. CDTMR2 TMR2 module clock is enabled TMR2 module clock is disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 148 CPU and logic associated with the interrupt controller. The LPICR is an 8-bit register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed to exit a low-power mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 149 7. With the processor clocks enabled, the core processes the pending interrupt request. IPSBAR 0x00_0012 (LPICR) Access: read/write Offset: ENBSTOP XLPM_IPL[2:0] Reset: Figure 9-3. Low-Power Interrupt Control Register (LPICR) Table 9-4. LPICR Field Description Field Description MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 150 IPS module clocks. Reads of this register return all zeroes. See Figure 9-4 Table 9-6 for the PPMRS definition. IPSBAR 0x00_0021 (PPMRS) Access: write-only Offset: PPMRS Reset: Figure 9-4. Peripheral Power Management Set Register (PPMRS) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 151 The LPCR controls chip operation and module operation during low-power modes. The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
-
Page 152: Ips Bus Timeout Monitor
IPS bus cycle and completes the cycle if there is no response when the programmed monitor cycle count is reached. The error termination is propagated onto the system bus and eventually back to the ColdFire Core. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor... - Page 153 Bus Monitor Timeout. This field selects the timeout period (measured in system bus clock cycles) for the bus BMT[2:0] monitor. 000 1024 cycles 001 512 cycles 010 256 cycles 011 128 cycles 100 64 cycles 101 32 cycles 110 16 cycles 111 8 cycles MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 9-10 Freescale Semiconductor...
-
Page 154: Functional Description
An interrupt request which has been enabled at the module of the interrupt’s origin. 9.4.1.1 Run Mode Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 9-11... - Page 155 SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 9.4.2.3 Flash The flash module is in a low-power state if not being accessed. No recovery time is required after exit from any low-power mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 9-12 Freescale Semiconductor...
- Page 156 • Clearing the QSPI enable bit (SPE) disables the QSPI function. • The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 9-13...
- Page 157 If low-power mode is exited by a reset, the state of the I/O pins reverts to their default direction settings. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 9-14 Freescale Semiconductor...
- Page 158 When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 9-15...
- Page 159 The correct flow to enter stop mode with SELF-WAKE: — assert SELF-WAKE at the same time as STOP. — wait for STOP_ACK bit to be set. • The correct flow to negate STOP with SELF-WAKE: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 9-16 Freescale Semiconductor...
- Page 160 (PWMCTL[PSWAI]) and doze mode (PWMCTL[PFRZ]). If either of these bits are set, the PWM input clock to the prescalar is disabled during the respective low power mode. In stop mode the input clock is disabled and PWM generation is halted. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 9-17...
- Page 161 Reset Chip Configuration Module Enabled Enabled Stopped Power Management Enabled Enabled Stopped Clock Module Enabled Interrupt Enabled Interrupt Enabled Interrupt Real-Time Clock Module Enabled Interrupt Enabled Interrupt Enabled Interrupt MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 9-18 Freescale Semiconductor...
- Page 162 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode is re-entered and changes made in halt mode remains in effect. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 9-19...
-
Page 163: Introduction
LVD control and status bits for setup and use of LVD reset or interrupt 10.3 Block Diagram Figure 10-1 illustrates the reset controller and is explained in the following sections. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-1... -
Page 164: Block Diagram
The reset controller programming model consists of these registers: • Reset control register (RCR)—selects reset controller functions • Reset status register (RSR)—reflects the state of the last reset source MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-2... - Page 165 0 Negate RSTO pin CAUTION: External logic driving reset configuration data during reset needs to be considered when asserting the RSTO pin when setting FRCRSTOUT. Reserved, should be cleared. — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 10-3 Freescale Semiconductor...
- Page 166 RSR can be read at any time. Writing to RSR has no effect. IPSBAR 0x11_0001 (RSR) Access: User read-only Offset: SOFT Reset: Reset Dependent Figure 10-3. Reset Status Register (RSR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-4...
- Page 167 To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 10-5 Freescale Semiconductor...
- Page 168 A software reset occurs when the SOFTRST bit is set. If the RSTI is negated and the PLL has acquired lock, the reset controller asserts RSTO for approximately 512 cycles. Then the device exits reset and resumes operation. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-6...
- Page 169 10-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 10-7 Freescale Semiconductor...
- Page 170 LATCH RESET STATUS ASSERT RSTO AND LATCH RESET STATUS RSTI NEGATED? PLL MODE? PLL LOCKED? WAIT 512 CLKOUT CYCLES NEGATE RSTO RCON ASSERTED? LATCH CONFIGURATION Figure 10-4. Reset Control Flow MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-8...
- Page 171 (5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 10-9 Freescale Semiconductor...
- Page 172 For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared to 0, even if another type of reset condition is detected during the reset sequence for LVD. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 10-10...
-
Page 173: Static Ram (Sram)
Byte, word, and longword address capabilities 11.2 Memory Map/Register Description The SRAM programming model shown in Table 11-1 includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 11-1... - Page 174 Base Address. Defines the 0-modulo-32K base address of the SRAM module. By programming this field, the SRAM may be located on any 32-Kbyte boundary (16-Kbyte boundary for the MCF52230 and MCF52231). 14–12 Reserved, must be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 11-2...
-
Page 175: Initialization/Application Information
If the SRAM requires initialization with instructions or data, perform the following steps: 1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 11-3 Freescale Semiconductor... - Page 176 Table 11-3 shows examples of typical RAMBAR settings. Table 11-3. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Instruction Only 0x2B Data Only 0x35 Instructions and Data 0x21 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 11-4...
-
Page 177: Chip Configuration Module (Ccm)
External clock or phase-lock loop (PLL) mode with internal or external reference • Output pad drive strength • Low-power configuration • Processor status (PSTAT) and processor debug data (DDATA) functions • BDM or JTAG mode MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 12-1... -
Page 178: External Signal Descriptions
Table 12-2 shows the accessibility of write-once bits. Table 12-2. Write-Once Bits Read/Write Accessibility Configuration Read/Write Access All configurations Read-always Debug operation Write-always MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 12-2 Freescale Semiconductor... - Page 179 Register Descriptions The following section describes the CCM registers. 12.3.3.1 Chip Configuration Register (CCR) IPSBAR 0x11_0004 (CCR) Access: Supervisor read-only Offset: SZEN PSTEN Reset Figure 12-2. Chip Configuration Register (CCR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 12-3...
- Page 180 Configuration”) if the external RCON pin is asserted. RCON is a read-only register. IPSBAR 0x11_0008 (RCON) Access: Supervisor read-only Offset: RLOAD MODE Reset Figure 12-3. Reset Configuration Register (RCON) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 12-4 Freescale Semiconductor...
-
Page 181: Functional Description
Three functions are defined within the chip configuration module: • Reset configuration • Output pad strength configuration • Clock mode selections These functions are described in the following sections. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 12-5... -
Page 182: Reset
Reset initializes CCM registers to a known startup state as described in Section 12.3, “Memory Map/Register Definition.” The CCM controls chip configuration at reset as described in Section 12.4, “Functional Description.” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 12-6 Freescale Semiconductor... -
Page 183: System Control Module (Scm)
— Core reset status register (CRSR) indicates type of last reset — Core watchdog service register (CWSR) services watchdog timer — Core watchdog control register (CWCR) for watchdog timer control MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-1... -
Page 184: Memory Map And Register Definition
Peripheral Access Control Register (PACR3) 0x00 13.7.3.2/13-15 0x00_0028 Peripheral Access Control Register (PACR4) 0x00 13.7.3.2/13-15 0x00_0029 Peripheral Access Control Register (PACR5) 0x00 13.7.3.2/13-15 0x00_002A Peripheral Access Control Register (PACR6) 0x00 13.7.3.2/13-15 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-2 Freescale Semiconductor... -
Page 185: Register Descriptions
1. IPSBAR 2. RAMBAR NOTE This is the list of memory access priorities when viewed from the processor core. Figure 13-1 Table 13-2 for descriptions of the bits in IPSBAR. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-3... - Page 186 The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a 0-modulo-size value. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-4 Freescale Semiconductor...
- Page 187 Note: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to the SRAM. For more information, see Section 11.2.1, “SRAM Base Address Register (RAMBAR).” 8–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-5...
- Page 188 Reset: See Note Note: The reset value of EXT depend on the last reset source. All other bits are initialized to zero. Figure 13-3. Core Reset Status Register (CRSR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-6 Freescale Semiconductor...
- Page 189 The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-7...
- Page 190 1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit. Core watchdog timer interrupt flag. CWTIF 0 CWT interrupt has not occurred 1 CWT interrupt has occurred. Write a 1 to clear the interrupt request. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-8 Freescale Semiconductor...
-
Page 191: Internal Bus Arbitration
MPARK RAMBAR MARB Internal Modules Figure 13-6. Arbiter Module Functions 13.6.1 Overview The basic functionality is that of a 2-port, pipelined internal bus arbitration module with the following attributes: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-9... - Page 192 In fixed arbitration, the master with highest priority (as specified by the MPARK[Mn_PRTY] bits) wins the bus. That master relinquishes the bus when all transfers to that master are complete. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-10 Freescale Semiconductor...
- Page 193 1 DMA BCRs function as 24 bit counters. 23–22 Master priority level for master 3 (FEC) M3_PRTY 00 Fourth (lowest) priority 01 Third priority 10 Second priority 11 First (highest) priority MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-11...
-
Page 194: System Access Control Unit (Sacu)
In many systems, the operating system executes in supervisor mode, while application software executes in user mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-12 Freescale Semiconductor... -
Page 195: Features
— Reset state provides supervisor-only read/write access to these modules. — Nine 8-bit registers control access to 17 of the on-chip peripheral modules • Grouped peripheral access control registers (GPACR0, GPACR1) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-13... -
Page 196: Memory Map/Register Definition
3 corresponds to master 3 (Fast Ethernet controller), bit 2 to master 2 (DMA Controller), and bit 0 to master 0 (ColdFire core). IPSBAR Access: read/write Offset: 0x0020 (MPR) Reset: Figure 13-8. Master Privilege Register (MPR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-14 Freescale Semiconductor... - Page 197 Only a system reset clears this flag. 2–0 This 3-bit field defines the access control for the given platform peripheral. ACCESS_CTRL0 The encodings for this field are shown in Table 13-10. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-15...
- Page 198 GPACRn to be used for a given reference within the IPS address space. These access control registers are 8 bits wide so that read, write, and execute attributes may be assigned to the given IPS region. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-16 Freescale Semiconductor...
- Page 199 No Access No Access 1000 Read / Write / Execute No Access 1001 Read / Execute No Access 1010 Read / Execute Read / Execute 1011 Execute No Access MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 13-17...
- Page 200 EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) GPACR1 0x0400_0000– CFM (Flash module’s backdoor access for 0x07FF_FFFF programming or access by a bus master other than the core) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 13-18 Freescale Semiconductor...
-
Page 201: Introduction
The digital I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins. Figure 14-1 is a block diagram of the MCF52235 ports. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-1... - Page 202 The MCF52235 ports module controls the configuration for the following external pins: • External bus accesses • Chip selects • Debug data • Processor status • FlexCAN transmit/receive data • C serial control • QSPI • UART transmit/receive MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-2 Freescale Semiconductor...
-
Page 203: Features
Descriptions,” for more detailed information on the different signals and pins. 14.5 Memory Map/Register Definition 14.5.1 Ports Memory Map Table 14-1 summarizes all the registers in the MCF52235 ports address space. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-3... - Page 204 The register address is the sum of the IPSBAR address and the value in this column. S/U equals supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-4 Freescale Semiconductor...
-
Page 205: Register Descriptions
0x10_0010 (PORTTD) 0x10_0011 (PORTUA) 0x10_0012 (PORTUB) 0x10_0013 (PORTUC) PORTn3 PORTn2 PORTn1 PORTn0 Reset: Figure 14-3. Port Output Data Registers with Bits 3:0 Implemented (PORTAS, PORTTA, PORTTC, PORTTD, PORTUA, PORTUB, PORTUC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-5... - Page 206 Setting any bit in a DDRn register configures the corresponding port n pin as an output. Clearing any bit in a DDRn register configures the corresponding pin as an input. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-6 Freescale Semiconductor...
- Page 207 Figure 14-8. Port Data Direction Registers with Bits 6:0 Implemented (DDRQS, DDRLD) IPSBAR Access: User read/write Offset: 0x10_0020 (DDRNQ) DDRn7 DDRn6 DDRn5 DDRn4 DDRn3 DDRn2 DDRn1 Reset: Figure 14-9. Port NQ Data Direction Register (DDRNQ) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-7...
- Page 208 0x10_0041 (SETUA) 0x10_0042 (SETUB) 0x10_0043 (SETUC) SETn3 SETn2 SETn1 SETn0 Reset: Figure 14-11. Port Pin Data/Set Data Registers with Bits 3:0 Implemented (SETAS, SETTA, SETTC, SETTD, SETUA, SETUB, SETUC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-8 Freescale Semiconductor...
- Page 209 Their bit definitions are shown in Figure 14-15, Figure 14-16, and Figure 14-17. The fields are described in Table 14-5, which applies to all CLRn registers. The CLRn registers are read/write. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-9...
- Page 210 Figure 14-16. Port Clear Output Data Registers with Bits 6:0 Implemented (CLRQS, CLRLD) IPSBAR Access: User read/write Offset: 0x10_0050 (CLRNQ) CLRn7 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 Reset: Figure 14-17. Port NQ Clear Output Data Register (CLRNQ) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-10 Freescale Semiconductor...
- Page 211 Figure 14-18. Dual-Function Pin Assignment Registers with Bits 7:0 Implemented (PANPAR, PDDPAR, PGPPAR) IPSBAR Access: User read/write Offset: 0x10_0075 (PLDPAR) PnPAR6 PnPAR5 PnPAR4 PnPAR3 PnPAR2 PnPAR1 PnPAR0 Reset: Figure 14-19. Port LD Pin Assignment Register (PLDPAR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-11...
- Page 212 14-7, which applies to all quad-function registers. IPSBAR Access: User read/write Offset: 0x10_0068 (PNQPAR) PnPAR7 PnPAR6 PnPAR5 PnPAR4 Reset PnPAR3 PnPAR2 PnPAR1 Reset Figure 14-21. Port NQ Pin Assignment Register (PNQPAR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-12 Freescale Semiconductor...
- Page 213 Pin Wired OR Register (PWOR) The Pin Wired OR register (PWOR) is read/write and each bit resets to logic 0. Refer to Table 2-1 details of which PWOR bit controls which pin. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-13...
- Page 214 See footnote 1 See footnote 1 1) Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode. Figure 14-25. Pin Drive Strength Register 1 (PDSR1) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 14-14 Freescale Semiconductor...
-
Page 215: Ports Interrupts
0 Pin is configured for low drive strength (2 mA) 1 Pin is configured for high drive strength (10 mA) 14.7 Ports Interrupts The ports module does not generate interrupt requests. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 14-15... -
Page 216: Interrupt Controller Module
The fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-1... - Page 217 (from highest to lowest priority) as shown in Table 15-1. Table 15-1. Interrupt Priority Within a Level Interrupt ICR[2:0] Priority Sources 7 (Highest) 8–63 8–63 8–63 8–63 — Fixed Midpoint Priority 1–7 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-2...
- Page 218 Recall that vector numbers 0–63 are reserved for the ColdFire processor and its internal exceptions. Thus, the mapping of bit positions to vector numbers is as follows: if interrupt source 1 is active and acknowledged, then Vector number = MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-3 Freescale Semiconductor...
-
Page 219: Memory Map
Table 15-3. Interrupt Controller Memory Map Width Section/ Address Register Access Reset Value (bits) Page Interrupt Controller 0 0x00_0C00 Interrupt Pending Register High (IPRH0) 0x0000_0000 15.3.1/15-6 0x00_0C04 Interrupt Pending Register Low (IPRL0) 0x0000_0000 15.3.1/15-6 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-4... - Page 220 Global IACK Registers 0x00_0F0E0 + 4n Global Level m Interrupt Acknowledge Registers 0x00 15.3.8/15-12 (n=1:7) (GLmIACK) 15.3 Register Descriptions The interrupt controller registers are described in the following sections. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-5 Freescale Semiconductor...
- Page 221 The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending Reserved, must be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-6...
- Page 222 Mask all interrupts. Setting this bit forces the other 63 bits of the IMRHn and IMRLn to ones, disabling all interrupt MASKALL sources, and providing a global mask-all capability. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-7 Freescale Semiconductor...
- Page 223 Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. INTFRCH 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-8...
- Page 224 In addition to providing the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-9 Freescale Semiconductor...
- Page 225 If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. Table 15-12. ICRnx Register Accessibility Registers Access ICRn1 – ICRn7 Read-only ICRn8 – ICRn63 Read / write MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-10...
- Page 226 The IACKLPR register is also loaded as the software IACK is performed. If there are no active sources, the interrupt MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-11 Freescale Semiconductor...
- Page 227 Vector number. A read from one of the LmIACK registers returns the vector for the highest priority unmasked VECTOR interrupt within a level for all interrupt controllers. As implemented on the MCF52, these registers contain the same information as LmIACK. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-12...
- Page 228 Write 1 to appropriate DTER0 bit DTIM1 DTIM1 interrupt Write 1 to appropriate DTER1 bit DTIM2 DTIM2 interrupt Write 1 to appropriate DTER2 bit DTIM3 DTIM3 interrupt Write 1 to appropriate DTER3 bit MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-13 Freescale Semiconductor...
- Page 229 Write 1 to EOSI1 ADCINT ADC Interrupt Write 1 to ZCI, LLMTI and HLMTI PWM Interrupt Write PWMIF = 1 RNGA RNGA RNGA Interrupt Clears after one cycle of module reset MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-14...
- Page 230 Cleared automatically RTC Interrupt Write 1 to appropriate bit. Table 15-17. Interrupt Source Assignment For Interrupt Controller 1 Source Module Flag Source Description Flag Clearing Mechanism 0–7 Not Used (Reserved) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-15 Freescale Semiconductor...
- Page 231 Edge port flag 5 Write EPF5 = 1 EPF6 Edge port flag 6 Write EPF6 = 1 EPF7 Edge port flag 7 Write EPF7 = 1 40–63 Not Used MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 15-16...
-
Page 232: Low-Power Wakeup Operation
LPICR[6:4], then the interrupt controller asserts the wake-up output signal, which is routed to the SCM and PLL module to re-enable the device’s clock trees and resume processing. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 15-17 Freescale Semiconductor... -
Page 233: Edge Port Modules (Eportn)
Mode EPPAR[2n, 2n + 1] Edge Detect Logic EPFRn To Interrupt Controller EPPDRn Synchronizer Rising Edge of System Clock EPIERn EPDRn EPDDRn IRQn pin Figure 16-1. EPORT Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 16-1... -
Page 234: Low-Power Mode Operation
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are set at reset. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 16-2 Freescale Semiconductor... -
Page 235: Memory Map/Register Definition
The EPORT pin assignment register (EPPAR) controls the function of each pin individually. IPSBAR 0x13_0000 (EPPAR0) Access: Supervisor read/write Offset: 0x14_0000 (EPPAR1) EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 EPPA0 Reset Figure 16-2. EPORT Pin Assignment Register (EPPAR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 16-3... - Page 236 Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output. 0 Corresponding EPORT pin configured as input 1 Corresponding EPORT pin configured as output MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 16-4 Freescale Semiconductor...
- Page 237 Reading EDPR returns the data stored in the register. Reset sets EPD7 – EPD0. 16.4.5 Edge Port Pin Data Register (EPPDR) The EPORT pin data register (EPPDR) reflects the current state of the pins. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 16-5...
- Page 238 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register. 0 Selected edge for IRQn pin not detected 1 Selected edge for IRQn pin detected MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 16-6 Freescale Semiconductor...
-
Page 239: Coldfire Flash Module (Cfm)
It is not possible to read from any flash logical block while the same logical block is being erased, programmed, or verified. Flash logical blocks are divided into multiple logical pages that can be erased separately. An erased bit reads 1 and a programmed bit reads 0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-1... - Page 240 Single power supply for program and erase operations • Software programmable interrupts on command completion, access violations, or protection violations • Fast page erase operation • Fast word program operation MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-2 Freescale Semiconductor...
-
Page 241: External Signal Description
CFM protection and access restriction scheme out of reset. A description of each byte found in the flash configuration field is given in Table 17-1. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-3... - Page 242 0x4400_0000. Backdoor access to flash for reads can be made by the bus master, but it takes 2 cycles longer than a direct read of the flash if using its FLASHBAR address. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-4 Freescale Semiconductor...
- Page 243 Address fetch speculation. Performance enhancement to generate speculative flash accesses. to reduce the effective flash access time from the actual two-cycle array time to a smaller number approaching one cycle. 0 Speculation enabled 1 Disable speculation MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-5...
- Page 244 0x1D_0018 CFMDACC 0x1D_001C RESERVED 0x1D_0020 CFMUSTAT RESERVED 0x1D_0024 CFMCMD RESERVED 0x1D_0028 RESERVED 0x1D_002C RESERVED 0x1D_0030 RESERVED 0x1D_0034 RESERVED 0x1D_0038 RESERVED 0x1D_003C RESERVED 0x1D_0040 RESERVED 0x1D_0044 RESERVED 0x1D_0048 RESERVED CFMCLKSEL MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-6 Freescale Semiconductor...
- Page 245 The CCIE bit is always readable and writable. The CCIE bit enables an interrupt in case the command completion flag, CCIF in the CFMUSTAT register, is set. 1 = An interrupt is requested when the CCIF flag is set. 0 = CCIF interrupt disabled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-7...
- Page 246 < 102.4 MHz. The CFMCLKD register bits PRDIV8 and DIV must be set with appropriate values before programming or erasing the CFM flash memory Section 17.4.2.3.1, “Writing the CFMCLKD Register.” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-8 Freescale Semiconductor...
- Page 247 This value was chosen because it represents the ColdFire HALT instruction, making it unlikely that a user compiled code accidentally programmed at the security configuration field location would unintentionally secure the flash memory. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-9...
- Page 248 Each flash logical sector can be protected from program and erase operations by setting the PROTECT PROTECT[M] bit. PROTECT[M] = 1: Flash logical sector M is protected. PROTECT[M] = 0: Flash logical sector M is not protected. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-10 Freescale Semiconductor...
- Page 249 Each MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-11...
- Page 250 DACC DACC[M] = 1: Flash logical sector M is placed in data address space. DACC[M] = 0: Flash logical sector M is placed in data and instruction address space. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-12 Freescale Semiconductor...
- Page 251 0 to the PVIOL flag has no effect on PVIOL. While the PVIOL flag is set, it is not possible to launch a command or start a command write sequence. 1 = Protection violation has occurred. 0 = No protection violation has been detected. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-13...
- Page 252 Valid flash memory commands are shown in Table 17-13. Writing a command other than those listed in Table 17-13 during a command write sequence causes the ACCERR flag in the CFMUSTAT register to set. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-14 Freescale Semiconductor...
- Page 253 Table 17-15. Clock Select States CLKSEL[1:0] Description Burst Read Access 2’b10 Single-Cycle Flash Block Read Access 1-1-1-1 All other combinations Two-cycle Flash Block Read Access 2-1-1-1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-15...
-
Page 254: Functional Description
Buffer empty as well as command completion are signaled by flags in the CFMUSTAT register with interrupts generated, if enabled. The next four sections describe the following: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-16 Freescale Semiconductor... - Page 255 Command Write Sequence The flash command controller is used to supervise the command write sequence to execute blank check, page erase verify, program, page erase, and mass erase algorithms. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-17...
- Page 256 17-11, upon command completion. Program Program a 32-bit word. Page Erase Erase a flash logical page. Mass Erase Erase the entire flash memory. All flash memory protection must be disabled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-18 Freescale Semiconductor...
- Page 257 (CCIF=1), the BLANK flag sets in the CFMUSTAT register if the entire flash memory is erased. If any flash memory location is not erased, the blank check operation terminates and the BLANK flag remains clear. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-19...
- Page 258 Blank Check BLANK Verify Status Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 Flash Memory Flash Memory EXIT EXIT Erased Not Erased Figure 17-14. Example Blank Check Command Flow MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-20 Freescale Semiconductor...
- Page 259 If any address in the selected flash logical page is not erased, the page erase verify operation terminates and the BLANK flag remains clear. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-21...
- Page 260 Verify Status Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 Flash Logical Page EXIT Flash Logical Page EXIT Erased Not Erased Figure 17-15. Example Page Erase Verify Command Flow MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-22 Freescale Semiconductor...
- Page 261 CFMUSTAT register sets and the program command does not launch. After the program command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the program operation has completed unless a new command write sequence has been buffered. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-23...
- Page 262 Address, Data, CBEIF Next Write? Command Set? Buffer Empty Check Read: Register CFMUSTAT • Bit Polling for CCIF Command Set? Completion Check EXIT Figure 17-16. Example Program Command Flow MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-24 Freescale Semiconductor...
- Page 263 CFMUSTAT register sets and the page erase command does not launch. After the page erase command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the page erase operation has completed, unless a new command write sequence has been buffered. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-25...
- Page 264 Address, Data, CBEIF Next Write? Command Set? Buffer Empty Check Read: Register CFMUSTAT • Bit Polling for CCIF Command Set? Completion Check EXIT Figure 17-17. Example Page Erase Command Flow MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-26 Freescale Semiconductor...
- Page 265 After the mass erase command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the mass erase operation has completed, unless a new command write sequence has been buffered. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-27...
- Page 266 1. Writing to the flash memory before initializing CFMCLKD. 2. Writing to the flash memory while CBEIF is not set. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-28 Freescale Semiconductor...
- Page 267 If a command is not active (CCIF=1) when the MCU enters stop mode, the ACCERR flag does not set. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-29...
- Page 268 The contents of the flash security word at address offset 0x0414 must be changed by programming that address when the device is unsecured and the sector containing the flash configuration field is unprotected. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 17-30 Freescale Semiconductor...
- Page 269 Doing so clears the flash security (FS) bit in the EzPort status register (see Section 21.4.1.3, “Read Status Register”), after which a reset chip (RESET) command can be issued to regain access to the device. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 17-31...
-
Page 270: Fast Ethernet Controller (Fec)
— Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode 18.2 Modes of Operation The primary operational modes are described in this section. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-1... -
Page 271: Fec Top-Level Functional Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-2 Freescale Semiconductor... - Page 272 FEC data only, and is not related to the DMA controller described in Chapter 20, “DMA Controller Module,” nor to the DMA timers described in Chapter 24, “DMA Timers (DTIM0–DTIM3).” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-3...
-
Page 273: Functional Description
By deasserting ECR[ETHER_EN], the configuration control registers such as the TCR and RCR are not reset, but the entire data path is reset. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-4 Freescale Semiconductor... - Page 274 Table 18-3. Table 18-3. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-5...
- Page 275 EMAC pin Transmit Clock ETXCLK Transmit Enable ETXEN Transmit Data ETXD[3:0] Transmit Error ETXER Collision ECOL Carrier Sense ECRS Receive Clock ERXCLK Receive Data Valid ERXDV Receive Data ERXD[3:0] MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-6 Freescale Semiconductor...
- Page 276 Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC is appended to the frame data regardless of MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-7...
- Page 277 When ERXDV asserts, the receiver first checks for a valid PA/SFD header. If the PA/SFD is valid, it is stripped and the frame is processed by the receiver. If a valid PA/SFD is not found, the frame is ignored. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-8 Freescale Semiconductor...
- Page 278 Figure 18-2. Otherwise, if the DA is not a broadcast address, then the microcontroller runs the address recognition subroutine, as shown in Figure 18-3. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-9...
- Page 279 MISS bit in the receive buffer descriptor is set. Otherwise, the frame is rejected. In general, when a frame is rejected, it is flushed from the FIFO. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-10 Freescale Semiconductor...
- Page 280 BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid PAUSE frame received Figure 18-2. Ethernet Address Recognition—Receive Block Decisions MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-11...
- Page 281 Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-12 Freescale Semiconductor...
- Page 282 3b:ff:ff:ff:ff:ff 7b:ff:ff:ff:ff:ff 5b:ff:ff:ff:ff:ff 27:ff:ff:ff:ff:ff 0x10 07:ff:ff:ff:ff:ff 0x11 57:ff:ff:ff:ff:ff 0x12 77:ff:ff:ff:ff:ff 0x13 f7:ff:ff:ff:ff:ff 0x14 c7:ff:ff:ff:ff:ff 0x15 97:ff:ff:ff:ff:ff 0x16 a7:ff:ff:ff:ff:ff 0x17 99:ff:ff:ff:ff:ff 0x18 b9:ff:ff:ff:ff:ff 0x19 f9:ff:ff:ff:ff:ff 0x1a c9:ff:ff:ff:ff:ff 0x1b 59:ff:ff:ff:ff:ff 0x1c MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-13...
- Page 283 0x2e ef:ff:ff:ff:ff:ff 0x2f 93:ff:ff:ff:ff:ff 0x30 b3:ff:ff:ff:ff:ff 0x31 f3:ff:ff:ff:ff:ff 0x32 d3:ff:ff:ff:ff:ff 0x33 53:ff:ff:ff:ff:ff 0x34 73:ff:ff:ff:ff:ff 0x35 23:ff:ff:ff:ff:ff 0x36 13:ff:ff:ff:ff:ff 0x37 3d:ff:ff:ff:ff:ff 0x38 0d:ff:ff:ff:ff:ff 0x39 5d:ff:ff:ff:ff:ff 0x3a 7d:ff:ff:ff:ff:ff 0x3b fd:ff:ff:ff:ff:ff 0x3c MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-14 Freescale Semiconductor...
- Page 284 (graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are deasserted internally. The user must specify the desired pause duration in the OPD register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-15...
- Page 285 FIFO underrun and receive FIFO overflow. For external loopback, set RCR[LOOP] and RCR[DRT] equal to 0 and configure the external transceiver for loopback. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-16 Freescale Semiconductor...
- Page 286 If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the RxBD. All subsequent data in the frame is discarded and subsequent frames may also be MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-17...
-
Page 287: Programming Model
IPSBAR + 0x1200-12FF MIB Block Counters 18.5.2 Detailed Memory Map (Control/Status Registers) Table 18-10 shows the FEC register memory map with each register address, name, and a brief description. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-18 Freescale Semiconductor... - Page 288 FEC only supports frame lengths up to 2047 bytes. The RMON counters are implemented independently for transmit and receive to ensure accurate network statistics when operating in full duplex mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-19...
- Page 289 IEEE_T_EXCOL Frames Transmitted with Excessive Collisions 0x1264 IEEE_T_MACERR Frames Transmitted with Tx FIFO Underrun 0x1268 IEEE_T_CSERR Frames Transmitted with Carrier Sense Error 0x126C IEEE_T_SQE Frames Transmitted with SQE Error MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-20 Freescale Semiconductor...
- Page 290 Receive Fifo Overflow count 0x12DC IEEE_R_FDXFC Flow Control Pause frames received 0x12E0 IEEE_R_OCTETS_OK Octet count for Frames Rcvd w/o Error 18.5.4 Registers The following sections describe each register in detail. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-21...
- Page 291 Babbling transmit error. This bit indicates that the transmitted frame length has exceeded BABT RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not occur. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-22 Freescale Semiconductor...
- Page 292 Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded. 18–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-23...
- Page 293 EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source (see Table 18-12) is masked. 1 The corresponding interrupt source (see Table 18-12) is not masked. 18–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-24 Freescale Semiconductor...
- Page 294 Set to one when this register is written, regardless of the value written. Cleared by the FEC device R_DES_ACTIVE when no additional empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-25...
- Page 295 Set to one when this register is written, regardless of the value written. Cleared by the FEC device when X_DES_ACTIVE no additional ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-26 Freescale Semiconductor...
- Page 296 The device may be operated with an external Ethernet PHY. However, due to the shared pin groups, the use of an external PHY limits ADC, interrupt, and QSPI functionality, and disables the UART0/1 and 16-bit timers (see Table 2-1). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-27...
- Page 297 To perform a read or write operation on the MII Management Interface, the MMFR register must be written by the user. To generate a valid read or write management frame, the ST field must be written with MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-28 Freescale Semiconductor...
- Page 298 (intended for manufacturing test) of an internal counter used in generating the EMDC clock signal. IPSBAR Access: User read/write Offset: 0x1044 (MSCR) Reset DIS_ PREA MII_SPEED MBLE Reset MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-29...
- Page 299 MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See Table 18-11 for the locations of the MIB counters. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-30 Freescale Semiconductor...
- Page 300 A read/write control bit. If set, the MIB logic halts and does not update any MIB counters. MIB_DISABLE A read-only status bit. If set the MIB block is not currently updating any MIB counters. MIB_IDLE 29–0 Reserved. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-31...
- Page 301 Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit LOOP output signals are not asserted. The system clock is substituted for the ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-32 Freescale Semiconductor...
- Page 302 1, transmission stops after the collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit FIFO that are transmitted when GTS is reasserted. To avoid this deassert ECR[ETHER_EN] following the GRA interrupt. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-33...
- Page 303 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to PADDR1 be used for exact match, and the Source Address field in PAUSE frames. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-34 Freescale Semiconductor...
- Page 304 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, PADDR2 and the Source Address field in PAUSE frames. 15–0 Type field in PAUSE frames. These 16 bits are a constant value of 0x8808. TYPE MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-35...
- Page 305 Table 18-25. OPD Field Descriptions Field Description 31–16 Opcode field used in PAUSE frames. OPCODE These bits are a constant, 0x0001. 15–0 Pause Duration field used in PAUSE frames. PAUSE_DUR MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-36 Freescale Semiconductor...
- Page 306 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive IADDR1 frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-37...
- Page 307 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive IADDR2 frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-38 Freescale Semiconductor...
- Page 308 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address GADDR1 recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-39...
- Page 309 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address GADDR2 recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-40 Freescale Semiconductor...
- Page 310 Reserved, should be cleared. 1–0 Number of bytes written to transmit FIFO before transmission of a frame begins X_WMRK 0x 64 bytes written 10 128 bytes written 11 192 bytes written MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-41...
- Page 311 Table 18-31. FRBR Field Descriptions Field Description 31–10 Reserved, read as 0 (except bit 10, which is read as 1). 9–2 Read-only. Highest valid FIFO RAM address. R_BOUND 1–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-42 Freescale Semiconductor...
- Page 312 Reserved, read as 0 (except bit 10, which is read as 1). 9–2 Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. R_FSTART 1–0 Reserved, read as 0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-43...
- Page 313 Figure 18-24. Receive Descriptor Ring Start Register (ERDSR) Table 18-33. ERDSR Field Descriptions Field Description 31–2 Pointer to start of receive buffer descriptor queue. R_DES_START 1–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-44 Freescale Semiconductor...
- Page 314 Figure 18-25. Transmit Buffer Descriptor Ring Start Register (ETDSR) Table 18-34. ETDSR Field Descriptions Field Description 31–2 Pointer to start of transmit buffer descriptor queue. X_DES_START 1–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-45...
- Page 315 Figure 18-26. Receive Buffer Size Register (EMRBR) Table 18-35. EMRBR Field Descriptions Field Description 30–11 Reserved, should be cleared. 10–4 Receive buffer size. R_BUF_SIZE 3–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-46 Freescale Semiconductor...
-
Page 316: Buffer Descriptors
If the TxBDs are set up in order, the DMA Controller could DMA the first BD before the 2nd was made available, potentially causing a transmit FIFO underrun. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-47... - Page 317 When the buffer has been DMA’d, the Ethernet controller modifies the E, L, M, BC, MC, LG, NO, CR, OV, and TR bits and write the length of the used portion of the buffer in the first longword. The M, BC, MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-48 Freescale Semiconductor...
- Page 318 1 The frame was received because of promiscuous mode. Offset + 0 Bit 7 Set if the DA is broadcast (FF-FF-FF-FF-FF-FF). Offset + 0 Bit 6 Set if the DA is multicast and not BC. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-49...
- Page 319 Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 18.5.3, “MIB Block Counters Memory Map” for more details. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-50 Freescale Semiconductor...
- Page 320 Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA engine, bits[4:0] are ignored. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 18-51...
- Page 321 R bit in the first BD for the frame. The driver should follow that with a write to TDAR which triggers the FEC to poll the next BD in the ring. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 18-52 Freescale Semiconductor...
-
Page 322: Ethernet Physical Transceiver (Ephy)
MDC rates up to 25 MHz • Supports MDIO preamble suppression • Jumbo packet • 2.5 V CMOS • 2.5 V MII interface • 125 MHz clock generator and timing recovery • Loopback modes MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-1... - Page 323 PHY_RBIAS MII_TXEN PHY SUB Block MII_TXD[3:0] MII_TXER MII_CRS MII_COL MII_MDC MII_MDIO MII Interface IP Bus IP Bus Registers Signals REF Clock Figure 19-1. Ethernet Physical Transceiver (EPHY) Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-2 Freescale Semiconductor...
-
Page 324: External Signal Descriptions
Ethernet twisted-pair output pin. This pin is high-impedance out of reset. 19.2.3 PHY_RXP — EPHY Twisted Pair Input + Ethernet twisted-pair input pin. This pin is high-impedance out of reset. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-3... - Page 325 Indicates the speed of a link, which can be 10 Mbps or 100 Mbps if EPHYCTL0 LEDEN bit is set. 19.2.12 LNKLED — Link LED Indicates whether a link is established with another network device if EPHYCTL0 LEDEN bit is set. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-4 Freescale Semiconductor...
-
Page 326: Memory Map And Register Descriptions
19.3.2.1 Ethernet Physical Transceiver Control Register 0 (EPHYCTL0) IPSBAR Access: User read/write Offset: 0x1E_0000 (EPHYCTL0) EPHYEN ANDIS DIS100 DIS10 LEDEN EPHYWAI EPHYIEN Reset Figure 19-3. Ethernet Physical Transceiver Control Register 0 (EPHYCTL0) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-5... - Page 327 0 Allows the EPHY module to continue running during wait. Reserved, should be cleared. EPHY Interrupt Enable. EPHYIEN This bit can be written anytime. 1 Enables EPHY module interrupts 0 Disables EPHY module interrupts MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-6 Freescale Semiconductor...
- Page 328 EPHY Port 10BASE-T mode status. 10DIS This bit is not writable. Output to indicate EPHY port 10BASE-T mode status. 1 EPHY port 10BASE-T disabled 0 EPHY port 10BASE-T enabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-7...
- Page 329 Proprietary Control Register Read/Write Write has no effect. Always reads 0x00. NOTE Bit notation for MII registers is: Bit 20.15 refers to MII register address 20 and bit number 15. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-8 Freescale Semiconductor...
- Page 330 MII_TXDx, MII_TXEN, and MII_TXER inputs, and it presents high impedance on MII_TXCLK, MII_RXCLK, MII_RXDV, MII_RXER, MII_RXDx, MII_COL, and MII_CRS outputs. The port responds to management transactions while in isolate mode. 0 Normal operation MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-9...
- Page 331 1 Forces the PHY to assert the MII_COL signal within 512 bit times from the assertion of MII_TXEN and de-assert MII_COL within 4 bit times of MII_TXEN being de-asserted. 0 Normal operation 6–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-10 Freescale Semiconductor...
- Page 332 1 Indicates that the auto-negotiation process has completed and that the contents of registers 4 through 7 are valid. 0 Indicates that the auto-negotiation process has not completed and that the contents of registers 4 through 7 are not valid MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-11...
- Page 333 1 Indicates that the extended register set (registers 2–31) has been implemented in the PHY. 0 Indicates that the extended register set (registers 2–31) has NOT been implemented in the PHY MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-12 Freescale Semiconductor...
- Page 334 A/N advertisement register. On power-up, before A/N starts, the register sets the selector field, bits 4.4:0, to 00001 to indicate that it is IEEE Standard 802.3 compliant. The MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-13...
- Page 335 1 10BASE-T half-duplex capable 0 Not 10BASE-T half-duplex capable 4–0 Selector field. This field is set to 0b1 at power-up to indicate that the module complies with the IEEE SELECTORFIELD 802.3 standard. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-14 Freescale Semiconductor...
- Page 336 1 Link partner is 100BASE-TX half-duplex capable 0 Link partner is not 100BASE-TX half-duplex capable 10BASE-T Full-Duplex TAF10FD 1 Link partner is10BASE-T full-duplex capable 0 Link partner is not 10BASE-T full-duplex capable MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-15...
- Page 337 0 Previous value of the transmitted link code word equalled 1 10–0 Message/Unformatted Code Field CODEFIELD Message code field — Predefined code fields defined in IEEE 802.3u-1995 Annex 28C Unformatted code filed — 11-bit field containing an arbitrary value MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-16 Freescale Semiconductor...
- Page 338 0 Three identical and consecutive link code words have not been received from link partner Link Partner A/N Able LPANA Indicates whether the link partner has A/N capabilities. 1 Link partner is A/N able 0 Link partner is not A/N able MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-17...
- Page 339 The PHY register set includes registers 16 through 29. These registers are not part of the MCU memory map. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-18 Freescale Semiconductor...
- Page 340 1 A new page has been received from the link partner 0 A new page has not been received from the link partner since the last access of this register (Bit 1 was set by a page received event) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-19...
- Page 341 Link Status This is a duplicate of LNKSTAT bit 2 of the status register (1.2). 1 Link is down 0 Link is up Duplex Mode DPMD 1 Full-duplex 0 Half-duplex MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-20 Freescale Semiconductor...
- Page 342 Far End Fault Disable FEFLTD 1 Far end fault detect is disabled 0 Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation is disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-21...
-
Page 343: Functional Description
EPHY register map. There are five basic modes of operation for the EPHY: • Power down/initialization • Auto-negotiate • 10BASE-T • 100BASE-TX • Low-power MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-22 Freescale Semiconductor... - Page 344 ANDIS, DIS100, and DIS10 Set EPHYEN=1 PHYADD[4:0] and ANDIS become latched in MII registers Delay for tStart-up Configure MII registers via MDIO Initialization Complete Figure 19-18. EPHY Start-Up / Initialization Sequence MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-23...
- Page 345 (symbol mode) — unaligned 100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), aligned 100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), unaligned 100BASE-TX half-duplex Symbol mode is not supported. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-24 Freescale Semiconductor...
- Page 346 The receive block determines the capabilities of the link partner and writes to the link partner ability register (register 5). The arbitration block determines the highest common mode of operation to establish the link. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-25...
- Page 347 MII. A 2.5 MHz internal clock is used for nibble wide transactions. A 10 MHz internal clock is used for serial transactions. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-26 Freescale Semiconductor...
- Page 348 Link Integrity Test: Used to determine whether the 10BASE-T link is operational. If neither data nor a link pulse is received for 64 ms, then the link is considered down. While the link is down, the transmit, MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-27...
- Page 349 The EPHY implementation includes the physical coding sublayer (PCS), the physical medium attachment (PMA), and the physical medium dependent (PMD) sublayer. The block diagram for 100BASE-TX operation is shown in Figure 19-22. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-28 Freescale Semiconductor...
- Page 350 Carrier sense is de-asserted when the ESD (end-of-stream) delimiter, the TR symbol pair, is found, or when an idle state is detected. In half-duplex, CRS is also asserted on transmit. Parallel to Serial: This block takes parallel data and converts it to serial format. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-29...
- Page 351 Baseline wander reduces noise immunity because the base line moves nearer to the positive or negative signal comparators. To correct for this EPHY uses DC MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-30 Freescale Semiconductor...
- Page 352 Upon exiting stop mode, the EPHY exits the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers. The MII registers have to be re-initialized after the start-up delay (t ) has expired. Start-up MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 19-31...
- Page 353 In this mode all analog blocks except the PLL clock generator and band gap reference are in low power mode. All digital blocks except the MDIO interface and management registers are inactive. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 19-32 Freescale Semiconductor...
-
Page 354: Dma Controller Module
(SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART and GPIOs. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-1... - Page 355 Continuous-mode or cycle-steal transfers • Independent transfer widths for source and destination • Independent source and destination address registers • Modulo addressing on source and destination addresses • Automatic channel linking MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-2 Freescale Semiconductor...
-
Page 356: Dma Transfer Overview
This section describes each internal register and its bit assignment. Modifying DMA control registers during a DMA transfer can result in undefined operation. Table 20-1 shows the mapping of DMA controller registers. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-3... - Page 357 If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate external DREQn signal activates channel n. IPSBAR Access: read/write Offset: 0x00_0014 (DMAREQC) Reset DMAC3 DMAC2 DMAC1 DMAC0 Reset Figure 20-3. DMA Request Control Register (DMAREQC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-4 Freescale Semiconductor...
- Page 358 The backdoor enable bit must be set in the SCM RAMBAR, as well as the secondary port valid bit in the core RAMBAR to enable backdoor accesses from the DMA to SRAM. See Section 11.2.1, “SRAM Base Address Register (RAMBAR),” for more details. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-5...
- Page 359 20-7. In response to an event, the DMA controller writes to the appropriate DSRn bit. Only a write to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer is complete. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-6 Freescale Semiconductor...
- Page 360 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-7...
- Page 361 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-8 Freescale Semiconductor...
- Page 362 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-9...
- Page 363 Disable request. DMA hardware automatically clears the corresponding DCRn[EEXT] bit when the byte count D_REQ register reaches zero. 0 EEXT bit is not affected. 1 EEXT bit is cleared when the BCR is exhausted. Reserved; should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-10 Freescale Semiconductor...
-
Page 364: Functional Description
A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE]. See 20.3.5, “DMA Control Registers (DCRn).” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-11... - Page 365 If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BED, DONE] are set and DMA transactions stop. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-12 Freescale Semiconductor...
- Page 366 BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-13...
- Page 367 BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 20-14 Freescale Semiconductor...
- Page 368 DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 20-15...
-
Page 369: Ezport
The rest of the micro-controller is disabled when the EzPort is enabled to avoid conflicts. • Disabled—When the EzPort is disabled, the rest of the micro-controller can access flash memory as normal. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 21-1... -
Page 370: External Signal Description
EzPort clock (EZPCK) is the serial clock for data transfers. Serial data in (EZPD) and chip select (EZPCS) are registered on the rising edge of EZPCK while serial data out (EZPQ) is driven on the falling edge of MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 21-2... -
Page 371: Command Definition
FAST_READ Page Program 0x02 4 to 256 Sector Erase 0xD8 Bulk Erase 0xC7 RESET Reset Chip 0xB9 Lists the compatible commands on the ST Microelectronics Serial Flash Memory parts. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 21-3 Freescale Semiconductor... - Page 372 Bulk Erase command. The flag clears after a Read Status Register (RDSR) command. 0 No error on previous erase/program command. 1 Error on previous erase/program command. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 21-4...
- Page 373 This command should not be used if the write error flag is set, a write is in progress, or the configuration register has already been loaded (as it is a write-once register). IPSBAR Access: read/write Offset: PRDIV8 DIV[5:0] Reset: Figure 21-3. EzPort Configuration Register MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 21-5 Freescale Semiconductor...
- Page 374 The write error flag sets if there is an attempt to program a protected area of the flash memory. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 21-6...
-
Page 375: Functional Description
The serial data out from the EzPort is tri-stated unless data is being driven, allowing the signal to be shared among several different EzPort (or compatible) devices in parallel, provided they have different chip selects. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 21-7 Freescale Semiconductor... -
Page 376: Initialization/Application Information
For proper program and erase operations, it is critical to set FCLK between 150 kHz and 200 kHz. Array damage due to overstress can occur when FCLK is less than 150 kHz. Incomplete programming and erasure can occur when FCLK is greater than 200 kHz. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 21-8... -
Page 377: Programmable Interrupt Timers (Pit0-Pit1)
Low-power modes are described in the power management module, Chapter 9, “Power Management.” Table 22-1 shows the PIT module operation in low-power modes and how it can exit from each mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 22-1... -
Page 378: Memory Map/Register Definition
22.2.2/22-4 0x16_0002 User/Supervisor Access Registers 0x15_0004 PIT Count Register (PCNTRn) 0xFFFF 22.2.3/22-5 0x16_0004 Accesses to reserved address locations have no effect and result in a cycle termination transfer error. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 22-2... - Page 379 0 PIT function not affected in doze mode 1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 22-3 Freescale Semiconductor...
- Page 380 PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF. IPSBAR 0x15_0002 (PMR0) Access: Supervisor Offset: 0x16_0002 (PMR1) read/write Reset Figure 22-3. PIT Modulus Register (PMRn) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 22-4...
-
Page 381: Functional Description
PIF flag issues an interrupt request to the CPU. When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 22-5 Freescale Semiconductor... - Page 382 Eqn. 22-1 Timeout period sys/2 22.3.4 Interrupt Operation Table 22-6 shows the interrupt request generated by the PIT. Table 22-6. PIT Interrupt Requests Interrupt Request Flag Enable Bit Timeout MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 22-6...
- Page 383 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 22-7 Freescale Semiconductor...
-
Page 384: Introduction
Four 16-bit input capture/output compare channels • 16-bit architecture • Programmable prescaler • Pulse widths variable from microseconds to seconds • Single 16-bit pulse accumulator • Toggle-on-overflow feature for pulse-width modulator (PWM) generation MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-1... - Page 385 EDGE PAOVF DETECT GPTPACNTH:GPTPACNTL PAIF PACLK/65536 16-Bit Counter Divide System PACLK/256 PACLK Divide-by-64 by 2 Clock Interrupt Interrupt PAMOD Request Logic PAOVI PAOVF PAIF Figure 23-1. GPT Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-2 Freescale Semiconductor...
- Page 386 This pin is available for general-purpose I/O when not configured for timer functions. 23.6 Memory Map and Registers Table 23-3 shows the memory map of the GPT module. The base address for GPT is IPSBAR + 0x1A_0000. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-3...
- Page 387 Pulse Accumulator Flag Register (GPTPAFLG) 0x00 23.6.16/23-14 0x1A_001A Pulse Accumulator Counter Register High 23.6.17/23-15 (GPTPACNTH) 0x1A_001B Pulse Accumulator Counter Register Low (GPTPACNTL) 23.6.17/23-15 0x1A_001D GPT Port Data Register (GPTPORT) 0x00 23.6.18/23-16 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-4 Freescale Semiconductor...
- Page 388 1 Output compare enabled 0 Input capture enabled 23.6.2 GPT Compare Force Register (GPCFORC) IPSBAR Access: Supervisor read/write Offset: 0x1A_0001 (GPCFORC) Reset: Figure 23-3. GPT Input Compare Force Register (GPCFORC) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-5...
- Page 389 (IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write anytime. 1 Corresponding PORTTn pin configured as output 0 No effect MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-6 Freescale Semiconductor...
- Page 390 The write occurs at least one cycle before the synchronization of the prescaler clock. These bits are read anytime. They should be written to only in test (special) mode; writing to them has no effect in normal modes. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-7...
- Page 391 0 Normal flag clearing 3–0 Reserved, should be cleared. Write GPTFLG1 Register Data Bit n Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 23-8. Fast Clear Flag Logic MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-8 Freescale Semiconductor...
- Page 392 Note: Channel 3 shares a pin with the pulse accumulator input pin. To use the PAI input, clear the OM3 and OL3 bits and clear the OC3M3 bit in the output compare 3 mask register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-9...
- Page 393 Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-10 Freescale Semiconductor...
- Page 394 111 Prescaler divisor 128 Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to 0x0000.) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-11...
- Page 395 6–0 Reserved, should be cleared. Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-12 Freescale Semiconductor...
- Page 396 Note: The pulse accumulator can operate in event mode even when the GPT enable bit, GPTEN, is clear. Pulse accumulator mode. Selects event counter mode or gated time accumulation mode. PAMOD 1 Gated time accumulation mode 0 Event counter mode MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-13...
- Page 397 IPSBAR Access: Supervisor read/write Offset: 0x1A_0019 (GPTPAFLG) PAOVF PAIF Reset: Figure 23-18. Pulse Accumulator Flag Register (GPTPAFLG) Table 23-19. GPTPAFLG Field Descriptions Field Description 7–2 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-14 Freescale Semiconductor...
- Page 398 To ensure coherent reading of the PA counter so that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-15...
- Page 399 Control the port logic of PORTTn. Reset clears the PORTTn data direction register, configuring all GPT port pins as inputs. These bits are read anytime, write anytime. 1 Corresponding pin configured as output 0 Corresponding pin configured as input MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-16 Freescale Semiconductor...
-
Page 400: Functional Description
GPT counter even if the OC3/PAI pin is being used as the pulse accumulator input. An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-17... - Page 401 The trailing edge of the active level at the PAI pin sets the PA input flag (PAIF). The PA input interrupt enable bit (PAI) enables the PAIF flag to generate interrupt requests. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-18 Freescale Semiconductor...
- Page 402 To configure a pin for output compare: 1. Set the pin’s IOS bit in GPTIOS. 2. Write the output compare value to GPTCn. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-19...
- Page 403 OMn/OLn bit pairs select the output action to be taken as a result of a successful output compare. When OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-20 Freescale Semiconductor...
- Page 404 PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 23-21...
- Page 405 When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 23-22 Freescale Semiconductor...
-
Page 406: Introduction
The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 14, “General Purpose I/O Module”) prior to configuring the DMA Timers. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-1... - Page 407 Free run and restart modes • Programmable interrupt or DMA request on input capture or reference-compare • Ability to stop the timer from counting when the ColdFire core is halted MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 24-2 Freescale Semiconductor...
- Page 408 The DTMRn registers program the prescaler and various timer modes. IPSBAR 0x00_0400 (DTMR0) Access: User read/write Offset: 0x00_0440 (DTMR1) 0x00_0480 (DTMR2) 0x00_04C0 (DTMR3) ORRI FRR Reset Figure 24-2. DTMRn Registers MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-3...
- Page 409 RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled. 0 Reset timer (software reset) 1 Enable timer MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 24-4 Freescale Semiconductor...
- Page 410 If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-5...
- Page 411 Capture on rising edge and trigger DMA Capture on falling edge and trigger interrupt Capture on falling edge and trigger DMA Capture on any edge and trigger interrupt Capture on any edge and trigger DMA MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 24-6 Freescale Semiconductor...
- Page 412 Figure 24-6. DTCRn Registers Table 24-6. DTCRn Field Descriptions Field Description 31–0 Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTIN , as programmed in DTMRn. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-7...
- Page 413 Each DMA timer can be configured to count up to a reference value. If the reference value is met, DTERn[REF] is set. • If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. • If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 24-8 Freescale Semiconductor...
- Page 414 DTCN1 EQU IPSBARx+0x44C ;Timer1 counter register DTER0 EQU IPSBARx+0x403 ;Timer0 event register DTER1 EQU IPSBARx+0x443 ;Timer1 event register * TMR0 is defined as: * *[PS] = 0xFF, divide clock by 256 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-9...
- Page 415 When calculating time-out periods, add one to the prescaler to simplify calculating, because DTMRn[PS] equal to 0x00 yields a prescaler of one, and DTMRn[PS] equal to 0xFF yields a prescaler of 256. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 24-10 Freescale Semiconductor...
- Page 416 For example, if a 60-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0xFBC5 (64,453 decimal), the time-out period is: × × × ---------------------------- - Timeout period 64453 2.20 seconds Eqn. 24-2 × MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 24-11...
-
Page 417: Introduction
Rx/Tx Data Reg. Logic Array Control QSPI_DOUT Regs Command QSPI_CS[3:0] Delay Counter Internal Bus Internal Bus Baud Rate Divide by 2 QSPI_CLK Generator Clock (f Figure 25-1. QSPI Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-1... -
Page 418: External Signal Description
Although QSPI_CSn signals function as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-2... -
Page 419: Memory Map/Register Definition
(QMR[MSTR]) must be set for the QSPI module to operate correctly. IPSBAR 0x00_0340 (QMR) Access: User read/write Offset: MSTR BITS CPOL CPHA BAUD Reset Figure 25-2. QSPI Mode Register (QMR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-3 Freescale Semiconductor... - Page 420 A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: / (2 × [desired QSPI_CLK baud rate]) QMR[BAUD] = f sys/ MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-4...
- Page 421 7–0 Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-5 Freescale Semiconductor...
- Page 422 The QIR contains QSPI interrupt enables and status flags. IPSBAR 0x00_034C (QIR) Access: User read/write Offset: WCEF ABRT SPIF WCEFB ABRTB ABRTL WCEFE ABRTE SPIFE Reset Figure 25-6. QSPI Interrupt Register (QIR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-6...
- Page 423 A read or write to the QSPI RAM causes QAR to increment. However, the QAR does not wrap after the last queue entry within each section of the RAM. The application software must manage address range errors. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-7 Freescale Semiconductor...
- Page 424 RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-8...
-
Page 425: Functional Description
The QSPI uses a dedicated 80-byte block of static RAM accessible to the module and CPU to perform queued operations. The RAM is divided into three segments: • 16 command control bytes (command RAM) • 32 transmit data bytes (transmit data RAM) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-9 Freescale Semiconductor... - Page 426 The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-10...
- Page 427 Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. Read this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-11 Freescale Semiconductor...
- Page 428 QSPI_CLK rate from the internal bus clock divided by two. Table 25-10 shows the QSPI_CLK frequency as a function of internal bus clock and baud rate. A baud rate value of zero turns off the QSPI_CLK. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-12...
- Page 429 (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1: × QDLYR[DTL] ----------------------------------------------- - Eqn. 25-3 Delay after transfer (DT = 1) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-13 Freescale Semiconductor...
- Page 430 QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 25-14...
-
Page 431: Initialization/Application Information
11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 25-15 Freescale Semiconductor... - Page 432 Logic Programmable Internal Bus Clock (f Clock Transmit DMA Request DMA Request Generation or External Clock (DTINn) Logic Receive DMA Request (To DMA Controller) Figure 26-1. UART Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-1...
- Page 433 All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-2 Freescale Semiconductor...
- Page 434 Writing control bytes into the appropriate registers controls the operation of the UART module. NOTE UART registers are accessible only as bytes. NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-3...
- Page 435 Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-4 Freescale Semiconductor...
- Page 436 Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-5...
- Page 437 Access: User read/write Offset: 0x00_0240 (UMR21) 0x00_0280 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 26-4. UART Mode Registers 2 (UMR2n) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-6 Freescale Semiconductor...
- Page 438 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-7...
- Page 439 1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-8 Freescale Semiconductor...
- Page 440 The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, cannot be RESET TRANSMITTER ENABLE TRANSMITTER specified in one command. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-9...
- Page 441 Transmitter must be enabled for the command to be accepted. This command ignores the state of UCTSn. Causes UTXDn to go high (mark) within two bit times. Any characters in the STOP BREAK transmit buffer are sent. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-10 Freescale Semiconductor...
- Page 442 FIFO. URXDn is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 26-18). RB contains the character in the receiver. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-11...
- Page 443 The UIPCRs hold the current state and the change-of-state for UCTSn. IPSBAR 0x00_0210 (UIPCR0) Access: User read-only Offset: 0x00_0250 (UIPCR1) 0x00_0290 (UIPCR2) Reset: UCTSn Figure 26-10. UART Input Port Changed Registers (UIPCRn) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-12 Freescale Semiconductor...
- Page 444 UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-13...
- Page 445 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-14 Freescale Semiconductor...
- Page 446 The UIPn registers show the current state of the UCTSn input. IPSBAR 0x00_0234 (UIP0) Access: User read-only Offset: 0x00_0274 (UIP1) 0x00_02B4 (UIP2) Reset: Figure 26-15. UART Input Port Registers (UIPn) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-15...
- Page 447 The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-16 Freescale Semiconductor...
- Page 448 When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: Eqn. 26-1 ----------------------------------- - Baudrate 32 x Divider MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-17...
- Page 449 UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on UTXDn. It automatically sends a start bit followed by the programmed number of data bits, an MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-18 Freescale Semiconductor...
- Page 450 The transmitter must be manually reenabled by reasserting URTSn before the next message is sent. Figure 26-19 shows the functional timing information for the transmitter. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-19...
- Page 451 (framing error) and URXDn remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error, MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-20 Freescale Semiconductor...
- Page 452 In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break (RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-21...
- Page 453 The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-22 Freescale Semiconductor...
- Page 454 Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until next valid start bit is detected. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-23...
- Page 455 Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in Figure 26-24. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-24 Freescale Semiconductor...
- Page 456 If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-25...
- Page 457 UART modules. 1. Initialize the appropriate ICRx register in the interrupt controller. 2. Unmask appropriate bits in IMR in the interrupt controller. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-26 Freescale Semiconductor...
- Page 458 The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-27...
- Page 459 8. Start the data transfer by setting DCRn[EEXT], which enables the UART channel to issue DMA requests. Table 26-14 shows the DMA requests. Table 26-14. UART DMA Requests Register DMA Request UISRn Receive DMA request UISRn Transmit DMA request MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-28 Freescale Semiconductor...
- Page 460 If preferred, program operation of transmitter ready-to-send (TXRTS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCRn: Enable transmitter and/or receiver. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-29...
- Page 461 Errors? SINIT Initiate: Channel Enable Receiver Interrupts CHK1 Assert Request To Send Call CHCHK SINITR Return Save Channel Status Figure 26-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-30 Freescale Semiconductor...
- Page 462 Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 26-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-31...
- Page 463 Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 26-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-32 Freescale Semiconductor...
- Page 464 Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR Figure 26-25. UART Mode Programming Flowchart (Sheet 4 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 26-33...
- Page 465 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 26-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 26-34 Freescale Semiconductor...
- Page 466 Register (I2FDR) (I2CR) (I2SR) (I2DR) (I2ADR) In/Out Clock Data Control Shift Register Start, Stop, Arbitration Control Input Address Sync Compare I2C_SCL I2C_SDA Figure 27-1. I C Module Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-1...
- Page 467 Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus-busy detection MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-2 Freescale Semiconductor...
- Page 468 Reserved, must be cleared. 27.2.2 C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 27-3, provides a programmable prescaler to configure the I C clock for bit-rate selection. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-3...
- Page 469 27.2.3 C Control Register (I2CR) I2CR enables the I C module and the I C interrupt. It also contains bits that govern operation as a slave or a master. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-4 Freescale Semiconductor...
- Page 470 Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration. RSTA 0 No repeat start 1 Generates a repeated START condition. 1–0 Reserved, must be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-5...
- Page 471 Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle. RXAK 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-6 Freescale Semiconductor...
- Page 472 I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-7...
- Page 473 Bit4 Bit3 Bit2 Bit1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Slave Address Data Byte STOP ACK from START ACK Bit Signal Receiver Signal Figure 27-8. Data Transfer MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-8 Freescale Semiconductor...
- Page 474 Figure 27-10. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-9...
- Page 475 Note: No acknowledge on the last byte Example 3: 7-bit Slave Rept 7-bit Slave Data Data Data Address Address Master Writes to Slave Master Reads from Slave Figure 27-11. Data Transfer, Combined Format MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-10 Freescale Semiconductor...
- Page 476 STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. I2C_SCL I2C_SDA by Master1 I2C_SDA by Master 2 Loses Arbitration, Master2 and becomes slave-receiver I2C_SDA Figure 27-13. Arbitration Procedure MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-11...
- Page 477 The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-12 Freescale Semiconductor...
- Page 478 2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-13...
- Page 479 MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 27-14 Freescale Semiconductor...
- Page 480 Read Data Generate Dummy Read Dummy Read Dummy Read from I2DR from I2DR STOP Signal from I2DR from I2DR And Store Figure 27-14. Flow-Chart of Typical I C Interrupt Routine MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 27-15...
- Page 481 1. In loop mode, the time between each conversion is 6 ADC clock cycles (1.2 μs at 5.0 MHz). Using simultaneous conversion, two samples are captured in 1.2 μs, providing an overall sample rate of 1.66 million samples per second. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-1...
- Page 482 Limit Status Register (ADLSTAT) 0x0000 28.4.7/28-13 0x19_0010 Zero Crossing Status Register (ADZCSTAT) 0x0000 28.4.8/28-14 0x19_0012–20 Result Registers 0-7 (ADRSLT0-7) 0x0000 28.4.9/28-14 0x19_0022–30 Low Limit Registers 0-7 (ADLLMT0-7) 0x0000 28.4.10/28-15 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-2...
- Page 483 START0 bit again is ignored until the end of the current scan. The ADC must be in a stable power configuration prior to writing to START0 (see Section 28.5.8, “Power Management”). 0 No action 1 Start command is issued MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-3 Freescale Semiconductor...
- Page 484 HLMTIE greater than the high limit register value. The raw result value is compared to ADHLMT[HLMT] before the offset register value is subtracted. 0 Interrupt disabled 1 Interrupt enabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-4...
- Page 485 Section 28.4.1, “Control 1 Register (CTRL1)”). 28.4.2.1 CTRL2 Under Sequential Scan Modes IPSBAR Access: read/write Offset: 0x19_0002 (CTRL2) Reset Figure 28-3. Control 2 Register (CTRL2) Under Sequential Scan Modes MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-5 Freescale Semiconductor...
- Page 486 The ADC must be in a stable power configuration prior to writing to START1 (see Section 28.5.8, “Power Management”). 0 No action 1 Start command is issued MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-6...
- Page 487 100 kHz 500 kHz 5.33 MHz CLK/12 00011 100 kHz 250 kHz 4.00 MHz CLK/16 00100 100 kHz 125 kHz 3.20 MHz CLK/20 — — — — — — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-7 Freescale Semiconductor...
- Page 488 AN0 through AN3, sample slots SAMPLE0-3 should only contain binary values between 000 and 011. Likewise, because converter B only has access to analog inputs AN4 through AN7, sample slots MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-8...
- Page 489 Sample input channel select 0. The settings for this field are given in Table 28-9. SAMPLE0 IPSBAR Access: read/write Offset: 0x19_0008 (ADLST2) SAMPLE7 SAMPLE6 SAMPLE5 SAMPLE4 Reset Figure 28-7. Channel List 2 Register (ADLST2) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-9 Freescale Semiconductor...
- Page 490 DS5 is set to 1, SAMPLE0 through SAMPLE4 are sampled. However, if in parallel mode and bits DS5 or DS1 are set to 1, only SAMPLE0 and SAMPLE4 are sampled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-10...
- Page 491 They are not cleared automatically on the next scan sequence. IPSBAR Access: read/write Offset: 0x19_000C (ADSTAT) R CIP0 CIP1 LLMTI HLMTI RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 EOSI1 EOSI0 Reset Figure 28-9. Status Register (ADSTAT) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-11 Freescale Semiconductor...
- Page 492 It is cleared by writing 1 to all active ADLSTAT[LLS] bits. 0 No low limit interrupt request 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-12...
- Page 493 0 Sample n is greater than or equal to the associated low-limit value 1 Sample n is less than the associated low-limit value Note: These bits are sticky, and can only be cleared by writing a 1 to them. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-13 Freescale Semiconductor...
- Page 494 Right shift with sign extend (ASR) three places to fit it into the range [0,4095] • Accept the number as presented in the register, knowing there are missing codes, because the lower three LSBs are always zero MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-14...
- Page 495 Limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high limit and 0x0000 for the low limit. At reset, limit checking is disabled. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-15 Freescale Semiconductor...
- Page 496 0x19_0040 (ADHLMT7) HLMT Reset Figure 28-14. High Limit Registers (ADHLMTn) Table 28-16. ADHLMTn Field Descriptions Field Description Reserved, should be cleared. 14–3 High limit. HLMT 2–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-16...
- Page 497 The ADC module is idle when neither of the two converters has a scan in process. 4. Active state The ADC module is active when at least one of the two converters has a scan in process. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-17 Freescale Semiconductor...
- Page 498 ADC is ready for operation. During auto power-down mode, this bit indicates the current powered state of converter B. 0 ADC converter B is currently enabled 1 ADC converter B is currently disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-18...
- Page 499 (powering-down) converter A and converter B automatically powers-down the voltage reference. 0 Manually power-up voltage reference circuit 1 Power-down voltage reference circuit is controlled by PD0 and PD1 (default) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-19 Freescale Semiconductor...
- Page 500 1 AN2 Select V Source bit. This bit selects the source of the V reference for conversions. REFL REFL SEL_VREFL 0 VRL 1 AN6 13–0 Reserved, should be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-20...
- Page 501 AN6-7. When configured as a differential pair, a reference to either member of the differential pair by a sample slot results in a differential measurement using that differential pair. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-21 Freescale Semiconductor...
- Page 502 SYNC inputs are ignored until the SYNC input is re-armed. This arming can occur anytime after the SYNC pulse occurs, even while the scan it initiated remains in process. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-22...
- Page 503 1-of-2 select function, such that either channel for the V- input of the A/D. of the two differential channels can be routed to the A/D input. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-23 Freescale Semiconductor...
- Page 504 Converter B Converter B Interface Interface Function Function V– V– REFL REFL Single-Ended Differential Channel Select Channel Select Single-Ended vs Single-Ended vs Differential Differential Figure 28-20. Input Select Mux MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-24...
- Page 505 A mix and match combination of differential and single-ended configurations may exist. Examples: • AN0 and AN1 differential, AN2 and AN3 single-ended • AN4 and AN5 differential, AN6 and AN7 single-ended MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-25 Freescale Semiconductor...
- Page 506 , return 0 when the plus (+) input is at V and the minus (−) input is at REFL REFL , and scale linearly between based on the voltage difference between the two signals. REFL MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-26...
- Page 507 3 bits (as shown in the ADRSLT register definition) and does not include the sign bit. The sign bit (SEXT) is calculated during subtraction of the corresponding ADOFSn offset value. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-27 Freescale Semiconductor...
- Page 508 SAMPLE slot may refer to any of the 8 analog inputs (AN0-7), thus the same input may be referenced by more than one SAMPLE slot. Scanning is initiated when the START0 bit is written as 1 or, if the SYNC0 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-28...
- Page 509 Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-29 Freescale Semiconductor...
- Page 510 During non-simultaneous scans, the A and B converters operate asynchronously with each converter using its own independent set of controls (CTRL1 for A and CTRL2 for B). Refer to Section 28.4.2.2, “CTRL2 Under Parallel Scan Modes,” for more information. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-30...
- Page 511 ADSDIS register or completes all 4 samples. If external sync is enabled (SYNC0=1), new scans are started for each sync pulse as long as the ADC has completed the previous scan (STAT[CIPn]=0). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-31 Freescale Semiconductor...
- Page 512 This hybrid mode converts at an ADC clock rate of 100 kHz using standby current mode when active, and gates off the ADC clock and powers down the converters when idle. A startup delay of MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-32...
- Page 513 PUDELAY values: a large value for full power-up and a smaller value for going from standby current levels to full power-up. The following paragraphs provide an explanation of how to use PUDELAY when starting the ADC up or changing modes. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-33 Freescale Semiconductor...
- Page 514 28.5.9 ADC Clock 28.5.9.1 General The ADC has two external clock inputs used to drive two clock domains within the ADC module. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-34...
- Page 515 The oscillator clock feeds an 80:1 divider, generating the auto standby clock. The auto standby clock is selected as the ADC clock during the auto standby power mode when both converters are idle. The auto MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-35 Freescale Semiconductor...
- Page 516 ADC Conversion Clock Resynchronized Asserted ADC Scans Start System Clock Old ADC Clock ADC Clock After Resynchronization ADCA Scan ADCB Scan Figure 28-26. ADC Clock Resynchronization for Sequential and Simultaneous Parallel Modes MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-36...
- Page 517 REFH DDA, the amplitude of V . It is imperative that special precautions be taken to assure the voltage applied to MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 28-37 Freescale Semiconductor...
- Page 518 Dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy. The power provided to these pins is suggested to come from a low noise filtered source. Uncoupling capacitors ought to be connected between V and V MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 28-38...
- Page 519 Period and Duty Counter Channel 2 PWMOUT2 Period and Duty Counter Channel 1 PWMOUT1 Period and Duty Counter Channel 0 PWMOUT0 Period and Duty Counter Figure 29-1. PWM Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-1...
- Page 520 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. A 32-bit access to any of these registers results in a bus transfer error. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-2...
- Page 521 If PWMCTL[CON23] is set, then this bit has no effect and PWMOUT2 is disabled. 0 PWM output disabled 1 PWM output enabled, if PWMCTL[CON23]=0 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-3 Freescale Semiconductor...
- Page 522 PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-4...
- Page 523 PWM signal is being generated, a truncated or stretched pulse can occur during the transition. IPSBAR 0x1B_0003 (PWMPRCLK) Access: Offset: SupervisorRead/Write PCKB PCKA Reset: Figure 29-5. PWM Prescale Clock Select Register (PWMPRCLK) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-5 Freescale Semiconductor...
- Page 524 PWM output modes. IPSBAR 0x1B_0004 (PWMCAE) Access: Offset: SupervisorRead/Write CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Reset: Figure 29-6. PWM Center Align Enable Register (PWMCAE) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-6...
- Page 525 1 Concatenate PWM 0 and 1. Channel 0 becomes the high order byte and channel 1 the low order byte. PWMOUT1 is the output for this 16-bit PWM signal, and PWMOUT0 is disabled. The channel 1 clock select, polarity, center align enable, and enable bits control this concatenated output. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-7 Freescale Semiconductor...
- Page 526 Figure 29-8. PWM Scale A Register (PWMSCLA) Table 29-8. PWMSCLA Field Descriptions Field Description 7–0 Part of divisor used to form Clock SA from Clock A. SCALEA SCALEA Value 0x00 0x01 0x02 0xFF MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-8...
- Page 527 The counter is also cleared at the end of the effective period (see Section 29.3.2.5, “Left-Aligned Outputs” Section 29.3.2.6, “Center-Aligned Outputs” for more details). When the channel is disabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-9 Freescale Semiconductor...
- Page 528 × × PWMn period Channel clock period PWMCAE CAEn PWMPERn Eqn. 29-3 For boundary case programming values (e.g. PWMPERn = 0x00), please refer to Section 29.3.2.8, “PWM Boundary Cases”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-10...
- Page 529 Cases”. IPSBAR 0x1B_001C (PWMDTY0) Access: Offset: 0x1B_001D (PWMDTY1) SupervisorRead/Write 0x1B_001E (PWMDTY2) 0x1B_001F (PWMDTY3) 0x1B_0020 (PWMDTY4) 0x1B_0021 (PWMDTY5) 0x1B_0022 (PWMDTY6) 0x1B_0023 (PWMDTY7) DUTY Reset: Figure 29-12. PWM Duty Registers (PWMDTYn) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-11 Freescale Semiconductor...
- Page 530 0 PWM outputs are forced to logic 0 1 PWM outputs are forced to logic 1 Reserved, must be cleared. PWM channel 7 input status. Reflects the current status of the PWMOUT7 pin. Read only. PWM7IN MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-12...
- Page 531 PWM channel has the capability of selecting one of two clocks, the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 29-14 shows the four different clocks and how the scaled clocks are created. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-13 Freescale Semiconductor...
- Page 532 Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-14...
- Page 533 The starting polarity of the output is also selectable on a per channel basis. Figure 29-15 shows a block diagram for a PWM timer. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-15 Freescale Semiconductor...
- Page 534 A change in duty or period can be forced into effect immediately by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-16...
- Page 535 When PWMCNTn register written to any When PWM channel is enabled When PWM channel is disabled value (PWMEn = 1). Counts from last value (PWMEn = 0) in PWMCNTn. Effective period ends MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-17 Freescale Semiconductor...
- Page 536 PWMn frequency = 40 MHz ÷ 4 = 10 MHz PWMn period = 100 ns ⎛ ⎞ × -- - PWMn Duty Cycle – 100% ⎝ ⎠ The output waveform generated is below: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-18...
- Page 537 Clock (A, B, SA, or SB) --------------------------------------------------------- - Eqn. 29-9 PWMn frequency × WMPERn The PWMn duty cycle (high time as a percentage of period) is expressed as: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-19 Freescale Semiconductor...
- Page 538 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-20...
- Page 539 PWMEn PPOLn PCLKn CAEn Output CON67 PWM7 PPOL7 PCLK7 CAE7 PWMOUT7 CON45 PWM5 PPOL5 PCLK5 CAE5 PWMOUT5 CON23 PWME3 PPOL3 PCLK3 CAE3 PWMOUT3 CON01 PWME1 PPOL1 PCLK1 CAE1 PWMOUT1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 29-21 Freescale Semiconductor...
- Page 540 (indicates no duty) 0x00 Always High (indicates no period) 0x00 Always Low (indicates no period) ≥ PWMPERn Always High ≥ PWMPERn Always Low Counter = 0x00 and does not count. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 29-22...
-
Page 541: Introduction
[0:15] • • • • • • • • Bus Interface Unit Clocks, Address and Data Buses, Interrupt and Test Signals Internal Bus Interface Figure 30-1. FlexCAN Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-1... - Page 542 FlexCAN caused by a defective CAN bus or defective stations. CAN Station 1 CAN Station 2 CAN Station n ColdFire Processor FlexCAN CANTX CANRX Transceiver CAN Bus Figure 30-3. Typical CAN System MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-2...
- Page 543 CAN bus, or until the FlexCAN enters the error passive or bus off state. After one of these conditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration, matching, move-in, and move-out. When this happens, the following events occur: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-3 Freescale Semiconductor...
- Page 544 In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Transmit and receive interrupts are generated. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-4...
-
Page 545: External Signal Description
Error and Status Register 0x0000_0000 30.3.6/30-13 (ERRSTAT) 0x1C_0028 Interrupt Mask Register (IMASK) 0x0000_0000 30.3.7/30-15 0x1C_0030 Interrupt Flag Register (IFLAG) 0x0000_0000 30.3.8/30-16 0x1C_0080 Message Buffers 0–15 (MB0–15) 2048 — 30.3.9/30-16 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-5 Freescale Semiconductor... - Page 546 Clearing this bit causes the FlexCAN to exit freeze mode. Refer to Section 30.1.3.2, “Freeze Mode,” more information. 0 FlexCAN ignores the BKPT signal and the CANMCR[HALT] bit. 1 FlexCAN module enabled to enter debug mode. Reserved, must be cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-6...
- Page 547 The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode. Note: Maximum MBs in Use = MAXMB + 1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-7 Freescale Semiconductor...
- Page 548 1–7. Eqn. 30-4 Phase buffer segment 2 (PSEG2 + 1) time quanta Bus off interrupt mask. BOFFMSK 0 Bus off interrupt disabled 1 Bus off interrupt enabled MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-8...
- Page 549 Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission. LBUF 0 Message buffer with lowest ID is transmitted first 1 Lowest numbered buffer is transmitted first MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-9 Freescale Semiconductor...
- Page 550 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30-6. FlexCAN Timer Register (TIMER) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-10...
- Page 551 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB14 Match for Extended Format (MB3). Match for Normal Format. (MB2). Mismatch for MB3 because of ID0. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-11 Freescale Semiconductor...
- Page 552 If the value of TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset to zero. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-12...
- Page 553 Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to Section 30.4.1, “Interrupts.” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-13 Freescale Semiconductor...
- Page 554 TXWRN 1 TXErrCounter ≥ 96 Receiver error status flag. Reflects the status of the FlexCAN receive error counter. 0 Receive error counter < 96 RXWRN 1 RxErrCounter ≥ 96 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-14...
- Page 555 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30-10. FlexCAN Interrupt Mask Register (IMASK) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-15 Freescale Semiconductor...
- Page 556 (0x1C_0000). The 256-byte message buffer space is fully used by the16 message buffer structures. Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-16...
- Page 557 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 30-13. Message Buffer Structure for Extended and Standard Frames MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-17 Freescale Semiconductor...
- Page 558 Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from 23–16, the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame. 15–8, 7–0 DATA MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-18...
- Page 559 MB automatically returns to the INACTIVE state. 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-19 Freescale Semiconductor...
- Page 560 The CPU prepares or changes an MB for transmission by writing the following: 1. Control/status word to hold Tx MB inactive (CODE = 1000) 2. ID word 3. Data bytes 4. Control/status word (active CODE, LENGTH) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-20...
- Page 561 30.3.13 Receive Process The CPU prepares or changes an MB for frame reception by writing the following: 1. Control/status word to hold Rx MB inactive (CODE = 0000) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-21 Freescale Semiconductor...
- Page 562 CAN bus. If the ID of the frame matches the ID of the FlexCAN MB, the frame is received by the FlexCAN. Such a frame is a self-received frame. FlexCAN MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-22...
- Page 563 MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration process, the data of that MB may no longer be coherent; therefore, that MB is deactivated. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-23 Freescale Semiconductor...
- Page 564 MB until the BUSY bit is cleared. If the BUSY bit is set or if the MB is empty, then reading the control and status word does not lock the MB. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-24...
- Page 565 For a message being transmitted, the TIMESTAMP entry is written into the transmit message buffer after the transmission has completed successfully. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-25 Freescale Semiconductor...
- Page 566 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-26...
- Page 567 5 .. 10 1 .. 2 4 .. 11 1 .. 3 5 .. 12 1 .. 4 6 .. 13 1 .. 4 7 .. 14 1 .. 4 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-27 Freescale Semiconductor...
-
Page 568: Initialization/Application Information
The control/status word of all message buffers must be written as an active or inactive message buffer b) All other entries in each message buffer should be initialized as required 3. Initialize RXGMASK, RX14MASK, and RX15MASK registers for acceptance mask as needed. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 30-28... - Page 569 (bus off and error) act in the same manner, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located in the CANCTRL register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 30-29 Freescale Semiconductor...
- Page 570 External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See Section 31.4.2, “Real-Time Debug Support”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-1...
- Page 571 Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-2 Freescale Semiconductor...
- Page 572 These registers are also accessed through the BDM port by the commands, WDMREG , described in Section 31.4.1.5, “BDM Command Set”. These commands contain a 5-bit field, RDMREG DRc, that specifies the register, as shown in Table 31-3. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-3...
- Page 573 The debug module revision A implementation provides a common hardware structure for BDM and breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown Table 31-4. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-4 Freescale Semiconductor...
- Page 574 0x00 using the WDEBUG instruction and through the BDM port using the RDMREG WDMREG commands. DRc[4:0]: 0x00 (CSR) Access: Supervisor write-only BDM read/write BSTAT TRG HALT BKPT Reset FDBG DBGH Reset Figure 31-2. Configuration/Status Register (CSR) MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-5...
- Page 575 Note: When PCD is set, do not execute a wddata instruction or perform any debug captures. Doing so, hangs the device. Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. Only commands from the external development system can modify IPW. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-6 Freescale Semiconductor...
- Page 576 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-7...
- Page 577 Transfer Type. See the TT definition in the AATR description, Section 31.3.4, “Address Attribute Trigger Register (AATR)”. 2–0 Transfer Modifier. See the TM definition in the AATR description, Section 31.3.4, “Address Attribute Trigger Register (AATR)”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-8 Freescale Semiconductor...
- Page 578 Read/Write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-9...
- Page 579 A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-10 Freescale Semiconductor...
- Page 580 Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-11...
- Page 581 Note: Debug Rev A only had the AND condition available for the triggers. Enable Level 1 Breakpoint. Global enable for the breakpoint trigger. L1EBL 0 Disables all level 1 breakpoints 1 Enables all level 1 breakpoint triggers MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-12 Freescale Semiconductor...
- Page 582 (PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-13...
- Page 583 1 PBR is enabled. Figure 31-8 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the command. PBMR only masks PBR0. WDMREG MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-14 Freescale Semiconductor...
- Page 584 ABLR. Table 31-13. ABHR Field Description Field Description 31–0 High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-15...
- Page 585 The DBR supports aligned and misaligned references. Table 31-16 shows relationships between processor address, access size, and location within the 32-bit data bus. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-16 Freescale Semiconductor...
- Page 586 When a pending condition is asserted, the processor halts execution at the next sample point. See Section 31.4.2.1, “Theory of Operation”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-17...
- Page 587 17-bit packets composed of a status/control bit and a 16-bit data word. As shown Figure 31-12, all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is high; DSI is sampled and DSO is driven. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-18 Freescale Semiconductor...
- Page 588 Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 31.4.1.3 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit Data Figure 31-13. Receive BDM Packet MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-19...
- Page 589 All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words. Operation Op Size Register Extension Word(s) Figure 31-15. BDM Command Format MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-20 Freescale Semiconductor...
- Page 590 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-21...
- Page 591 If a bus error terminates a memory or register access, error status (S = 1, DATA = 0x0001) returns instead of result data. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-22 Freescale Semiconductor...
- Page 592 - Halted: The CPU must be halted to perform this command. - Steal: Command generates bus cycles that can be interleaved with bus accesses. - Parallel: Command is executed in parallel with CPU activity. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-23...
- Page 593 The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-24 Freescale Semiconductor...
- Page 594 Command/Result Formats: Byte Command A[31:16] A[15:0] Result D[7:0] Word Command A[31:16] A[15:0] Result D[15:0] Longword Command A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 31-21. Command/Result Formats READ MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-25...
- Page 595 Write data to the memory location specified by the longword address. BAAR[TT,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-26 Freescale Semiconductor...
- Page 596 Debug Module Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 31-23. Command Format WRITE MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-27...
- Page 597 The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the current DUMP operand size, and store the updated address in the temporary register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-28 Freescale Semiconductor...
- Page 598 ’NOT READY’ LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD ’ILLEGAL’ ’NOT READY’ BERR ’NOT READY’ Figure 31-26. Command Sequence DUMP Operand Data: None MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-29...
- Page 599 The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 31-27. Command Format FILL MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-30 Freescale Semiconductor...
- Page 600 BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Figure 31-29. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’ Figure 31-30. Command Sequence MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-31...
- Page 601 PC for performance monitoring. The SYNC execution of this command is considerably less obtrusive to the real-time operation of an application than command sequence. HALT READ RESUME Command Formats: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-32 Freescale Semiconductor...
- Page 602 NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Figure 31-36. Command Sequence RCREG Operand Data: The only operand is the 32-bit Rc control register select field. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-33...
- Page 603 A7 and OTHER_A7 to the two program-visible definitions (supervisor and user stack pointers), based on the SR[S] bit. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-34 Freescale Semiconductor...
- Page 604 See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 31-37. Command/Result Formats WCREG Command Sequence: MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-35...
- Page 605 Result D[31:16] D[15:0] Figure 31-39. Command/Result Formats RDMREG Table 31-22 shows the definition of DRc encoding. Table 31-22. Definition of DRc Encoding—Read DRc[5:0] Debug Register Definition Mnemonic 0x00 Configuration/Status MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-36 Freescale Semiconductor...
- Page 606 Longword data is written into the specified debug register. The data is supplied most-significant word first. Result Data: Command complete status (0xFFFF) is returned when register write is complete. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-37...
- Page 607 If the processor core cannot be halted, the debug interrupt can be used. With this configuration, TDR[TRC] equals 10, breakpoint trigger becomes a debug interrupt to the processor, which is treated MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-38 Freescale Semiconductor...
- Page 608 TT equals 0x2, TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that forced entry into this mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-39...
- Page 609 This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-40 Freescale Semiconductor...
- Page 610 PST port one PSTCLK cycle before the data is displayed on DDATA. 0x8 Begin 1-byte transfer on DDATA. 0x9 Begin 2-byte transfer on DDATA. 0xA Begin 3-byte transfer on DDATA. 0xB Begin 4-byte transfer on DDATA. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-41...
- Page 611 Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 31-43 shows the PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to display the lower 2 bytes of an address. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-42 Freescale Semiconductor...
- Page 612 PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} adda.l <ea>y,Ax PST = 0x1, {PST = 0xB, DD = source operand} addi.l #<data>,Dx PST = 0x1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-43...
- Page 613 PST = 0x1, {PST = 0x9, DD = source operand} eor.l Dy,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} eori.l #<data>,Dx PST = 0x1 ext.l PST = 0x1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-44 Freescale Semiconductor...
- Page 614 PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} ori.l #<data>,Dx PST = 0x1 pea.l <ea>y PST = 0x1, {PST = 0xB, DD = destination operand} pulse PST = 0x4 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-45...
- Page 615 PST = 0x4, {PST = 0x8, DD = source operand} wddata.l <ea>y PST = 0x4, {PST = 0xB, DD = source operand} wddata.w <ea>y PST = 0x4, {PST = 0x9, DD = source operand} MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-46 Freescale Semiconductor...
- Page 616 {Ry,#<data>},ACCext23 PST = 0x1 move.l ACCext01,Rx PST = 0x1 move.l ACCext23,Rx PST = 0x1 move.l ACCy,ACCx PST = 0x1 move.l ACCy,Rx PST = 0x1 move.l MACSR,CCR PST = 0x1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-47...
- Page 617 Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xFF) display this status throughout the entire time the ColdFire processor is in the given mode. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 31-48 Freescale Semiconductor...
- Page 618 EVDD PST3 PST2 PST1 PST0 DDATA3 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK IVDD Pins reserved for BDM developer use. Supplied by target Figure 31-44. Recommended BDM Connector MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 31-49...
- Page 619 4-bit TAP Instruction Decoder 4-bit TAP Instruction Register JTAG_EN TCLK Disable DSCLK TMS/BKPT Force BKPT = 1 TRST/DSCLK JTAG Module to Debug Module BKPT DSCLK Figure 32-1. JTAG Block Diagram MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-1...
- Page 620 The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is selected; if it is high, the JTAG is selected. Table 32-2 summarizes the pin function selected depending on JTAG_EN logic state. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-2...
- Page 621 (lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 32-3 Freescale Semiconductor...
- Page 622 0 0 0 0 0 0 0 1 1 1 0 1 The reset values for PRN and PIN are device-dependent. Varies, depending on design center location. Figure 32-2. IDCODE Register MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-4...
- Page 623 The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG signals, analog signals, power supplies, compliance enable pins, and clock signals. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 32-5 Freescale Semiconductor...
- Page 624 TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-6...
- Page 625 Selects boundary scan register while applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 32-7 Freescale Semiconductor...
- Page 626 The update-DR state and the falling edge of TCLK can then transfer this data to the update cells. The data is applied to the external output pins by the EXTEST or CLAMP instruction. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-8...
- Page 627 After the lockout recovery sequence has completed, the user must reset the JTAG TAP controller and the MCU to return to normal operation. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 32-9 Freescale Semiconductor...
- Page 628 However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor 32-10...
- Page 629 MAC Accumulator 0 ACC0 CPU @ 0x80E Status Register CPU @ 0x80F Program Counter CPU @ 0xC04 Flash Base Address Register FLASHBAR CPU @ 0xC05 RAM Base Address Register RAMBAR MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 630 Reset Controller, Chip Configuration, and Power Management IPSBAR + 0x12_0000 Clock Module IPSBAR + 0x13_0000 Edge Port 0 IPSBAR + 0x14_0000 Edge Port 1 IPSBAR + 0x15_0000 Programmable Interval Timer 0 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 631 Peripheral Access Control Register 1 PACR1 IPSBAR + 0x0026 Peripheral Access Control Register 2 PACR2 IPSBAR + 0x0027 Peripheral Access Control Register 3 PACR3 IPSBAR + 0x0028 Peripheral Access Control Register 4 PACR4 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 632 (Write) UART Clock Select Register 0 UCSR0 IPSBAR + 0x0208 (Read) Reserved (Write) UART Command Register 0 UCR0 IPSBAR + 0x020C (Read) UART Receive Buffer 0 URB0 (Write) UART Transmit Buffer 0 UTB0 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 633 UART Baud Rate Generator Register 11 UBG11 IPSBAR + 0x025C (Read) Reserved UART Baud Rate Generator Register 21 UBG21 IPSBAR + 0x0274 (Read) UART Input Port Register 1 UIP1 (Write) Reserved MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 634 IPSBAR + 0x0304 C Frequency Divider Register I2FDR IPSBAR + 0x0308 C Control Register I2CR IPSBAR + 0x030C C Status Register I2SR IPSBAR + 0x0310 C Data I/O Register I2DR QSPI Registers MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 635 DMA Timer Capture Register 1 DTCR1 IPSBAR + 0x044C DMA Timer Counter Register 1 DTCN1 IPSBAR + 0x0480 DMA Timer Mode Register 2 DTMR2 IPSBAR + 0x0482 DMA Timer Extended Mode Register 2 DTXMR2 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 636 IPSBAR + 0x0C4A Interrupt Control Register 0-10 ICR010 IPSBAR + 0x0C4B Interrupt Control Register 0-11 ICR011 IPSBAR + 0x0C4C Interrupt Control Register 0-12 ICR012 IPSBAR + 0x0C4D Interrupt Control Register 0-13 ICR013 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 637 IPSBAR + 0x0C6B Interrupt Control Register 0-43 ICR043 IPSBAR + 0x0C6C Interrupt Control Register 0-44 ICR044 IPSBAR + 0x0C6D Interrupt Control Register 0-45 ICR045 IPSBAR + 0x0C6E Interrupt Control Register 0-46 ICR046 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 638 Interrupt Mask Register Low 1 IMRL1 IPSBAR + 0x0D10 Interrupt Force Register High 1 INTFRCH1 IPSBAR + 0x0D14 Interrupt Force Register Low 1 INTFRCL1 IPSBAR + 0x0D18 Interrupt Request Level Register 1 IRLR1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-10...
- Page 639 Interrupt Control Register 1-29 ICR129 IPSBAR + 0x0D5E Interrupt Control Register 1-30 ICR130 IPSBAR + 0x0D5F Interrupt Control Register 1-31 ICR131 IPSBAR + 0x0D61 Interrupt Control Register 1-32 ICR132 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-11 Freescale Semiconductor...
- Page 640 IPSBAR + 0x0DE0 Software Interrupt Acknowledge Register 1 SWACKR1 IPSBAR + 0x0DE4 Level 1 Interrupt Acknowledge Register 1 L1IACKR1 IPSBAR + 0x0DE8 Level 2 Interrupt Acknowledge Register 1 L2IACKR1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-12...
- Page 641 Descriptor Individual Lower Address Register IALR IPSBAR + 0x1120 Descriptor Group Upper Address Register GAUR IPSBAR + 0x1124 Descriptor Group Lower Address Register GALR IPSBAR + 0x1144 Transmit FIFO Watermark TFWR MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-13 Freescale Semiconductor...
- Page 642 Port LD Output Data Register PORTLD IPSBAR + 0x10_0016 Port GP Output Data Register PORTGP IPSBAR + 0x10_0017 Reserved — IPSBAR + 0x10_0018 Reserved — IPSBAR + 0x10_0019 Reserved — MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-14...
- Page 643 IPSBAR + 0x10_0037 Reserved — IPSBAR + 0x10_0038 Port NQ Pin Data/Set Data Register SETNQ IPSBAR + 0x10_0039 Reserved — IPSBAR + 0x10_003A Port AN Pin Data/Set Data Register SETAN MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-15 Freescale Semiconductor...
- Page 644 IPSBAR + 0x10_0059 Port UA Clear Output Data Register CLRUA IPSBAR + 0x10_005A Port UB Clear Output Data Register CLRUB IPSBAR + 0x10_005B Port UC Clear Output Data Register CLRUC MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-16...
- Page 645 IPSBAR + 0x10_007C Port Drive Strength Register 0 PDSR0 Reset Control, Chip Configuration, and Power Management Registers IPSBAR + 0x11_0000 Reset Control Register IPSBAR + 0x11_0001 Reset Status Register MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-17 Freescale Semiconductor...
- Page 646 IPSBAR + 0x16_0000 PIT Control and Status Register 1 PCSR 1 IPSBAR + 0x16_0002 PIT Modulus Register 1 PMR 1 IPSBAR + 0x16_0004 PIT Count Register 1 PCNTR 1 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-18...
- Page 647 GPTA Interrupt Enable Register GPTAIE IPSBAR + 0x1A_000D GPTA System Control Register 2 GPTASCR2 IPSBAR + 0x1A_000E GPTA Flag Register 1 GPTAFLG1 IPSBAR + 0x1A_000F GPTA Flag Register 2 GPTAFLG2 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-19 Freescale Semiconductor...
- Page 648 PWM Channel Period Register 2 PWMPER2 IPSBAR + 0x1B_0017 PWM Channel Period Register 3 PWMPER3 IPSBAR + 0x1B_0018 PWM Channel Period Register 4 PWMPER4 IPSBAR + 0x1B_0019 PWM Channel Period Register 5 PWMPER5 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-20...
- Page 649 IPSBAR + 0x1E_0000 Ethernet Physical Transceiver Control Register 0 EPHYCTL0 IPSBAR + 0x1E_0001 Ethernet Physical Transceiver Control Register 1 EPHYCTL1 IPSBAR + 0x1E_0002 Ethernet Physical Transceiver Status Register EPHYSR MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 A-21 Freescale Semiconductor...
- Page 650 UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor A-22...
- Page 651 PLL clock. Section 7.8.3 / Page 7-12 Deleted the sentence “The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 652 “This type of halt is always first marked as pending in the pocessor, which samples for pending halt and interrupt conditions once per instruction”.) Appendix A • Corrected PACRn addresses. • Deleted the entry for the (nonexistent) GSWIACK register. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 653 Section 18.5.4.6 / Page 18-27 Added the following text to the MMFR description: “Before accessing the MII registers via the MMFR, the software must poll EIR[MII] to make sure that an access is not currently in progress.” MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 654 Figure 31-8 / Page 31-16 Changed the address of PBR3 (was 0x1C, is 0x1B). Table 31-22 / Page 31-39 Changed the initial state of the CSR (was 0x0, is 0x0090_0000). MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 655 Figure 16-3 / Page 16-4 Replaced register figure with correct 8-bit version. Section 17.3.2 / Page 17-4 Deleted erroneous reference to external boot mode. Table 18-11 / Page 18-19 Added RMON_R_DROP counter. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 656 • Corrected missing and incomplete sentences. • Updated block diagram to include correct peripheral signal names. • Revised package information. Section 1.4.3 / Page 1-10 Corrected second sentence to read “... a 256-bit boundary-scan register...”. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 657 Figure 15-2 / Page 15-6 • Changed register name from IPSBMT to IPRLn. • Changed field label from INT[16:1] to INT[15:1]. Figure 15-4 / Page 15-8 Changed field label from INT_MASK[16:1] to INT_MASK[15:1]. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 658 Section 26.4.1.2.1 / Page • Changed numerator in Equation 26-1 from f to f sys/2 26-19 • Changed values in Equation 26.2 to reflect a 60-MHz clock. Chapter 28 Deleted superfluous Table 28-5. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 659 Table 11-2 / Page 11-3 Filled in table in PRIU/PRIL field description. Figure 14-1 / Page 14-2 Added FEC signals and arranged signals in same order as in Table 2-1. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor...
- Page 660 Section 27.6.1 / Page 27-12 Added missing line of code to note: I2CR = 0x80 ; re-enable Section 27.6.2 / Page 27-13 Replaced instances of MBB with IBB. Section 29.2 Replaced “Address” with “IPSBAR Offset” in the register figures. MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6 Freescale Semiconductor B-10...
Need help?
Do you have a question about the MCF52230 ColdFire and is the answer not in the manual?
Questions and answers