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Freescale Semiconductor MC9S08JS16L Reference Manual

Freescale Semiconductor MC9S08JS16L Reference Manual (306 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 4 MB

Table of Contents

Table of Contents
7
Chapter 1 Device Overview
17
- Introduction
  17
- MCU Block Diagram
  18
- System Clock Distribution
  19
Chapter 2 Pins and Connections
21
- Pins and Connections
  21
- Introduction
  21
- Device Pin Assignment
  21
- Recommended System Connections
  22
- Power
  24
- Oscillator (XTAL, EXTAL)
  24
- Ssosc , V Usb33 )
  24
- RESET Pin
  24
- Background/Mode Select (BKGD/MS)
  25
- Bootloader Mode Select (BLMS)
  26
- USB Data Pins (USBDP, USBDN)
  26
- General-Purpose I/O and Peripheral Ports
  26
Chapter 3 Modes of Operation
29
- Introduction
  29
- Features
  29
- Run Mode
  29
- Active Background Mode
  29
- Wait Mode
  30
- Stop Modes
  31
- Stop3 Mode
  31
- Stop2 Mode
  32
- On-Chip Peripheral Modules in Stop Modes
  33
Chapter 4 Memory
35
- Memory 4.1 MC9S08JS16 Series Memory Map
  35
- Reset and Interrupt Vector Assignments
  36
- Register Addresses and Bit Assignments
  37
- RAM (System RAM)
  43
- Usb Ram
  44
- Bootloader ROM
  44
- External Signal Description
  44
- Modes of Operation
  45
- Flash Memory Map
  46
- Bootloader Operation
  47
- Flash Memory
  50
- Features
  50
- Program and Erase Time
  50
- Program and Erase Command Execution
  51
- Burst Program Execution
  52
- Access Errors
  54
- Flash Block Protection
  54
- Flash Block Protection Disabled
  55
- Vector Redirection
  55
- Security
  55
- Flash Registers and Control Bits
  57
- Flash Clock Divider Register (FCDIV)
  57
- Flash Options Register (FOPT and NVOPT)
  58
- Flash Configuration Register (FCNFG)
  59
- Flash Protection Register (FPROT and NVPROT)
  59
- Flash Status Register (FSTAT)
  60
- Flash Command Register (FCMD)
  61
Chapter 5 Resets, Interrupts, and System Configuration
63
Chapter 6 Parallel Input/Output
79
Chapter 7 Central Processor Unit (S08CPUV2)
87
- Central Processor Unit (S08CPUV2)
  87
- Introduction
  87
- Features
  87
- Programmer's Model and CPU Registers
  88
- Accumulator (A)
  88
- Index Register (H:X)
  88
- Stack Pointer (SP)
  89
- Program Counter (PC)
  89
- Condition Code Register (CCR)
  89
- Addressing Modes
  91
- Inherent Addressing Mode (INH)
  91
- Relative Addressing Mode (REL)
  91
- Immediate Addressing Mode (IMM)
  91
- Direct Addressing Mode (DIR)
  91
- Extended Addressing Mode (EXT)
  92
- Indexed Addressing Mode
  92
- Special Operations
  93
- Reset Sequence
  93
- Interrupt Sequence
  93
- Wait Mode Operation
  94
- Stop Mode Operation
  94
- BGND Instruction
  95
- HCS08 Instruction Set Summary
  96
Chapter 8 Keyboard Interrupt (S08KBIV2)
107
- Keyboard Interrupt (S08KBIV2)
  107
- Introduction
  107
- Features
  109
- Modes of Operation
  109
- Block Diagram
  109
- External Signal Description
  110
- Register Definition
  110
- KBI Status and Control Register (KBISC)
  110
- KBI Pin Enable Register (KBIPE)
  111
- KBI Edge Select Register (KBIES)
  111
- Functional Description
  112
- Edge Only Sensitivity
  112
- Edge and Level Sensitivity
  112
- KBI Pullup/Pulldown Resistors
  113
- KBI Initialization
  113
Chapter 9 Multi-Purpose Clock Generator (S08MCGV1)
115
- Multi-Purpose Clock Generator (S08MCGV1)
  115
- Introduction
  115
- Features
  117
- Modes of Operation
  119
- External Signal Description
  119
- Register Definition
  120
- MCG Control Register 1 (MCGC1)
  120
- MCG Control Register 2 (MCGC2)
  121
- MCG Trim Register (MCGTRM)
  122
- MCG Status and Control Register (MCGSC)
  123
- MCG Control Register 3 (MCGC3)
  124
- Functional Description
  126
- Operational Modes
  126
- Mode Switching
  130
- Bus Frequency Divider
  131
- Low Power Bit Usage
  131
- Internal Reference Clock
  131
- External Reference Clock
  131
- Fixed Frequency Clock
  132
- Initialization / Application Information
  132
- MCG Module Initialization Sequence
  132
- MCG Mode Switching
  133
- Calibrating the Internal Reference Clock (IRC)
  144
Chapter 10 Modulo Timer (S08MTIMV1)
147
- Modulo Timer (S08MTIMV1)
  147
- Introduction
  147
- MTIM Configuration Information
  147
- Features
  149
- Modes of Operation
  149
- Block Diagram
  150
- External Signal Description
  150
- Register Definition
  150
- MTIM Status and Control Register (MTIMSC)
  152
- MTIM Clock Configuration Register (MTIMCLK)
  153
- MTIM Counter Register (MTIMCNT)
  154
- MTIM Modulo Register (MTIMMOD)
  154
- Functional Description
  155
- MTIM Operation Example
  156
Chapter 11 Real-Time Counter (S08RTCV1)
157
- Real-Time Counter (S08RTCV1)
  157
- Introduction
  157
- Features
  159
- Modes of Operation
  159
- Block Diagram
  160
- External Signal Description
  160
- Register Definition
  160
- RTC Status and Control Register (RTCSC)
  161
- RTC Counter Register (RTCCNT)
  162
- RTC Modulo Register (RTCMOD)
  162
- Functional Description
  162
- RTC Operation Example
  163
- Initialization/Application Information
  164
Chapter 12 Serial Communications Interface (S08SCIV4)
167
- Serial Communications Interface (S08SCIV4)
  167
- Introduction
  167
- Features
  169
- Modes of Operation
  169
- Block Diagram
  169
- Register Definition
  172
- SCI Baud Rate Registers (SCIBDH, SCIBDL)
  172
- SCI Control Register 1 (SCIC1)
  173
- SCI Control Register 2 (SCIC2)
  174
- SCI Status Register 1 (SCIS1)
  175
- SCI Status Register 2 (SCIS2)
  177
- SCI Control Register 3 (SCIC3)
  178
- SCI Data Register (SCID)
  179
- Functional Description
  179
- Baud Rate Generation
  179
- Transmitter Functional Description
  180
- Receiver Functional Description
  181
- Interrupts and Status Flags
  183
- Additional SCI Functions
  184
Chapter 13 16-Bit Serial Peripheral Interface (S08SPI16V1)
187
- 16-Bit Serial Peripheral Interface (S08SPI16V1)
  187
- Introduction
  187
- SPI Port Configuration Information
  187
- Features
  190
- Modes of Operation
  190
- Block Diagrams
  190
- External Signal Description
  192
- SPSCK - SPI Serial Clock
  193
- MOSI - Master Data Out, Slave Data in
  193
- MISO - Master Data In, Slave Data out
  193
- SS - Slave Select
  193
- Register Definition
  193
- SPI Control Register 1 (SPIC1)
  193
- SPI Control Register 2 (SPIC2)
  195
- SPI Baud Rate Register (SPIBR)
  196
- SPI Status Register (SPIS)
  197
- SPI Data Registers (SPIDH:SPIDL)
  198
- SPI Match Registers (SPIMH:SPIML)
  199
- Functional Description
  199
- General
  199
- Master Mode
  200
- Slave Mode
  201
- Data Transmission Length
  202
- SPI Clock Formats
  203
- SPI Baud Rate Generation
  205
- Special Features
  205
- Error Conditions
  207
- Low Power Mode Options
  207
- 10SPI Interrupts
  209
- Initialization/Application Information
  210
- SPI Module Initialization Example
  210
Chapter 14 Timer/Pulse-Width Modulator (S08TPMV3)
215
- Timer/Pulse-Width Modulator (S08TPMV3)
  215
- Introduction
  215
- Features
  215
- TPMV3 Differences from Previous Versions
  217
- Migrating from TPMV1
  219
- Features
  220
- Modes of Operation
  220
- Block Diagram
  221
- Signal Description
  223
- Detailed Signal Descriptions
  223
- Register Definition
  227
- TPM Status and Control Register (TPMSC)
  227
- TPM-Counter Registers (TPMCNTH:TPMCNTL)
  228
- TPM Counter Modulo Registers (TPMMODH:TPMMODL)
  229
- TPM Channel N Status and Control Register (Tpmcnsc)
  230
- TPM Channel Value Registers (Tpmcnvh:tpmcnvl)
  231
- Functional Description
  233
- Counter
  233
- Channel Mode Selection
  235
- Reset Overview
  238
- General
  238
- Description of Reset Operation
  238
- Interrupts
  238
- Description of Interrupt Operation
  239
Chapter 15 Universal Serial Bus Device Controller (S08USBV1)
243
- Universal Serial Bus Device Controller (S08USBV1)
  243
- Introduction
  243
- Clocking Requirements
  243
- Current Consumption in USB Suspend
  243
- Regulator
  243
- Features
  246
- Modes of Operation
  246
- Block Diagram
  247
- External Signal Description
  248
- Usbdp
  248
- Usbdn
  248
- Vusb33
  248
- Register Definition
  248
- USB Control Register 0 (USBCTL0)
  249
- Peripheral ID Register (PERID)
  249
- Peripheral ID Complement Register (IDCOMP)
  250
- Peripheral Revision Register (REV)
  250
- Interrupt Status Register (INTSTAT)
  251
- Interrupt Enable Register (INTENB)
  252
- Error Interrupt Status Register (ERRSTAT)
  253
- Error Interrupt Enable Register (ERRENB)
  254
- Status Register (STAT)
  255
- 10Control Register (CTL)
  256
- 11Address Register (ADDR)
  257
- 12Frame Number Register (FRMNUML, FRMNUMH)
  257
- 13Endpoint Control Register (Epctln, N=0-6)
  258
- Functional Description
  259
- Block Descriptions
  259
- Buffer Descriptor Table (BDT)
  264
- USB Transactions
  267
- USB Packet Processing
  269
- Start of Frame Processing
  270
- Suspend/Resume
  271
- Resets
  272
- Interrupts
  273
Chapter 16 Cyclic Redundancy Check Generator (S08CRCV2)
275
- Cyclic Redundancy Check Generator (S08CRCV2)
  275
- Introduction
  275
- Features
  277
- Modes of Operation
  277
- Block Diagram
  278
- External Signal Description
  278
- Register Definition
  278
- Memory Map
  278
- Register Descriptions
  279
- Functional Description
  280
- ITU-T (CCITT) Recommendations & Expected CRC Results
  280
- Initialization Information
  281
Chapter 17 Development Support
283
- Development Support
  283
- Introduction
  283
- Features
  284
- Background Debug Controller (BDC)
  284
- BKGD Pin Description
  285
- Communication Details
  286
- BDC Commands
  289
- BDC Hardware Breakpoint
  292
- On-Chip Debug System (DBG)
  293
- Comparators a and B
  293
- Bus Capture Information and FIFO Operation
  293
- Change-Of-Flow Information
  294
- Tag Vs. Force Breakpoints and Triggers
  294
- Trigger Modes
  295
- Hardware Breakpoints
  297
- Register Definition
  297
- BDC Registers and Control Bits
  297
- System Background Debug Force Reset Register (SBDFR)
  299
- DBG Registers and Control Bits
  300

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