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Freescale Semiconductor MC68332 User Manual

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  • Page 1 Distributed by: www.Jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Jameco Part Number 961012UsersManual...
  • Page 2 Freescale Semiconductor M68300 Family MC68332 User’s Manual © MOTOROLA, INC. 1995 © Freescale Semiconductor, Inc., 2004. All rights reserved. For More Information On This Product, Go to: www.freescale.com...
  • Page 3 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...

  • Page 4: Table Of Contents

    Symbols and Operators .................. 2-1 CPU32 Registers .................... 2-2 Pin and Signal Mnemonics ................2-3 Register Mnemonics ..................2-4 Conventions ....................2-5 SECTION 3OVERVIEW MC68332 Features ..................3-1 3.1.1 System Integration Module (SIM) ............3-1 3.1.2 Central Processing Unit (CPU) ............... 3-1 3.1.3 Time Processor Unit (TPU) ..............
  • Page 5 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 4.2.10 Software Watchdog ................4-5 4.2.11 Periodic Interrupt Timer ................4-7 4.2.12 Low-Power Stop Operation ..............4-8 4.2.13 Freeze Operation ................... 4-9 System Clock ....................4-9 4.3.1 Clock Sources ..................4-10 4.3.2...
  • Page 6 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 4.5.6 External Bus Arbitration ................ 4-35 4.5.6.1 Slave (Factory Test) Mode Arbitration ......... 4-36 4.5.6.2 Show Cycles ................4-36 Reset ......................4-37 4.6.1 Reset Exception Processing ..............4-37 4.6.2 Reset Control Logic ................4-38 4.6.3...
  • Page 7 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page CPU32 Registers .................... 5-2 5.2.1 Data Registers ..................5-3 5.2.2 Address Registers .................. 5-5 5.2.3 Program Counter ..................5-5 5.2.4 Control Registers ..................5-5 5.2.4.1 Status Register ................5-5 5.2.4.2 Alternate Function Code Registers ..........
  • Page 8 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 6.2.1.1 Low-Power Stop Operation ............6-2 6.2.1.2 Freeze Operation ................6-3 6.2.1.3 QSM Interrupts ................6-3 6.2.2 QSM Pin Control Registers ..............6-3 Queued Serial Peripheral Interface ..............6-4 6.3.1 QSPI Registers ..................
  • Page 9 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 7.2.1 Time Bases .................... 7-2 7.2.2 Timer Channels ..................7-2 7.2.3 Scheduler ....................7-2 7.2.4 Microengine .................... 7-2 7.2.5 Host Interface ..................7-2 7.2.6 Parameter RAM ..................7-3 TPU Operation ....................7-3 7.3.1...
  • Page 10 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 7.6.1.3 Emulation Control ................. 7-13 7.6.1.4 Low-Power Stop Control .............. 7-13 7.6.2 Channel Control Registers ..............7-14 7.6.2.1 Channel Interrupt Enable and Status Registers ......7-14 7.6.2.2 Channel Function Select Registers ..........7-14 7.6.2.3...
  • Page 11 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page D.2.7 DDRE — Port E Data Direction Register ....... $YFFA15 D-8 D.2.8 PEPAR — Port E Pin Assignment Register ......$YFFA17 D-8 D.2.9 PORTF0/PORTF1 — Port F Data Register...$YFFA19, $YFFA1B D-9 D.2.10...
  • Page 12 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page D.4.11 SPCR1 — QSPI Control Register 1 ........$YFFC1A D-26 D.4.12 SPCR2 — QSPI Control Register 2 ........$YFFC1C D-27 D.4.13 SPCR3 — QSPI Control Register 3 ..........$YFFC1E SPSR — QSPI Status Register $YFFC1F ..............D-27 D.4.14...
  • Page 13 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page MC68332 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 14 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Title Page MCU Block Diagram ..................3-3 Pin Assignments for 132-Pin Package ............3-4 Pin Assignments for 144-Pin Package ............3-5 Internal Register Memory Map ..............3-10 Overall Memory Map ..................3-11 Separate Supervisor and User Space Map ..........3-12 Supervisor Space (Separate Program/Data Space) Map ......
  • Page 15 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Title Page QSPI RAM ...................... 6-8 Flowchart of QSPI Initialization Operation ............ 6-11 Flowchart of QSPI Master Operation (Part 1) ..........6-12 Flowchart of QSPI Master Operation (Part 2) ..........6-13 Flowchart of QSPI Master Operation (Part 3) ..........6-14 Flowchart of QSPI Slave Operation (Part 1) ..........
  • Page 16 Freescale Semiconductor, Inc. LIST OF TABLES Table Title Page MCU Driver Types................... 3-6 MCU Pin Characteristics ................. 3-6 MCU Power Connections ................3-7 MCU Signal Characteristics ................3-7 MCU Signal Function ..................3-8 SIM Reset Mode Selection................3-15 Module Pin Functions..................3-16 Show Cycle Enable Bits ..................
  • Page 17 SIM Address Map....................D-4 TPURAM Address Map .................D-16 QSM Address Map ..................D-18 TPU Address Map ..................D-30 Parameter RAM Address Map ..............D-37 MC68332 Module Address Map..............D-38 Register Bit and Field Mnemonics..............D-41 MC68332 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 18: Section 1 Introduction

    Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applica- tions.
  • Page 19 Freescale Semiconductor, Inc. MC68332 INTRODUCTION USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 20: Section 2Nomenclature

    Freescale Semiconductor, Inc. SECTION 2 NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 Symbols and Operators + — Addition - — Subtraction or negation (two's complement) * —...

  • Page 21: Cpu32 Registers

    Freescale Semiconductor, Inc. 2.2 CPU32 Registers A6–A0 — Address registers (Index registers) A7 (SSP) — Supervisor Stack Pointer A7 (USP) — User Stack Pointer CCR — Condition code register (user portion of SR) D7–D0 — Data Registers (Index registers) DFC — Alternate function code register PC —...

  • Page 22: Pin And Signal Mnemonics

    Freescale Semiconductor, Inc. 2.3 Pin and Signal Mnemonics ADDR[23:0] — Address Bus AS — Address Strobe AVEC — Autovector BERR — Bus Error BG — Bus Grant BGACK — Bus Grant Acknowledge BKPT — Breakpoint BR — Bus Request CLKOUT — System Clock CS[10:0] —...

  • Page 23: Register Mnemonics

    Freescale Semiconductor, Inc. 2.4 Register Mnemonics CFSR[0:3] — Channel Function Select Registers [0:3] CIER — Channel Interrupt Enable Register CISR — Channel Interrupt Status Register CPR[0:1] — Channel Priority Registers [0:1] CREG — Test Control Register C CR[0:F] — QSM Command RAM CSBARBT —...

  • Page 24: Conventions

    Freescale Semiconductor, Inc. SWSR — Software Watchdog Service Register SYNCR — Clock Synthesizer Control Register SYPCR — System Protection Control Register TCR — TPU Test Configuration Register TICR — TPU Interrupt Configuration Register TPUMCR — TPU Module Configuration Register TRAMBAR — TPURAM Base Address/Status Register TRAMMCR —...
  • Page 25 Freescale Semiconductor, Inc. MC68332 NOMENCLATURE USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 26: Section 3Overview

    TICS . Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY . 3.1 MC68332 Features The following paragraphs highlight capabilities of each of the microcontroller modules. Each module is discussed separately in a subsequent section of this user's manual.

  • Page 27: Queued Serial Module (Qsm)

    Freescale Semiconductor, Inc. 3.1.4 Queued Serial Module (QSM) • Enhanced Serial Communication Interface (SCI), Universal Asynchronous Re- ceiver Transmitter (UART): Modulus Baud Rate, Parity • Queued Serial Peripheral Interface (SPI): 80-Byte RAM, Up to 16 Automatic Transfers • Dual Function I/O Ports •...
  • Page 28 Freescale Semiconductor, Inc. STBY CHIP CSBOOT SELECTS ADDR23/CS10 PC6/ADDR22/CS9 BGACK PC5/ADDR21/CS8 CS[10:0] PC4/ADDR20/CS7 PC3/ADDR19/CS6 TPUCH[15:0] TPUCH[15:0] PC2/FC2/CS5 PC1/FC1/CS4 T2CLK T2CLK PC0/FC0/CS3 2 KBYTES BGACK/CS2 BG/CS1 BR/CS0 ADDR[23:0] ADDR[18:0] SIZ1 PE7/SIZ1 SIZ0 PE6/SIZ0 PE5/DS PE4/AS PE3/RMC AVEC PE2/AVEC DSACK1 PE1/DSACK1 DSACK0...
  • Page 29 Freescale Semiconductor, Inc. BGACK/CS2 STBY ADDR1 BG/CS1 ADDR2 BR/CS0 ADDR3 CSBOOT ADDR4 DATA0 ADDR5 DATA1 ADDR6 DATA2 ADDR7 DATA3 ADDR8 DATA4 ADDR9 DATA5 ADDR10 DATA6 ADDR11 DATA7 ADDR12 MC68332 DATA8 ADDR13 DATA9 ADDR14 DATA10 ADDR15 DATA11 ADDR16 DATA12 ADDR17 DATA13...

  • Page 30: Pin Descriptions

    Freescale Semiconductor, Inc. FC0/CS3 PE4/AS FC1/CS4 PE6/SIZ0 FC2/CS5 PE7/SIZ1 ADDR19/CS6 ADDR20/CS7 PF0/MODCLK ADDR21/CS8 PF1/IRQ1 ADDR22/CS9 PF2/IRQ2 ADDR23/CS10 PF3/IRQ3 PF4/IRQ4 PF5/IRQ5 T2CLK PF6/IRQ6 TPUCH15 PF7/IRQ7 TPUCH14 BERR TPUCH13 HALT TPUCH12 RESET MC68332 CLKOUT TPUCH11 TPUCH10 TPUCH9 TPUCH8 EXTAL XTAL TPUCH7 TPUCH6...
  • Page 31 Freescale Semiconductor, Inc. Table 3-1 MCU Driver Types Type Description Output-only signals that are always driven; no external pull-up required Type A output with weak P-channel pull-up during reset Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time.

  • Page 32: Signal Descriptions

    Freescale Semiconductor, Inc. Table 3-2 MCU Pin Characteristics (Continued) Output Input Input Discrete Port Mnemonic Driver Synchronized Hysteresis Designation PQS7 — — — Special — — — — Special — XTAL NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.
  • Page 33 Freescale Semiconductor, Inc. Table 3-4 MCU Signal Characteristics (Continued) Signal Signal Active Name Module Type State IFETCH CPU32 Output — IPIPE CPU32 Output — IRQ[7:1] Input MISO Input/Output — MODCLK Input — MOSI Input/Output — PC[6:0] Output (Port) PCS[3:0] Input/Output —...

  • Page 34: Intermodule Bus

    Freescale Semiconductor, Inc. Table 3-5 MCU Signal Function (Continued) Signal Name Mnemonic Function Function Codes FC[2:0] Identify processor state and current address space Freeze FREEZE Indicates that the CPU has entered background mode Halt HALT Suspend external bus activity Instruction Pipeline...

  • Page 35: Internal Register Map

    Freescale Semiconductor, Inc. 3.6.1 Internal Register Map In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent- ed by Y determines the base address of MCU module control registers. In M68300 mi- crocontrollers, Y is equal to M111, where M is the logic state of the module mapping (MM) bit in the system integration module configuration register (SIMCR).
  • Page 36 Freescale Semiconductor, Inc. 000000 VECTOR VECTOR TYPE OF OFFSET NUMBER EXCEPTION 0000 RESET — INITIAL STACK POINTER $XX0000 0004 RESET — INITIAL PC 0008 BUS ERROR 000C ADDRESS ERROR 0010 ILLEGAL INSTRUCTION ZERO DIVISION 0014 0018 CHK, CHK2 INSTRUCTIONS 001C...
  • Page 37 Freescale Semiconductor, Inc. $000000 $000000 VECTOR VECTOR TYPE OF OFFSET NUMBER EXCEPTION 0000 RESET — INITIAL STACK POINTER $XX0000 0004 RESET — INITIAL PC 0008 BUS ERROR 000C ADDRESS ERROR 0010 ILLEGAL INSTRUCTION 0014 ZERO DIVISION 0018 CHK, CHK2 INSTRUCTIONS...
  • Page 38 Freescale Semiconductor, Inc. VECTOR VECTOR EXCEPTION VECTORS LOCATED $000000 $000000 OFFSET NUMBER IN SUPERVISOR PROGRAM SPACE 0000 RESET — INITIAL STACK POINTER $XX0000 0004 RESET — INITIAL PC $XX0004 VECTOR VECTOR EXCEPTION VECTORS LOCATED OFFSET NUMBER IN SUPERVISOR DATA SPACE 0000 RESET —...
  • Page 39 Freescale Semiconductor, Inc. $000000 $000000 USER USER PROGRAM DATA SPACE SPACE $YFF000 $YFFA00 $7FF000 INTERNAL REGISTERS $YFFA80 RESERVED $YFFB00 TPURAM CTL $YFFB40 RESERVED $YFFC00 $YFFE00 $FF0000 INTERNAL REGISTERS $YFFFFF $FFFFFF $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset.

  • Page 40: System Reset

    Freescale Semiconductor, Inc. 3.7 System Reset The following information is a concise reference only. MC68332 system reset is a com- plex operation. To understand operation during and after reset, refer to SECTION 4 SYSTEM INTEGRATION MODULE, paragraph 4.6 Reset for more complete discus- sion of the reset function.

  • Page 41: Mcu Module Pin Function During Reset

    Freescale Semiconductor, Inc. 3.7.2 MCU Module Pin Function During Reset Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers.

  • Page 42: Section 4 System Integration Module

    Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE This section is an overview of SIM function. Refer to the SIM Reference Manual (SIM- RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D REGISTER SUMMARY for information concerning the SIM address map and register structure.

  • Page 43: System Configuration And Protection

    Freescale Semiconductor, Inc. SYSTEM CONFIGURATION AND PROTECTION CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK CHIP SELECTS CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST FREEZE/QUOT S(C)IM BLOCK Figure 4-1 System Integration Module Block Diagram 4.2 System Configuration and Protection The system configuration and protection functional block controls module configura- tion, preserves reset status, monitors internal activity, and provides periodic interrupt generation.

  • Page 44: Module Mapping

    Freescale Semiconductor, Inc. MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR CLOCK SOFTWARE WATCHDOG TIMER RESET REQUEST PRESCALER PERIODIC INTERRUPT TIMER IRQ [7:1] SYS PROTECT BLOCK Figure 4-2 System Configuration and Protection 4.2.1 Module Mapping...

  • Page 45: Show Internal Cycles

    Freescale Semiconductor, Inc. terrupt request is acknowledged, even when there is only a single request pending. For an interrupt to be serviced, the appropriate IARB field must have a non-zero value. If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU32 processes a spurious interrupt exception.

  • Page 46: Bus Monitor

    Freescale Semiconductor, Inc. 4.2.7 Bus Monitor The internal bus monitor checks data and size acknowledge (DSACK) or autovector (AVEC) signal response times during normal bus cycles. The monitor asserts the in- ternal bus error (BERR) signal when the response time is excessively long.
  • Page 47 Freescale Semiconductor, Inc. Perform a software watchdog service sequence as follows: 1. Write $55 to SWSR. 2. Write $AA to SWSR. Both writes must occur before time-out in the order listed, but any number of instruc- tions can be executed between the two writes.

  • Page 48: Periodic Interrupt Timer

    Freescale Semiconductor, Inc. PITR FREEZE PITCLK 8-BIT MODULUS ÷ 4 CLOCK COUNTER INTERRUPT PRECLK CLOCK EXTAL PRESCALER (2 DISABLE RESET SWCLK LPSTOP 15 STAGE SWT1 DIVIDER CHAIN (2 SWT0 PIT BLOCK Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer 4.2.11 Periodic Interrupt Timer...

  • Page 49: Low-Power Stop Operation

    Freescale Semiconductor, Inc. Use the following expression to calculate timer period. PIT Modulus ) Prescaler Value ) 4 ( ) PIT Period --------------------------------------------------------------------------------------------- - EXTAL Frequency Interrupt priority and vectoring are determined by the values of the periodic interrupt request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt control register (PICR).

  • Page 50: Freeze Operation

    Freescale Semiconductor, Inc. 4.2.13 Freeze Operation The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in- ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected.

  • Page 51: Clock Sources

    Freescale Semiconductor, Inc. 4.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock sig- nal from either an internal or an external reference frequency — the clock synthesizer control register (SYNCR) determines operating frequency and mode of operation.
  • Page 52 Freescale Semiconductor, Inc. ply must be used as the V source. Adequate external bypass capacitors should DDSYN be placed as close as possible to the V pin to assure stable operating frequen- DDSYN cy. When an external system clock signal is applied and the PLL is disabled, V...
  • Page 53 Freescale Semiconductor, Inc. When the clock synthesizer is used, control register SYNCR determines operating fre- quency and various modes of operation. The SYNCR W bit controls a three-bit pres- caler in the feedback divider. Setting W increases VCO speed by a factor of four. The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of Y + 1.
  • Page 54 Freescale Semiconductor, Inc. Table 4-7 Clock Control Multipliers (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Prescalers [W:X] = 00 [W:X] = 01...
  • Page 55 Freescale Semiconductor, Inc. Table 4-8 System Frequencies from 32.768–kHz Reference To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Prescaler [W:X] = 00 [W:X] = 01...

  • Page 56: External Bus Clock

    Freescale Semiconductor, Inc. Table 4-8 System Frequencies from 32.768–kHz Reference (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Prescaler [W:X] = 00 [W:X] = 01...

  • Page 57: Loss Of Reference Signal

    Freescale Semiconductor, Inc. During a low-power stop, unless the system clock signal is supplied by an external source and that source is removed, the SIM clock control logic and the SIM clock sig- nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK.

  • Page 58: External Bus Interface

    Freescale Semiconductor, Inc. 4.4 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices. Figure 4-7 shows a basic system with external memory and pe- ripherals. ASYNC BUS PERIPHERAL CLKOUT DSACK DSACK...

  • Page 59: Bus Signals

    Freescale Semiconductor, Inc. 4.4.1 Bus Signals The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an ad- dress and provide timing information for data.

  • Page 60: Size Signals

    Freescale Semiconductor, Inc. 4.4.1.6 Size Signals Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4- 10 shows SIZ0 and SIZ1 encoding.

  • Page 61: Bus Error Signal

    Freescale Semiconductor, Inc. 4.4.1.9 Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK, provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Ex- ception Control Cycles for more information.

  • Page 62: Operand Alignment

    Freescale Semiconductor, Inc. Table 4-12 Effect of DSACK Signals DSACK1 DSACK0 Result Insert Wait States in Current Bus Cycle Complete Cycle — Data Bus Port Size is 8 Bits Complete Cycle — Data Bus Port Size is 16 Bits Reserved...

  • Page 63: Misaligned Operands

    Freescale Semiconductor, Inc. 4.4.4 Misaligned Operands CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address is on a byte boundary only.

  • Page 64: Synchronization To Clkout

    Freescale Semiconductor, Inc. Fast-termination cycles, which are two-cycle external accesses with no wait states, use chip-select logic to generate handshaking signals internally. Chip-select logic can also be used to insert wait states before internal generation of handshaking signals. Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.

  • Page 65: Read Cycle

    Freescale Semiconductor, Inc. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ signals and ADDR0 are externally decoded to select the active portion of the data bus (refer to 4.4.2 Dynamic Bus Sizing). When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle), then asserts a DSACK[1:0] combination that indicates port size.

  • Page 66: Write Cycle

    Freescale Semiconductor, Inc. PERIPHERAL ADDRESS DEVICE (S0) 1) SET R/W TO READ 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS AND DS (S1) PRESENT DATA (S2) 1) DECODE ADDR, R/W, SIZ[1:0], DS...

  • Page 67: Fast Termination Cycles

    Freescale Semiconductor, Inc. PERIPHERAL ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK (S3)

  • Page 68: Cpu Space Cycles

    Freescale Semiconductor, Inc. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). At the appropriate time, chip- select logic asserts data and size acknowledge signals.

  • Page 69: Breakpoint Acknowledge Cycle

    Freescale Semiconductor, Inc. 4.5.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. Breakpoints can be used alone or in conjunction with the background debugging mode. The following paragraphs discuss breakpoint processing when background de- bugging mode is not enabled.
  • Page 70 Freescale Semiconductor, Inc. the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is syn- chronized with an operand fetch, exception processing occurs at the end of the instruc- tion during which BKPT is latched. Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Man- ual (SIMRM/AD) for additional information.
  • Page 71 Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW CPU32 PERIPHERAL ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]...

  • Page 72: Lpstop Broadcast Cycle

    Freescale Semiconductor, Inc. 4.5.4.2 LPSTOP Broadcast Cycle Low-power stop is initiated by the CPU32. Individual modules can be stopped by set- ting the STOP bits in each module configuration register, or the SIM can turn off sys- tem clocks after execution of the LPSTOP instruction. When the CPU executes LPSTOP, the LPSTOP broadcast cycle is generated.
  • Page 73 Freescale Semiconductor, Inc. Retry Termination HALT and BERR are asserted in lieu of, at the same time as, or before DSACK or after DSACK; BERR is negated at the same time or after DSACK; HALT may be negated at the same time or after BERR.

  • Page 74: Bus Errors

    Freescale Semiconductor, Inc. 4.5.5.1 Bus Errors The CPU32 treats bus errors as a type of exception. Bus error exception processing begins when the CPU detects assertion of the IMB BERR signal (by the internal bus monitor or an external source) while the HALT signal remains negated.

  • Page 75: Retry Operation

    Freescale Semiconductor, Inc. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur (refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after exception processing has been completed (during the execution of the exception han- dler routine, or later) does not cause a double bus fault.

  • Page 76: External Bus Arbitration

    Freescale Semiconductor, Inc. The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbi- tration). However, when external bus arbitration occurs while the MCU is halted, ad- dress and control signals go to high-impedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write sig- nals revert to the previous driven states.

  • Page 77: Slave (Factory Test) Mode Arbitration

    Freescale Semiconductor, Inc. REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1) ASSERT BUS REQUEST (BR) 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED...

  • Page 78: Reset

    Freescale Semiconductor, Inc. Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show In- ternal Cycles). This field is cleared by reset. When show cycles are disabled, the address bus, function codes, size, and read/write signals reflect internal bus activity, but AS and DS are not asserted externally and external data bus pins are in high-im- pedance state during internal accesses.

  • Page 79: Reset Control Logic

    Freescale Semiconductor, Inc. 4.6.2 Reset Control Logic SIM reset control logic determines the cause of a reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate re- set lines. Reset control logic can drive four different internal signals.

  • Page 80: Data Bus Mode Selection

    Freescale Semiconductor, Inc. Table 4-16 Reset Mode Selection Mode Select Pin Default Function Alternate Function (Pin Left High) (Pin Pulled Low) DATA0 CSBOOT 16-Bit CSBOOT 8-Bit DATA1 BGACK DATA2 DATA3 ADDR19 DATA4 CS[7:6] ADDR[20:19] DATA5 CS[8:6] ADDR[21:19] DATA6 CS[9:6] ADDR[22:19]...
  • Page 81 Freescale Semiconductor, Inc. DATA15 • • • • • • • • MODE SELECT • • • • DATA1 LINES DATA0 RESET Optional, to prevent conflict on RESET negation. DATA BUS MODE DECODE Figure 4-15 Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC- TERISTICS.

  • Page 82: Clock Mode Selection

    Freescale Semiconductor, Inc. 4.6.3.2 Clock Mode Selection The state of the clock mode (MODCLK) pin during reset determines what clock source the MCU uses. When MODCLK is held high during reset, the clock signal is generated from a reference frequency. When MODCLK is held low during reset, the clock syn- thesizer is disabled, and an external system clock signal must be applied.

  • Page 83: Pin State During Reset

    Freescale Semiconductor, Inc. Table 4-17 Module Pin Functions Module Pin Mnemonic Function CPU32 DSI/IFETCH DSI/IFETCH DSO/IPIPE DSO/IPIPE BKPT/DSCLK BKPT/DSCLK PGP7/IC4/OC5 Discrete Input PGP[6:3]/OC[4:1] Discrete Input PGP[2:0]/IC[3:1] Discrete Input Discrete Input PCLK Discrete Input PWMA, PWMB Discrete Output PQS7/TXD Discrete Input...

  • Page 84: Reset States Of Pins Assigned To Other Mcu Modules

    Freescale Semiconductor, Inc. Table 4-18 SIM Pin Reset States State While Pin State After RESET Released Mnemonic RESET Pin State Pin State Asserted Function Function CS10/ADDR23 CS10 ADDR23 Unknown CS[9:6]/ADDR[22:19]/PC[6:3] CS[9:6] ADDR[22:19] Unknown ADDR[18:0] High-Z Output ADDR[18:0] Unknown ADDR[18:0] Unknown...

  • Page 85: Power-On Reset

    Freescale Semiconductor, Inc. If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated.

  • Page 86: Reset Processing Summary

    Freescale Semiconductor, Inc. CLKOUT LOCK V DD 10 CLOCKS 512 CLOCKS RESET CYCLES ADDRESS AND BUS STATE CONTROL SIGNALS UNKNOWN THREE-STATED NOTES: 1. Internal start-up time. 2. SSP fetched. 3. PC fetched. 4. First instruction fetched. 32 POR TIM Figure 4-16 Power-On Reset 4.6.8 Reset Processing Summary...

  • Page 87: Reset Status Register

    Freescale Semiconductor, Inc. 4.6.9 Reset Status Register The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released.

  • Page 88: Interrupt Acknowledge And Arbitration

    Freescale Semiconductor, Inc. IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.

  • Page 89: Interrupt Processing Summary

    Freescale Semiconductor, Inc. WARNING Do not assign the same arbitration priority to more than one module. When two or more IARB fields have the same nonzero value, the CPU32 interprets multiple vector numbers at the same time, with un- predictable consequences.

  • Page 90: Interrupt Acknowledge Bus Cycles

    Freescale Semiconductor, Inc. B. The processor state is stacked. The S bit in the status register is set, establish- ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. C. The interrupt acknowledge cycle begins: 1. FC[2:0] are driven to %111 (CPU space) encoding.
  • Page 91 Freescale Semiconductor, Inc. ASYNC BUS PERIPHERAL CLKOUT DSACK DSACK IACK ADDR[23:0] ADDR[15:0] DATA[15:0] DATA[15:0] MEMORY ADDR[23:0] DATA[15:8] CSBOOT MEMORY ADDR[23:0] DATA[7:0] 1. Can be decoded to provide additional address space. 2. Varies depending upon peripheral memory size. 32 EXAMPLE SYS BLOCK...

  • Page 92: Chip-Select Registers

    Freescale Semiconductor, Inc. in the corresponding option register is programmed to a nonzero value, selecting a transfer size. The chip-select option must not be written until a base address has been written to a proper base address register. CSBOOT is automatically asserted out of reset.

  • Page 93: Chip-Select Pin Assignment Registers

    Freescale Semiconductor, Inc. 4.8.1.1 Chip-Select Pin Assignment Registers The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin has two or three possible functions, as shown in Table 4-19.

  • Page 94: Chip-Select Base Address Registers

    Freescale Semiconductor, Inc. A pin programmed as a discrete output drives an external signal to the value specified in the pin data register. No discrete output function is available on pins CSBOOT, BR, BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.
  • Page 95 Freescale Semiconductor, Inc. Table 4-22 Option Register Function Summary MODE BYTE STRB DSACK SPACE AVEC 0 = ASYNC* 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 WAIT 00 = CPU SP 000 = All* 0 = Off*...

  • Page 96: Portc Data Register

    Freescale Semiconductor, Inc. to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the val- ues are the same, and other option register constraints are satisfied, a chip select sig- nal is asserted. This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.

  • Page 97: Chip-Select Reset Operation

    Freescale Semiconductor, Inc. During a CPU space cycle, bits [15:3] of the appropriate base register must be config- ured to match ADDR[23:11], as the address is compared to an address generated by the CPU. Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0] are set to %111, designating CPU space access.
  • Page 98 Freescale Semiconductor, Inc. weak internal pull-up drivers for each of the data lines, so that chip-select operation will be selected by default out of reset. However, the internal pull-up drivers can be overcome by bus loading effects — to insure a particular configuration out of reset, use an active device to put the data lines in a known state during reset.

  • Page 99: Parallel Input/Output Ports

    Freescale Semiconductor, Inc. Table 4-24 CSBOOT Base and Option Register Reset Values Fields Reset Values Base Address $000000 Block Size 1 Mbyte Async/Sync Mode Asynchronous Mode Upper/Lower Byte Both Bytes Read/Write Read/Write AS/DS DSACK 13 Wait States Address Space Supervisor/User Space...

  • Page 100: Section 5 Central Processing Unit

    Freescale Semiconductor, Inc. SECTION 5 CENTRAL PROCESSING UNIT The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller applica- tions.

  • Page 101: Cpu32 Registers

    Freescale Semiconductor, Inc. DECODE BUFFER STAGE STAGE STAGE INSTRUCTION PIPELINE CONTROL STORE PROGRAM DATA COUNTER SECTION SECTION CONTROL LOGIC EXECUTION UNIT MICROSEQUENCER AND CONTROL WRITE PENDING PREFETCH BUFFER CONTROLLER MICROBUS CONTROLLER ADDRESS BUS CONTROL DATA SIGNALS 1127A Figure 5-1 CPU32 Block Diagram 5.2 CPU32 Registers...

  • Page 102: Data Registers

    Freescale Semiconductor, Inc. 16 15 DATA REGISTERS 16 15 ADDRESS REGISTERS 16 15 A7 (USP) USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 5-2 User Programming Model 16 15 A7' (SSP) SUPERVISOR STACK POINTER (CCR) STATUS REGISTER VECTOR BASE REGISTER...
  • Page 103 Freescale Semiconductor, Inc. Each of data registers D7–D0 is 32 bits wide. Byte operands occupy the low-order 8 bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits. When a data register is used as either a source or destination operand, only the ap- propriate low-order byte or word (in byte or word operations, respectively) is used or changed;...

  • Page 104: Address Registers

    Freescale Semiconductor, Inc. 5.2.2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Ad- dress registers cannot be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size.

  • Page 105: Alternate Function Code Registers

    Freescale Semiconductor, Inc. All operations to the SR and CCR are word-size operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level. Refer to APPENDIX D REGISTER SUMMARY for bit/field definitions and a diagram of the status register.
  • Page 106 Freescale Semiconductor, Inc. BIT DATA 1 BYTE = 8 BITS INTEGER DATA 1 BYTE = 8 BITS BYTE 0 BYTE 1 BYTE 2 BYTE 3 WORD = 16 BITS WORD 0 WORD 1 WORD 2 LONG WORD = 32 BITS...

  • Page 107: Virtual Memory

    Freescale Semiconductor, Inc. 5.4 Virtual Memory The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 Mbytes of memory available to each user program by using virtual memory techniques.

  • Page 108: Privilege Levels

    Freescale Semiconductor, Inc. The halted processing state is an indication of catastrophic hardware failure. For ex- ample, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts.
  • Page 109 Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary Instruction Syntax Operand Size Operation + X ⇒ Destination ABCD Dn, Dn Source + Destination – (An), – (An) Dn, <ea> 8, 16, 32 Source + Destination ⇒ Destination <ea>, Dn 8, 16, 32 ADDA <ea>, An...
  • Page 110 Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary DBcc Dn, <label> If condition false, then Dn – 1 ⇒ PC; if Dn ∂ (– 1), then PC + d ⇒ PC DIVS/DIVU <ea>, Dn 32/16 ⇒ 16: 16 Destination / Source ⇒ Destination...

  • Page 111: M68000 Family Compatibility

    Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary none none (SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP none none (SP) ⇒ PC; SP + 4 ⇒ SP SBCD Dn, Dn Destination –...

  • Page 112: Special Control Instructions

    Freescale Semiconductor, Inc. 5.8.2 Special Control Instructions Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have been added to the MC68000 instruction set for use in controller applications. 5.8.2.1 Low Power Stop (LPSTOP) In applications where power consumption is a consideration, the CPU32 forces the de- vice into a low power standby mode when immediate processing is not required.

  • Page 113: Types Of Exceptions

    Freescale Semiconductor, Inc. Table 5-2 Exception Vector Assignments Vector Vector Offset Assignment Number Space Reset: Initial Stack Pointer Reset: Initial Program Counter Bus Error Address Error Illegal Instruction Zero Division CHK, CHK2 Instructions TRAPcc, TRAPV Instructions Privilege Violation Trace Line 1010 Emulator...

  • Page 114: Exception Processing Sequence

    Freescale Semiconductor, Inc. Sources of external exception include interrupts, breakpoints, bus errors, and reset re- quests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access con- trol and processor restart.
  • Page 115 Freescale Semiconductor, Inc. causing a change in program flow. In the trace mode, a trace exception is gener- ated after an instruction is executed, allowing a debugger program to monitor the execution of a program under test. Breakpoint Instruction — An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred.

  • Page 116: Enabling Bdm

    Freescale Semiconductor, Inc. TARGET SYSTEM BUS STATE ANALYZER TARGET 1129A Figure 5-8 Bus State Analyzer Configuration 5.10.2.1 Enabling BDM Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal.

  • Page 117: Entering Bdm

    Freescale Semiconductor, Inc. 5.10.2.2.1 External BKPT Signal Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data.

  • Page 118: Bdm Commands

    Freescale Semiconductor, Inc. A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register.

  • Page 119: Background Mode Registers

    Freescale Semiconductor, Inc. 5.10.2.5 Background Mode Registers BDM processing uses three special purpose registers to keep track of program context during development. A description of each follows. 5.10.2.5.1 Fault Address Register (FAR) The FAR contains the address of the faulting bus cycle immediately following a bus or address error.
  • Page 120 Freescale Semiconductor, Inc. INSTRUCTION DEVELOPMENT SYSTEM REGISTER BUS DATA RCV DATA LATCH COMMAND LATCH SERIAL IN PARALLEL IN PARALLEL OUT SERIAL OUT PARALLEL IN SERIAL IN SERIAL OUT PARALLEL OUT STATUS RESULT LATCH EXECUTION UNIT STATUS SYNCHRONIZE DATA MICROSEQUENCER DSCLK...

  • Page 121: Recommended Bdm Connection

    Freescale Semiconductor, Inc. DATA FIELD ⇑ STATUS CONTROL BIT Figure 5-10 BDM Serial Data Word Table 5-6 CPU Generated Message Encoding Bit 16 Data Message Type xxxx Valid Data Transfer FFFF Command Complete; Status OK 0000 Not Ready with Response; Come Again 0001 BERR Terminated Bus Cycle;...

  • Page 122: On-Chip Breakpoint Hardware

    Freescale Semiconductor, Inc. 5.10.5 On-Chip Breakpoint Hardware An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap on any memory access. Off-chip address comparators preclude breakpoints unless show cycles are enabled. Breakpoints on instruction prefetches that are ultimately flushed from the instruction pipeline are not acknowledged;...
  • Page 123 Freescale Semiconductor, Inc. MC68332 CENTRAL PROCESSING UNIT 5-24 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 124: Section 6Queued Serial Module

    Freescale Semiconductor, Inc. SECTION 6 QUEUED SERIAL MODULE This section is an overview of queued serial module (QSM) function. Refer to the QSM Reference Manual (QSMRM/AD) for complete information about the QSM. 6.1 General The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI).

  • Page 125: Qsm Registers And Address Map

    Freescale Semiconductor, Inc. ity. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted until meaningful data is available. 6.2 QSM Registers and Address Map There are four types of QSM registers: QSM global registers, QSM pin control regis- ters, QSPI registers, and SCI registers.

  • Page 126: Freeze Operation

    Freescale Semiconductor, Inc. 6.2.1.2 Freeze Operation The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debugging mode. At the present time, FRZ0 has no effect;...

  • Page 127: Queued Serial Peripheral Interface

    Freescale Semiconductor, Inc. the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. The port QS data direction register (DDRQS) determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output.
  • Page 128 Freescale Semiconductor, Inc. form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate, clocking, and interrupt-driven communication options are available. Serial transfer of any number of bits from eight to sixteen can be specified. Program- mable transfer length simplifies interfacing to a number of devices that require different data lengths.

  • Page 129: Qspi Registers

    Freescale Semiconductor, Inc. QUEUE CONTROL BLOCK QUEUE POINTER COMPARATOR DONE END QUEUE ADDRESS 80-BYTE POINTER QSPI RAM REGISTER CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS CHIP SELECT COMMAND DELAY COUNTER 8/16-BIT SHIFT REGISTER MOSI PROGRAMMABLE Rx/Tx DATA REGISTER LOGIC ARRAY MISO...

  • Page 130: Control Registers

    Freescale Semiconductor, Inc. 6.3.1.1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation. The CPU has read and write access to all control registers, but the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis- ters must be initialized before the QSPI is enabled to ensure defined operation.

  • Page 131: Transmit Ram

    Freescale Semiconductor, Inc. RECEIVE TRANSMIT COMMAND WORD WORD BYTE QSPI RAM MAP Figure 6-3 QSPI RAM 6.3.2.2 Transmit RAM Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally writes one word of data into this segment for each queue command to be executed.

  • Page 132: Qspi Operation

    Freescale Semiconductor, Inc. Table 6-2 QSPI Pin Function Pin/Signal Name Mnemonic Mode Function Master In Slave Out MISO Master Serial Data Input to QSPI Slave Serial Data Output from QSPI Master Out Slave In MOSI Master Serial Data Output from QSPI...

  • Page 133: Qspi Operating Modes

    Freescale Semiconductor, Inc. 6.3.5 QSPI Operating Modes The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the QSPI. Switching between the modes is con- trolled by MSTR in SPCR0.
  • Page 134 Freescale Semiconductor, Inc. BEGIN CPU INITIALIZES QSM GLOBAL REGISTERS CPU INITIALIZES QSM PIN REGISTERS INITIALIZATION OF QSPI BY THE CPU CPU INITIALIZES QSPI CONTROL REGISTERS CPU INITIALIZES QSPI RAM CPU ENABLES QSPI MSTR = 1 QSPI FLOW 1 Figure 6-4 Flowchart of QSPI Initialization Operation...
  • Page 135 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (MASTER MODE) IS QSPI DISABLED HAS NEWQP WORKING QUEUE POINTER BEEN WRITTEN CHANGED TO NEWQP READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL CHIP-SELECT(S) IS PCS TO SCK DELAY...
  • Page 136 Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (SLAVE MODE) IS QSPI DISABLED QUEUE POINTER HAS NEWQP CHANGED TO NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED...
  • Page 137 Freescale Semiconductor, Inc. WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE BIT ASSERTED NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY AFTER TRANSFER EXECUTE PROGRAMMED DELAY ASSERTED EXECUTE STANDARD DELAY QSPI FLOW 4 Figure 6-5 Flowchart of QSPI Master Operation (Part 3)
  • Page 138 Freescale Semiconductor, Inc. IS QSPI DISABLED QUEUE POINTER HAS NEWQP CHANGED TO NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE...
  • Page 139 Freescale Semiconductor, Inc. IS THIS THE ASSERT SPIF LAST COMMAND STATUS FLAG IN THE QUEUE IS INTERRUPT INTERRUPT CPU ENABLE BIT SPIFIE ASSERTED IS WRAP INCREMENT WORKING RESET WORKING QUEUE ENABLE BIT QUEUE POINTER POINTER TO NEWQP OR $0000 ASSERTED...

  • Page 140: Master Mode

    Freescale Semiconductor, Inc. Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0.
  • Page 141 Freescale Semiconductor, Inc. The following expressions apply to SCK baud rate: System Clock SCK Baud Rate ----------------------------------- - 2 SPBR × System Clock SPBR ---------------------------------------------------------------------------------- 2 SCK × ) Baud Rate Desired Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value.
  • Page 142 Freescale Semiconductor, Inc. Table 6-3 BITS Encoding BITS Bits per Transfer 0000 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 1001 1010 1011 1100 1101 1110 1111 Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to com- plete conversion.

  • Page 143: Master Wraparound Mode

    Freescale Semiconductor, Inc. When the proper number of bits have been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM. The command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to NEWQP.
  • Page 144 Freescale Semiconductor, Inc. particular application. SCK is the serial clock input in slave mode. Assertion of the ac- tive-low slave select signal SS initiates slave mode operation. Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used.

  • Page 145: Slave Wraparound Mode

    Freescale Semiconductor, Inc. 6.3.5.4 Slave Wraparound Mode Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master wraparound operation.
  • Page 146 Freescale Semiconductor, Inc. Changing the value of SCI control bits during a transfer operation may disrupt opera- tion. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. (WRITE-ONLY) TRANSMITTER SCDR Tx BUFFER...
  • Page 147 Freescale Semiconductor, Inc. RECEIVER ÷16 BAUD RATE 10 (11) - BIT CLOCK Rx SHIFT REGISTER DATA PIN BUFFER (8) 7 6 5 4 3 2 1 0 RECOVERY ALL ONES PARITY DETECT WAKEUP LOGIC SCCR1 (CONTROL REGISTER 1) SCDR Rx BUFFER...

  • Page 148: Status Register

    Freescale Semiconductor, Inc. 6.4.1.2 Status Register The SCI status register (SCSR) contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a read/write sequence. In gen- eral, flags are cleared by reading the SCSR, then reading (receiver status bits) or writ- ing (transmitter status bits) the SCDR.

  • Page 149: Serial Formats

    Freescale Semiconductor, Inc. • Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time (RT) samples of logic one.

  • Page 150: Parity Checking

    Freescale Semiconductor, Inc. time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period.

  • Page 151: Receiver Operation

    Freescale Semiconductor, Inc. The transmission complete (TC) flag in SCSR shows transmitter shifter state. When TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not automatically cleared. The processor must clear it by first reading SCSR while TC is set, then writing new data to TDR.

  • Page 152: Idle-Line Detection

    Freescale Semiconductor, Inc. Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter.

  • Page 153: Receiver Wakeup

    Freescale Semiconductor, Inc. In some applications, CPU overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line.

  • Page 154: Qsm Initialization

    Freescale Semiconductor, Inc. 6.5 QSM Initialization After reset, the QSM remains in an idle state until initialized. A general sequence guide for initialization follows. A. Global 1. Configuration register (QSMCR) a. Write an interrupt arbitration priority value into the IARB field.
  • Page 155 Freescale Semiconductor, Inc. 3. To receive a. Set the receiver (RE) and receiver interrupt (RIE) bits in SCCR1. 4. To transmit a. Set transmitter (TE) and transmitter interrupt (TIE). b. Clear the transmitter data register empty (TDRE) and transmit complete (TC) indicators by reading the serial communication interface status reg- ister (SCSR).

  • Page 156: Section 7Time Processor Unit

    Freescale Semiconductor, Inc. SECTION 7TIME PROCESSOR UNIT The time processor unit (TPU) is an intelligent, semi-autonomous microcontroller de- signed for timing control. Operating simultaneously with the CPU, the TPU schedules tasks, processes ROM instructions, accesses shared data with the CPU, and performs input and output.

  • Page 157: Tpu Components

    Freescale Semiconductor, Inc. 7.2 TPU Components The TPU module consists of two 16-bit time bases, sixteen independent timer chan- nels, a task scheduler, a microengine, and a host interface. In addition, a dual-port pa- rameter RAM is used to pass parameters between the module and the host CPU.

  • Page 158: Parameter Ram

    Freescale Semiconductor, Inc. 7.2.6 Parameter RAM Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are organized as 128 16-bit words. Although all parameter word locations in RAM can be accessed by all channels, only 100 are normally used: channels 0 to 13 use six parameter words, while channels 14 and 15 each use eight parameter words.

  • Page 159: Channel Orthogonality

    Freescale Semiconductor, Inc. event service time (latency) determines TPU performance in a given application. La- tency can be closely estimated — refer to Freescale TPU Reference Manual (TPURM/ AD) for more information. 7.3.2 Channel Orthogonality Most timer systems are limited by the fixed number of functions assigned to each pin.

  • Page 160: Tpu Interrupts

    Freescale Semiconductor, Inc. To support changing TPU application requirements, Freescale has established a TPU function library. The function library is a collection of TPU functions written for easy as- sembly in combination with each other or with custom functions. Refer to Freescale Pro-...

  • Page 161: Standard And Enhanced Standard Time Functions

    Freescale Semiconductor, Inc. 7.4 Standard and Enhanced Standard Time Functions The following paragraphs describe factory-programmed time functions implemented in standard and enhanced standard TPU microcode ROM. A complete description of the functions is beyond the scope of this manual. Refer to the TPU Reference Manual (TPURM/AD) for additional information.

  • Page 162: Pulse-Width Modulation (Pwm)

    Freescale Semiconductor, Inc. 7.4.4 Pulse-Width Modulation (PWM) The TPU can generate a pulse-width modulation waveform with any duty cycle from zero to 100% (within the resolution and latency capability of the TPU). To define the PWM, the CPU provides one parameter that indicates the period and another param- eter that indicates the high time.

  • Page 163: Stepper Motor (Sm)

    Freescale Semiconductor, Inc. Up to 15 position-synchronized pulse generator function channels can operate with a single input reference channel executing a PMA or PMM input function. The input channel measures and stores the time period between the flywheel teeth and resets TCR2 when the engine reaches a reference position.

  • Page 164: Quadrature Decode (Qdec)

    Freescale Semiconductor, Inc. allowing the latest complete accumulation (over the specified number of periods) to al- ways be available in a parameter. By using the output compare function in conjunction with PPWA, an output signal can be generated that is proportional to a specified input signal.

  • Page 165: Queued Output Match (Qom)

    Freescale Semiconductor, Inc. specified number of transitions, ceasing channel activity until reinitialization. After each transition or specified number of transitions, the channel can generate a link to other channels. 7.5.3 Queued Output Match (QOM) QOM can generate single or multiple output match events from a table of offsets in pa- rameter RAM.

  • Page 166: Universal Asynchronous Receiver/Transmitter (Uart)

    Freescale Semiconductor, Inc. 7.5.7 Universal Asynchronous Receiver/Transmitter (UART) The UART function uses one or two TPU channels to provide asynchronous commu- nications. Data word length is programmable from 1 to 14 bits. The function supports detection or generation of even, odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud.
  • Page 167 Freescale Semiconductor, Inc. 7.6.1 System Configuration Registers The TPU configuration control registers, TPUMCR and TICR, determine the value of the prescaler, perform emulation control, specify whether the external TCR2 pin func- tions as a clock source or as gate of the DIV8 clock for TCR2, and determine interrupt request level and interrupt vector number assignment.

  • Page 168: Emulation Control

    Freescale Semiconductor, Inc. TCR2 DIGITAL EXTERNAL PRESCALER SYNCHRONIZER 00 ÷ 1 FILTER TCR2 PIN TCR2 01 ÷ 2 CONTROL 10 ÷ 4 11 ÷ 8 INT CLK /8 (T2CG CONTROL BIT) 0 – A 1 – B PRESCALER CTL BLOCK 2...

  • Page 169: Channel Control Registers

    Freescale Semiconductor, Inc. 7.6.2 Channel Control Registers The channel control and status registers enable the TPU to control channel interrupts, assign time functions to be executed on a specified channel, or select the mode of op- eration or the type of host service request for the time function specified. Refer to Ta- ble 7-3.

  • Page 170: Development Support And Test Registers

    Freescale Semiconductor, Inc. Table 7-3 Channel Priority Encodings CHX[1:0] Service Guaranteed Time Slots Disabled — 1 out of 7 Middle 2 out of 7 High 4 out of 7 7.6.3 Development Support and Test Registers These registers are used for custom microcode development or for factory test. De- scribing the use of the registers is beyond the scope of this manual.
  • Page 171 Freescale Semiconductor, Inc. MC68332 TIME PROCESSOR UNIT 7-16 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 172: Section 8Standby Ram With Tpu Emulation

    Freescale Semiconductor, Inc. SECTION 8 STANDBY RAM WITH TPU EMULATION The standby RAM module with TPU emulation capability (TPURAM) consists of a con- trol register block and a 2-Kbyte array of fast (two bus cycle) static RAM, which is es- pecially useful for system stacks and variable storage.

  • Page 173: Tpuram Privilege Level

    Freescale Semiconductor, Inc. an address that overlaps the address of the module control register block. Writing a valid base address to TRAMBAR[15:3] clears RAMDS and enables the array. TRAMBAR can be written only once after a master reset. This prevents runaway soft- ware from accidentally re-mapping the array.

  • Page 174: Low-Power Stop Operation

    Freescale Semiconductor, Inc. itance, V supply ramp time, available standby voltage, and available standby current must be known. Assuming that the rate of change is constant as V changes from 0.0 V to 5.5 V (nominal V to nominal V...
  • Page 175 Freescale Semiconductor, Inc. MC68332 STANDBY RAM WITH TPU EMULATION USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 176: Appendix A Electrical Characteristics

    –500 to 500 – 0.3 V NEGCLMAP ≅ + 0.3 POSCLAMP ≅ Operating Temperature Range to T °C MC68332 No Suffix 0 to 70 MC68332 “C” Suffix –40 to 85 MC68332 “V” Suffix –40 to 105 MC68332 “M” Suffix –40 to 125 Storage Temperature Range –55 to 150...
  • Page 177 Freescale Semiconductor, Inc. Table A-2 Typical Ratings, 16.78 MHz Operation Rating Symbol Value Unit Supply Voltage Operating Temperature °C Supply Current LPSTOP, VCO off µA LPSTOP, External clock, maxi f Clock Synthesizer Operating Voltage DDSYN Supply Current DDSYN DDSYN VCO on, maximum f...
  • Page 178 Freescale Semiconductor, Inc. Table A-3 Thermal Characteristics Rating Symbol Value Unit °C/W Thermal Resistance Plastic 132-Pin Surface Mount Θ Plastic 144-Pin Surface Mount Thin Plastic 144-Pin Surface Mount Notes: The average chip-junction temperature (T ) in C can be obtained from: + (P ×...
  • Page 179 Freescale Semiconductor, Inc. Table A-4 16.78 MHz Clock Control Timing and V = 5.0 Vdc ±10%, V = 0 Vdc, T to T DDSYN 32.768 kHz reference Characteristic Symbol Unit PLL Reference Frequency Range System Frequency 16.78 On-Chip PLL System Frequency 0.131...
  • Page 180 Freescale Semiconductor, Inc. Table A-4a. 20.97 MHz Clock Control Timing and V = 5.0 Vdc ±5%, V = 0 Vdc, T to T DDSYN 32.768 kHz reference Characteristic Symbol Unit PLL Reference Frequency Range System Frequency 20.97 On-Chip PLL System Frequency 0.131...
  • Page 181 Freescale Semiconductor, Inc. Table A-5 16.78 MHz DC Characteristics and V = 5.0 Vdc ± 10%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Input High Voltage 0.7 (V + 0.3 Input Low Voltage – 0.3 0.2 (V Input Hysteresis —...
  • Page 182 Freescale Semiconductor, Inc. Table A-5a. 20.97 MHz DC Characteristics and V = 5.0 Vdc ± 5%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Input High Voltage 0.7 (V + 0.3 Input Low Voltage – 0.3 0.2 (V Input Hysteresis —...
  • Page 183 Freescale Semiconductor, Inc. Notes for Tables A–5 and A–5a: 1. Applies to: Port E [7:4] — SIZ[1:0], AS, DS Port F [7:0] — IRQ[7:1], MODCLK Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO TPUCH[15:0], T2CLK BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC EXTAL (when PLL enabled) 2.
  • Page 184 Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing and V = 5.0 Vdc ± 10%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation (32.768 kHz crystal) 0.13 16.78 Clock Period 59.6 — ECLK Period —...
  • Page 185 Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing (Continued) and V = 5.0 Vdc ± 10%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In High Impedance — CLDH DSACK[1:0] Asserted to Data In Valid —...
  • Page 186 Freescale Semiconductor, Inc. Table A-6a. 20.97 MHz AC Timing and V = 5.0 Vdc ± 5%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit Frequency of Operation (32.768 kHz crystal) 0.13 20.97 Clock Period 47.7 — ECLK Period —...
  • Page 187 Freescale Semiconductor, Inc. Table A-6a. 20.97 MHz AC Timing (Continued) and V = 5.0 Vdc ± 5%, V = 0 Vdc, T to T DDSYN Characteristic Symbol Unit CLKOUT Low to Data In High Impedance — CLDH DSACK[1:0] Asserted to Data In Valid —...
  • Page 188 Freescale Semiconductor, Inc. Notes for Tables A–6 and A–6a: 1.All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted. 2.Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
  • Page 189 Freescale Semiconductor, Inc. CLKOUT NOTE: Timing shown with respect to 20% and 70% V DD . 68300 CLKOUT TIM NOTE: Timing shown with respect to 20% and 70% V Figure A-1 CLKOUT Output Timing Diagram EXTAL 68300 EXT CLK INPUT TIM NOTE: Timing shown with respect to 20% and 70% V .
  • Page 190 Freescale Semiconductor, Inc. CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 DSACK0 DSACK1 D0–D15 BERR HALT BKPT 68300 RD CYC TIM Figure A-4 Read Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL A-15 For More Information On This Product, Go to: www.freescale.com...
  • Page 191 Freescale Semiconductor, Inc. CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 DSACK0 DSACK1 D0–D15 BERR HALT BKPT 68300 WR CYC TIM Figure A-5 Write Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS A-16 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 192 Freescale Semiconductor, Inc. CLKOUT A0–A23 FC0–FC2 SIZ0, SIZ1 D0–D15 BKPT 68300 FAST RD CYC TIM Figure A-6 Fast Termination Read Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL A-17 For More Information On This Product, Go to: www.freescale.com...
  • Page 193 Freescale Semiconductor, Inc. CLKOUT A0–A23 FC0–FC2 SIZ0, SIZ1 D0–D15 BKPT 68300 FAST WR CYC TIM Figure A-7 Fast Termination Write Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS A-18 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 194 Freescale Semiconductor, Inc. CLKOUT A0–A23 D0–D15 DSACK0 DSACK1 BGACK 68300 BUS ARB TIM Figure A-8 Bus Arbitration Timing Diagram —Active Bus Case MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL A-19 For More Information On This Product, Go to: www.freescale.com...
  • Page 195 Freescale Semiconductor, Inc. CLKOUT A0–A23 D0–D15 BGACK 68300 BUS ARB TIM IDLE Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case CLKOUT A0–A23 D0–D15 BKPT START OF SHOW CYCLE EXTERNAL CYCLE 68300 SHW CYC TIM NOTE: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion.
  • Page 196 Freescale Semiconductor, Inc. CLKOUT A0–A23 FC0–FC2 SIZ0, SIZ1 D0–D15 68300 CHIP SEL TIM NOTE: AS and DS timing shown for reference only. Figure A-11 Chip Select Timing Diagram RESET D0–D15 68300 RST/MODE SEL TIM Figure A-12 Reset and Mode Select Timing Diagram...
  • Page 197 Freescale Semiconductor, Inc. Table A-7 Background Debugging Mode Timing = 5.0 Vdc ± 10%, V = 0 Vdc, T to T Characteristic Symbol Unit DSI Input Setup Time — DSISU DSI Input Hold Time — DSIH DSCLK Setup Time —...
  • Page 198 Freescale Semiconductor, Inc. CLKOUT FREEZE BKPT/DSCLK IFETCH/DSI IPIPE/DSO 68300 BKGD DBM SER COM TIM Figure A-13 Background Debugging Mode Timing Diagram — Serial Communication CLKOUT FREEZE IFETCH/DSI 68300 BKGD DBM FRZ TIM Figure A-14 Background Debugging Mode Timing Diagram —...
  • Page 199 Freescale Semiconductor, Inc. Table A-8 16.78 MHz ECLK Bus Timing = 5.0 Vdc ± 10%, V = 0 Vdc, T to T Characteristic Symbol Unit ECLK Low to Address Valid — ECLK Low to Address Hold — ECLK Low to CS Valid (CS delay) —...
  • Page 200 Freescale Semiconductor, Inc. CLKOUT ECLK A0–A23 D0–D15 READ WRITE D0–D15 WRITE 68300 E CYCLE TIM NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR) = 0. Figure A-15 ECLK Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL...
  • Page 201 Freescale Semiconductor, Inc. Table A-9 QSPI Timing = 5.0 Vdc ± 10%, V = 0 Vdc, T to T 200 pF load on all QSPI pins) Function Symbol Unit Operating Frequency Master System Clock Frequency Slave System Clock Frequency Cycle Time...
  • Page 202 Freescale Semiconductor, Inc. PCS0–PCS3 OUTPUT CPOL=0 OUTPUT CPOL=1 OUTPUT MISO MSB IN DATA LSB IN MSB IN INPUT MOSI MSB OUT DATA LSB OUT PORT DATA MSB OUT OUTPUT 68300 QSPI T MAST CPHA0 Figure A-16 QSPI Timing — Master, CPHA = 0 PCS0–PCS3...
  • Page 203 Freescale Semiconductor, Inc. INPUT CPOL=0 INPUT CPOL=1 INPUT MISO DATA LSB OUT MSB OUT OUTPUT MOSI MSB IN DATA LSB IN MSB IN INPUT 68300 QSPI T SLV CPHA0 Figure A-18 QSPI Timing — Slave, CPHA = 0 INPUT CPOL=0...
  • Page 204 Freescale Semiconductor, Inc. CLKOUT TPU OUTPUT TPU INPUT TPU I/O TIM Figure A-20 TPU Timing Diagram Table A-10 16.78 MHz Time Processor Unit Timing = 5.0 Vdc ±10%, V and V = 0 Vdc, T to T DDSYN H, 32.768 kHz reference...
  • Page 205 Freescale Semiconductor, Inc. MC68332 ELECTRICAL CHARACTERISTICS A-30 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 206: Appendix B Mechanical Data And Ordering Information

    APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION This section contains detailed information to be used as a guide when ordering. The MC68332 is available in either a 132-pin or 144-pin plastic surface mount pack- age. This appendix provides package pin assignment drawings, dimensional draw- ings, and ordering information.
  • Page 207 Freescale Semiconductor, Inc. V DD V DD V STBY BGACK/C ADDR1 BG/CS1 ADDR2 BR/CS0 ADDR3 CSBOOT ADDR4 DATA0 ADDR5 DATA1 ADDR6 DATA2 ADDR7 DATA3 V DD ADDR8 V DD V SS V SS DATA4 ADDR9 DATA5 ADDR10 DATA6 ADDR11 DATA7...
  • Page 208 Freescale Semiconductor, Inc. V SS V SS FC0/CS3 PE4/AS FC1/CS4 PE6/SIZ0 FC2/CS5 PE7/SIZ1 ADDR19/CS6 ADDR20/CS7 PF0/MODCLK ADDR21/CS8 PF1/IRQ1 ADDR22/CS9 PF2/IRQ2 ADDR23/CS10 PF3/IRQ3 V DD PF4/IRQ4 V SS PF5/IRQ5 T2CLK PF6/IRQ6 TPUCH15 PF7/IRQ7 TPUCH14 BERR TPUCH13 HALT TPUCH12 RESET V SS...
  • Page 209 Freescale Semiconductor, Inc. Case outlines number 831A-01 issue A, 863C-01 issue O, and 918-02 issue A are available on the web at MC68332 MECHANICAL DATA AND ORDERING INFORMATION USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...
  • Page 210 Freescale Semiconductor, Inc. Table B-1 MCU Ordering Information Package Type TPU Type Temperature Frequency Package Order Number (MHz) Order Quantity 132-pin PQFP Motion Control –40 to +85 °C 16 MHz 2 pc tray SPAKMC332GCFC16 36 pc tray MC68332GCFC16* 20 MHz...
  • Page 211 Freescale Semiconductor, Inc. Table B-1 MCU Ordering Information (Continued) Package Type TPU Type Temperature Frequency Package Order Number (MHz) Order Quantity 144-pin QFP Motion Control –40 to +85 °C 16 MHz 2 pc tray SPAKMC332GCFV16 44 pc tray MC68332GCFV16* 20 MHz...
  • Page 212 Freescale Semiconductor, Inc. Table B-1 MCU Ordering Information (Continued) Package Type TPU Type Temperature Frequency Package Order Number (MHz) Order Quantity 144-pin TQFP Motion Control –40 to +85 °C 16 MHz 2 pc tray SPAKMC332GCPV16 60 pc tray MC68332GCPV16* 20 MHz...
  • Page 213 Freescale Semiconductor, Inc. MC68332 MECHANICAL DATA AND ORDERING INFORMATION USER’S MANUAL For More Information On This Product, Go to: www.freescale.com...

  • Page 214: Appendix Cdevelopment Support

    APPENDIX C DEVELOPMENT SUPPORT This section serves as a brief reference to Freescale development tools for the MC68332 microcontroller. Information provided is complete as of the time of publica- tion, but new systems and software are continually being developed. In addition, there is a growing number of third-party tools available.

  • Page 215: M68Mevb1632 Modular Evaluation Board

    Freescale Semiconductor, Inc. C.2 M68MEVB1632 Modular Evaluation Board The M68MEVB1632 Modular Evaluation Board (MEVB) is a development tool for eval- uating M68HC16 and M68300 MCU-based systems. The MEVB consists of the M68HC16MPFB modular platform board, an MCU personality board (MPB), an in-cir- cuit debugger printed circuit board (ICD16 or ICD32), and development software.

  • Page 216: Appendix D Register Summary

    Freescale Semiconductor, Inc. APPENDIX D REGISTER SUMMARY This appendix contains MCU address maps, register diagrams, and bit/field defini- tions. More detailed information about register function is provided in the appropriate sections of the manual. Except for central processing unit resources, information is presented in the intermod- ule bus address order shown in Table D-1.

  • Page 217: D.1.1 Cpu32 Register Model

    Freescale Semiconductor, Inc. D.1.1 CPU32 Register Model 3116 DATA REGISTERS 3116 ADDRESS REGISTERS 3116 A7 (USP) USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure D-1 User Programming Model 3116 A7 (SSP) SUPERVISOR STACK POINTER (CCR) STATUS REGISTER VECTOR BASE REGISTER...

  • Page 218: D.1.2 Sr — Status Register

    Freescale Semiconductor, Inc. D.1.2 SR — Status Register T[1:0] RESET: The status register (SR) contains condition codes, an interrupt priority mask, and three control bits. The condition codes are contained in the condition code register (CCR), the lower byte of the SR. (The lower and upper bytes of the status register are also referred to as the user and system bytes, respectively.) At the user privilege level, only...
  • Page 219 Freescale Semiconductor, Inc. Table D-2 SIM Address Map Access Address $YFFA00 SIM CONFIGURATION (SIMCR) $YFFA02 FACTORY TEST (SIMTR) $YFFA04 CLOCK SYNTHESIZER CONTROL (SYNCR) $YFFA06 NOT USED RESET STATUS REGISTER (RSR) $YFFA08 MODULE TEST E (SIMTRE) $YFFA0A NOT USED NOT USED...
  • Page 220 Freescale Semiconductor, Inc. Table D-2 SIM Address Map Access Address $YFFA5E CHIP-SELECT OPTION 4 (CSOR4) $YFFA60 CHIP-SELECT BASE 5 (CSBAR5) $YFFA62 CHIP-SELECT OPTION 5 (CSOR5) $YFFA64 CHIP-SELECT BASE 6 (CSBAR6) $YFFA66 CHIP-SELECT OPTION 6 (CSOR6) $YFFA68 CHIP-SELECT BASE 7 (CSBAR7)
  • Page 221 Freescale Semiconductor, Inc. SUPV — Supervisor/Unrestricted Data Space The SUPV bit places the SIM global registers in either supervisor or user data space. 0 = Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.
  • Page 222 Freescale Semiconductor, Inc. RSTEN — Reset Enable 0 = Loss of reference causes the MCU to operate in limp mode. 1 = Loss of reference causes system reset. STSIM — Stop Mode System Integration Clock 0 = SIM clock driven by an external source and VCO off during low-power stop.
  • Page 223 Freescale Semiconductor, Inc. D.2.6 PORTE0/PORTE1 — Port E Data Register $YFFA11, $YFFA13 NOT USED RESET: PORTE is an internal data latch that can be accessed at two locations. PORTE can be read or written at any time. If a pin in I/O port E is configured as an output, the corre- sponding bit value is driven out on the pin.
  • Page 224 Freescale Semiconductor, Inc. D.2.9 PORTF0/PORTF1 — Port F Data Register $YFFA19, $YFFA1B NOT USED RESET: PORTF is an internal data latch that can be accessed at two locations. It can be read or written at any time. If a pin in I/O port F is configured as an output, the corresponding bit value is driven out on the pin.
  • Page 225 Freescale Semiconductor, Inc. D.2.12 SYPCR — System Protection Control Register $YFFA21 NOT USED RESET: MODCLK SYPCR controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written once following power-on or reset. SWE — Software Watchdog Enable...
  • Page 226 Freescale Semiconductor, Inc. D.2.13 PICR — Periodic Interrupt Control Register $YFFA22 PIRQL RESET: Contains information concerning periodic interrupt priority and vectoring. PICR[10:0] can be read or written at any time. PICR[15:11] are unimplemented and always return zero. PIRQL[2:0] — Periodic Interrupt Request Level This field determines the priority of periodic interrupt requests.
  • Page 227 Freescale Semiconductor, Inc. D.2.18 TSTSC — Test Module Shift Count $YFFA34 Register is used for factory test only. D.2.19 TSTRC — Test Module Repetition Count $YFFA36 Register is used for factory test only. D.2.20 CREG — Test Submodule Control Register $YFFA38 Register is used for factory test only.
  • Page 228 Freescale Semiconductor, Inc. D.2.24 CSPAR1 — Chip Select Pin Assignment Register 1 $YFFA46 CSPA1[4] CSPA1[3] CSPA1[2] CSPA1[1] CSPA1[0] RESET: DATA7 DATA6 DATA5 DATA4 DATA3 CSPAR1 Pin Assignments CSPAR1 Field CSPAR1 Signal Alternate Signal Discrete Output CSPA1[4] CS10 ADDR23 ECLK CSPA1[3]...
  • Page 229 Freescale Semiconductor, Inc. BLKSZ — Block Size This field determines the size of the block above the base address that is enabled by the chip select. Block Size Encoding BLKSZ[2:0] Block Size Address Lines Compared ADDR[23:11] ADDR[23:13] 16 K ADDR[23:14]...
  • Page 230 Freescale Semiconductor, Inc. This field selects an address space to be used by the chip-select logic. IPL — Interrupt Priority Level This field determines interrupt priority level when a chip select is used for interrupt ac- knowledge. It does not affect CPU interrupt recognition.

  • Page 231: D.3 Standby Ram Module With Tpu Emulation

    Freescale Semiconductor, Inc. D.3 Standby RAM Module with TPU Emulation Table D-3 is the TPURAM address map. TPURAM responds to both program and data space accesses. The RASP bit in the TRAMMCR determines whether the processor must be operating at the supervisor privilege level to access the array. TPURAM con- trol registers are accessible at the supervisor privilege level only.
  • Page 232 Freescale Semiconductor, Inc. RAMDS — RAM Array disabled 0 = RAM array is enabled 1 = RAM array is disabled The TPURAM array is disabled by internal logic after a master reset. Writing a valid base address to the RAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the RAM array.

  • Page 233: D.4 Queued Serial Module

    Freescale Semiconductor, Inc. D.4 Queued Serial Module Table D-4 is the QSM address map. The column labeled “Access” indicates the privi- lege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.

  • Page 234: D.4.3 Qilr — Qsm Interrupt Level Register

    Freescale Semiconductor, Inc. reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP. FRZ[1:0] — Freeze Control...
  • Page 235 Freescale Semiconductor, Inc. INTV[7:0] — Interrupt Vector Number The values of INTV[7:1] are the same for both QSPI and SCI interrupt requests; the value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM. INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI interrupt.
  • Page 236 Freescale Semiconductor, Inc. PT — Parity Type 0 = Even parity 1 = Odd parity PE — Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled M — Mode Select 0 = 10-bit SCI frame 1 = 11-bit SCI frame WAKE —...
  • Page 237 Freescale Semiconductor, Inc. D.4.6 SCSR — SCI Status Register $YFFC0C NOT USED TDRE RDRF IDLE RESET: SCSR contains flags that show SCI operating conditions. These flags are cleared ei- ther by SCI hardware or by a CPU32 read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR.

  • Page 238: D.4.9 Pqspar — Port Qs Pin Assignment Register

    Freescale Semiconductor, Inc. PF — Parity Error 0 = No parity error on the received data 1 = Parity error occurred on the received data. D.4.7 SCDR — SCI Data Register $YFFC0E R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1...
  • Page 239 Freescale Semiconductor, Inc. PQSPAR Pin Assignments PQSPAR Field PQSPAR Bit Pin Function PQSPA0 PQS0 MISO PQSPA1 PQS1 MOSI PQSPA2 PQS2 PQSPA3 PQS3 PCS0/SS PQSPA4 PQS4 PCS1 PQSPA5 PQS5 PCS2 PQSPA6 PQS6 PCS3 PQSPA7 PQS7 NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK 2.
  • Page 240 Freescale Semiconductor, Inc. Effect of DDRQS on QSM Pin Function QSM Pin Mode DDRQS Bit Pin Function State MISO Master DDQS0 Serial Data Input to QSPI Disables Data Input Slave Disables Data Output Serial Data Output from QSPI MOSI Master...
  • Page 241 Freescale Semiconductor, Inc. WOMQ — Wired-OR Mode for QSPI Pins 0 = Outputs have normal MOS drivers. 1 = Pins designated for output by DDRQS have open-drain drivers. BITS — Bits Per Transfer The BITS field determines the number of serial data bits transferred.
  • Page 242 Freescale Semiconductor, Inc. D.4.12 SPCR2 — QSPI Control Register 2 $YFFC1C SPIFIE WREN WRTO ENDQP NEWQP RESET: SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read ac- cess only.
  • Page 243 Freescale Semiconductor, Inc. HMIE — HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled 1 = HALTA and MODF interrupts enabled HALT — Halt 0 = Halt not enabled 1 = Halt enabled SPIF — QSPI Finished Flag...
  • Page 244 Freescale Semiconductor, Inc. D.4.16 CR[0:F] — Command RAM $YFFD40–$YFFD4F CONT BITSE DSCK PCS3 PCS2 PCS1 PCS0* — — — — — — — — CONT BITSE DSCK PCS3 PCS2 PCS1 PCS0* COMMAND CONTROL PERIPHERAL CHIP SELECT *The PCS0 bit represents the dual-function PCS0/SS.
  • Page 245 Freescale Semiconductor, Inc. D.5 Time Processor Unit Table D-5 is the TPU address map. The column labeled “Access” indicates the privi- lege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.
  • Page 246 Freescale Semiconductor, Inc. PSCK = 0 PSCK = 1 TCR1 Prescaler Divide Number of Rate at Number of Rate at Clocks 16 MHz Clocks 16 MHz 2 ms 250 ns 4 ms 500 ns 8 ms 1 ms 16 ms 2 ms TCR2P —...
  • Page 247 Freescale Semiconductor, Inc. PSCK — Prescaler Clock 0 = System clock/32 is input to TCR1 prescaler 1 = System clock/4 is input to TCR1 prescaler IARB — Interrupt Arbitration Each module that generates interrupts must have an IARB value. IARB values are used to arbitrate between interrupt requests of the same priority.
  • Page 248 Freescale Semiconductor, Inc. BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits DSCR[5:0] are TPU breakpoint enables. Setting a bit enables a breakpoint condition. BP — Break if mPC equals mPC breakpoint register. BC — Break if CHAN register equals channel breakpoint register at beginning of state or when CHAN is changed through microcode.
  • Page 249 Freescale Semiconductor, Inc. CIRL — Channel Interrupt Request Level This three-bit encoded field specifies the interrupt request level for all channels. Level seven for this field indicates a nonmaskable interrupt; level zero indicates that all chan- nel interrupts are disabled.
  • Page 250 Freescale Semiconductor, Inc. D.5.11 HSQR0 — Host Sequence Register 0 $YFFE14 CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 RESET: D.5.12 HSQR1 — Host Sequence Register 1 $YFFE16 CH 7 CH 6...
  • Page 251 Freescale Semiconductor, Inc. D.5.15 CPR0 — Channel Priority Register 0 $YFFE1C CH 15 CH 14 CH13 CH 12 CH 11 CH 10 CH 9 CH 8 RESET: D.5.16 CPR1 — Channel Priority Register 1 $YFFE1E CH 7 CH 6 CH 5...

  • Page 252: D.5.21 Tpu Parameter Ram

    Freescale Semiconductor, Inc. D.5.20 DCNR — Decoded Channel Number Register $YFFE26 CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1...
  • Page 253 Freescale Semiconductor, Inc. Table D-7 MC68332 Module Address Map (Assumes SIMCR MM = 1) Access Address $FFFA00 MODULE CONFIGURATION (SIMCR) $FFFA02 FACTORY TEST (SIMTR) $FFFA04 CLOCK SYNTHESIZER CONTROL (SYNCR) $FFFA06 NOT USED RESET STATUS (RSR) $FFFA08 MODULE TEST E (SIMTRE)
  • Page 254 Freescale Semiconductor, Inc. Table D-7 MC68332 Module Address Map (Continued) (Assumes SIMCR MM = 1) Access Address 15 8 $FFFA5A CHIP-SELECT OPTION 3 (CSOR3) $FFFA5C CHIP-SELECT BASE 4 (CSBAR4) $FFFA5E CHIP-SELECT OPTION 4 (CSOR4) $FFFA60 CHIP-SELECT BASE 5 (CSBAR5) $FFFA62...
  • Page 255 Freescale Semiconductor, Inc. Table D-7 MC68332 Module Address Map (Continued) (Assumes SIMCR MM = 1) Access Address 15 8 $FFFD20– TRANSMIT RAM (TR[0:F]) QUEUE RAM $FFFD3F $FFFD40– COMMAND RAM (CR[0:F]) QUEUE RAM $FFFD4F Access Address 15 8 $FFFE00 TPU MODULE CONFIGURATION REGISTER (TPUMCR)
  • Page 256 Freescale Semiconductor, Inc. Table D-8 Register Bit and Field Mnemonics Mnemonic Name Register Location ADDR[23:11] Base Address CSBAR[0:10], CSBARBT, TRAMBAR AVEC Autovector Enable CSOR[0:10], CSORBT BP, BC, BH, Breakpoint Enable Points DSCR BL, BM, BT BITS Bits Per Transfer SPCR0...
  • Page 257 Freescale Semiconductor, Inc. Table D-8 Register Bit and Field Mnemonics (Continued) Mnemonic Name Register Location Framing Error SCSR FRZBM Freeze Bus Monitor Enable SIMCR FRZSW Freeze Software Enable SIMCR FRZ[1:0] Freeze Control DSCR, QSMCR HALT Halt SPCR3 HALTA Halt Acknowledge Flag...
  • Page 258 Freescale Semiconductor, Inc. Table D-8 Register Bit and Field Mnemonics (Continued) Mnemonic Name Register Location Periodic Timer Prescaler Control PITR Receiver Active SCSR RAMDS TPURAM Array Disable TRAMBAR RASP[1:0] TPURAM Array Space TRAMMCR RDRF Receive Data Register Full SCSR Receiver Enable...
  • Page 259 Freescale Semiconductor, Inc. Table D-8 Register Bit and Field Mnemonics (Continued) Mnemonic Name Register Location Overflow Flag Frequency Control (VCO) SYNCR WAKE Wakeup by Address Mark SCCR1 WOMQ Wired-OR Mode for QSPI Pins SPCR0 WOMS Wired-OR Mode for SCI Pins...
  • Page 260 This is a complete revision, with complete reprint. All known errors in the publication have been corrected. The following summary lists significant changes. Section 1 Introduction Page 1-1 New introduction to the MC68332 microcontroller. Section 2 Nomenclature Page 2-1 Added “Symbols and Operators” section.
  • Page 261 Completely revised electrical characteristics section. Add- ed 20.97 MHz timing parameters. Appendix B Mechanical Data and Ordering Information Pages B-1 – B-10 Revised MC68332 132-pin assignment drawing. Included new diagrams on 144-pin assignment and package dimen- sions. Revised ordering information table. Appendix C Development Support Pages C-1 –...
  • Page 262 Freescale Semiconductor, Inc. INDEX Chip-select operation 4-55 –A– Chip-select pins 4-51 CIER 7-14 Address bus 4-18 CIRL 7-5 Address registers CISR 7-11, 7-14 fault 5-20 Clock mode (MODCLK) 4-10 general-purpose 5-1 Clock synthesizer control register (SYNCR) 4-10 Address strobe (AS) 4-18...
  • Page 263 Freescale Semiconductor, Inc. ECLK 4-15 loop mode 5-23 EDIV 4-15 Instruction set 5-9 End queue pointer 6-9 Instructions ENDQP 6-9 ABCD 5-4 Error flags, SCI 6-29 BCD 5-4 Exception vector table 6-3 low-power stop 5-13 Exceptions MOVEC 5-6 internal 5-14...
  • Page 264 Freescale Semiconductor, Inc. MSTR 6-10, 6-17 PORTE 4-58 Multimaster operation 6-10 PORTF 4-58 PORTQS 6-4 PQSPAR 6-3, 6-17, 6-20, 6-25 –N– Privilege level supervisor 5-5 N 5-5 Privilege levels 5-9 Negative (N) 5-5 user New queue pointer 6-9 supervisor 5-2...
  • Page 265 Freescale Semiconductor, Inc. Receive data register (RDR) 6-28 SIM 1-1, 3-1, 4-1 Receive RAM 6-7 SIM configuration register (SIMCR) 4-3 Receive time (RT) clock 6-29 SIMCLK 4-16 Receive time (RT) sampling clock 6-26 SIMCR 3-10, 4-3 Receiver data register flag (RDRF) 6-29...
  • Page 266 Freescale Semiconductor, Inc. TE 6-27 TICR 7-12 TIE 6-28 Time processor unit (TPU) 3-1, 7-1 Timer control registers TCR1 7-12 TCR2 7-12 TPU 1-1, 3-1 TPU functions enhanced 7-6 standard 7-6 TPU module configuration register (TPUMCR) 7-2 TPUMCR 7-2, 7-12...

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