Freescale Semiconductor MC9S12XE Series Reference Manual

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MC9S12XEP100

Reference Manual

Covers MC9S12XE Family

HCS12X

Microcontrollers

MC9S12XEP100RMV1

Rev. 1.19

12/2008

freescale.com

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Summary of Contents for Freescale Semiconductor MC9S12XE Series

Page 1 MC9S12XEP100 Reference Manual Covers MC9S12XE Family HCS12X Microcontrollers MC9S12XEP100RMV1 Rev. 1.19 12/2008 freescale.com...
Page 2 To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ This document contains information for the complete S12XE-Family and thus includes a set of separate flash (FTM) module sections to cover the whole family.
Page 3 128 KByte Flash Module (S12XFTM128K2V1) ... . 831 Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) ... . 891 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 4: Table Of Contents
Appendix F Ordering Information ....... 1321 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 5 BLANK PAGE MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 6 BLANK PAGE MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 7 2.1.1 Overview ............. 89 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 8 2.3.42 Port M Polarity Select Register (PPSM) ........135 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 9 2.3.87 Port R Data Direction Register (DDRR) ........165 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 10 3.4.3 Chip Access Restrictions ..........217 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 11 5.5.2 Emulation Modes ............257 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 12 7.4.9 SYNC — Request Timed Reference Pulse ........299 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 13 10.3 Memory Map and Register Deﬁnition ..........354 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 14 11.6 Interrupts ..............495 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 15 14.2.2 IOC6 — Input Capture and Output Compare Channel 6 ......527 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 16 16.2.1 RXCAN — CAN Receiver Input Pin ........605 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 17 18.1.4 Block Diagram ............678 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 18 20.2 External Signal Description ........... . . 725 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 19 21.4.7 Low Power Mode Options ..........784 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 20 23.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins ......819 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 21 25.1 Introduction ..............892 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 22: Chapter 26 384 Kbyte Flash Module (S12Xftm384K2V1)
27.1 Introduction ..............1016 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 23: Chapter 28 768 Kbyte Flash Module (S12Xftm768K4V2)
29.1 Introduction ..............1140 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 24: Appendix A Electrical Characteristics
A.6 Reset, Oscillator and PLL ............1235 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 25: Appendix B Package Information
D.2 Pinout explanations: ............1269 Appendix E Detailed Register Address Map Appendix F Ordering Information MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 26 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 27: Chapter 1 Device Overview Mc9S12Xe-Family
208-Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options. 1.1.1 Features Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 28 — Good noise immunity — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal — Transconductance sized for optimum start-up margin for typical crystals • IPLL (Internally ﬁltered, frequency modulated phase-locked-loop clock generation) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 29 — Wake from low power modes on analog comparison > or <= match • Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules) — Five receive and three transmit buffers MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 30 — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3V and 5V range operation — Low-voltage reset (LVR) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 31 — Special test mode (Freescale use only) Low-power modes: • System stop modes — Pseudo stop mode — Full stop mode with fast wake-up option • System wait mode Operating system states • Supervisor state • User state MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 32 DATA[7:0] PD[7:0] SCI7 Asynchronous Serial IF SCI2 Asynchronous Serial IF IIC0 IIC1 Inter IC Module Inter IC Module SCI3 CAN4 RXCAN Asynchronous Serial IF msCAN 2.0B TXCAN MC9S12XE-Family Block Diagram Figure 1-1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 33 SPI2 (serial peripheral interface) 0x0100–0x0113 FTM control registers 0x0114–0x011F MPU (memory protection unit) 0x0120–0x012F INT (interrupt module) 0x0130–0x0137 SCI4 (serial communications interface) 0x0138–0x013F SCI5 (serial communications interface) 0x0140–0x017F CAN0 0x0180–0x01BF CAN1 0x01C0–0x01FF CAN2 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 34 S12XE CPU & BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map. EEEPROM size is presented like a ﬁxed 256 KByte in the memory map. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 35 2 ranges separated by an unimplemeted range, as depicted by the dashed lines. For more information refer to tables below and MMC section. 0x7F_FFFF Figure 1-2. MC9S12XE100 Global Memory Map MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 36 Accessing reserved registers within the 2K register space does not generate an illegal address reset. The ﬁxed 8K RAM default location in the global map is 0x0F_E000- 0x0F_FFFF. This is subject to remapping when conﬁguring the local address map for a larger RAM access range. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 37 0x7F_0000 to 0x7F_FFFF Table 1-5. Derivative Dependent Flash Block Mapping Device 0x70_0000 0x74_0000 0x78_0000 0x7A_0000 0x7C_0000 0x7E_0000 9S12XEP100 9S12XEP768 — 9S12XEQ512 — — 9S12XEx384 — — — 9S12XET256 — — — — B0(128K) 9S12XEA256 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 38 The block B0 is a reduced size 128K block on the 256K derivative. On the larger derivatives B0 is a 256K block. The block B0 is a reduced size 64K block on the 128K derivative. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 39 Chapter 1 Device Overview MC9S12XE-Family XGATE Global Memory Map Local Memory Map 0x00_0000 Registers 0x00_07FF 0x0000 Registers XGRAM_LOW 0x0800 0x0F_FFFF FLASH 0x78_0800 FLASH XGFLASH_HIGH 0xFFFF 0x7F_FFFF Figure 1-3. XGATE Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 40 The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and Mask Set number. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 41 Bit 5-4: Major mask set revision number including FAB transfers Bit 3-0: Minor — non full — mask set revision Currently available as MC9S12XEP100 die only Currently available as MC9S12XEQ512 die only Currently available as MC9S12XET256 die only MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 42 208-pin MAPBGA package with an external bus interface (address/data bus) • 144-pin LQFP package with an external bus interface (address/data bus) • 112-pin LQFP without external bus interface • 80-pin QFP without external bus interface MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 43 PD7 PAD24 PAD01 PJ1 BKGD VDDX VDDX PD4 PAD00 PAD08 VDDX VDDR VSS3 VDDX PE4 RESET PL7 N.C. N.C. N.C. N.C. EXTAL XTAL N.C. N.C. Figure 1-4. - Pin Assignments, 208 MAPBGA Package MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 44 PA5/ADDR13 DATA11/PC3 PA4/ADDR12 UDS/ADDR0/PB0 Pins shown in BOLD are not available on the 80 QFP package PA3/ADDR11 ADDR1/PB1 PA2/ADDR10 ADDR2/PB2 PA1/ADDR9 ADDR3/PB3 PA0/ADDR8 ADDR4/PB4 Figure 1-5. MC9S12XE-Family Pin Assignments 144-pin LQFP Package MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 45 PAD02/AN02 IOC4/PT4 PAD09/AN09 VREGAPI/IOC5/PT5 PAD01/AN01 IOC6/PT6 PAD08/AN08 Pins shown in BOLD are not available on the 80 QFP package IOC7/PT7 PAD00/AN00 VSS2 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD Figure 1-6. MC9S12XE-Family Pin Assignments 112-pin LQFP Package MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 46 TIMIOC1/MOSI1/PWM1/KWP1/PP1 PAD07/AN07 TIMIOC0/MISO1/PWM0/KWP0/PP0 PAD06/AN06 IOC0/PT0 PAD05/AN05 IOC1/PT1 PAD04/AN04 IOC2/PT2 PAD03/AN03 MC9S12XE-Family IOC3/PT3 PAD02/AN02 80QFP VDDF PAD01/AN01 VSS1 PAD00/AN00 IOC4/PT4 VSS2 VREGAPI/IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD Figure 1-7. MC9S12XE-Family Pin Assignments 80-pin QFP Package MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 47 NOTE SPECIAL BOND-OUT TO PROVIDE ACCESS TO EXTRA ADC CHANNELS IN 80QFP. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. THE MC9S12XET256 AND MC9S12XEG128 USE THE STANDARD 80QFP BOND-OUT, COMPATIBLE WITH OTHER FAMILY MEMBERS. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 48 Ports are available for each package option. Routing of pin functions is summarized in Table 1-8. Table 1-9 provides a pin out summary listing the availability of individual pins for each package option. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 49 The 9S12XEA256 is a special bondout for access to extra ADC channels in 80QFP. Available in 80QFP / 256K memory size only. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. The 9S12XET256 is the standard 256K/80QFP bondout, compatible with other family members. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 50 Table 1-8. Peripheral - Port Routing Options PF[0] PF[1] PF[2] PF[3] PF[5:4] PF[7:6] PH[1:0] PH[3:2] PH[5:4] PH[7:6] PJ[0] PJ[1] PJ[2] PJ[3] PJ[4] PJ[5] PJ[7:6] PL[1:0] PL[3:2] PL[5:4] PL[7:6] PM[1:0] PM[3:2] PM[5:4] PM[7:6] PP[3:0] PP[7:4] PR[7:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 51 TIMIOC2 KWP1 PWM1 MOSI1 TIMIOC1 KWP0 PWM0 MISO1 TIMIOC0 KWJ3 KWJ2 ADDR22 ACC2 ADDR19 IQSTAT3 ADDR18 IQSTAT2 ADDR17 IQSTAT1 ADDR16 IQSTAT0 VDDX VDDX7 VSSX VSSX7 IOC0 TIMIOC0 IOC1 TIMIOC1 IOC2 TIMIOC2 IOC3 TIMIOC3 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 52 ADDR20 ACC0 KWJ1 TXD2 KWJ0 RXD2 BKGD MODC VDDX VDDX4 VSSX VSSX4 DATA8 DATA9 DATA10 DATA11 ADDR0 IVD0 ADDR1 IVD1 ADDR2 IVD2 ADDR3 IVD3 ADDR4 IVD4 ADDR5 IVD5 ADDR6 IVD6 ADDR7 IVD7 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 53 MOSI2 TXD4 RXD4 KWH4 MISO2 RXD4 XCLKS ECLKX2 MODB TAGHI MODA TAGLO ECLK VSSX VSSX2 VDDX VDDX2 RESET VDDR VSS3 R9/T8 VSSPLL EXTAL XTAL R10/T11 VDDPLL TXD7 KWH3 TXD7 RXD7 KWH2 SCK1 RXD7 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 54 DATA3 VDDX VDDX5 VSSX VSSX5 LSTRB EROMCTL XIRQ ADDR8 IVD8 ADDR9 IVD9 ADDR10 IVD10 ADDR11 IVD11 ADDR12 IVD12 ADDR13 IVD13 ADDR14 IVD14 ADDR15 IVD15 VSSX VSSX3 VDDX VDDX3 DATA4 DATA5 DATA6 DATA7 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 55 AN03 PAD11 AN11 PAD27 AN27 PAD04 AN04 PAD12 AN12 PAD28 AN28 PAD05 AN05 PAD13 AN13 PAD29 AN29 PAD06 AN06 PAD14 AN14 PAD30 AN30 PAD07 AN07 PAD15 AN15 PAD31 AN31 PAD16 AN16 PAD17 AN17 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 56 PAD23 AN23 TXCAN3 TXCAN4 TXD3 RXCAN3 RXCAN4 RXD3 RXD0 TXD0 RXD1 TXD1 VSSX VSSX6 VDDX VDDX6 MISO0 MOSI0 SCK0 TEST KWJ7 TXCAN4 SCL0 TXCAN0 KWJ6 RXCAN4 SDA0 RXCAN0 KWJ5 SCL1 KWJ4 SDA1 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 57 RXCAN0 TXD3 VSSX VSSX1 VDDX VDDX1 ROMCTL EWAIT KWP7 PWM7 SCK2 TIMIOC7 KWP6 PWM6 TIMIOC6 KWP5 PWM5 MOSI2 TIMIOC5 KWP4 PWM4 MISO2 TIMIOC4 Standard 80QFP only. NOTE that XEA256 80QFP is not compatible MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 58 Port F I/O, interrupt, SCL of PPSF IIC0 SDA0 — — — PERF/ Port F I/O, interrupt, SDA of PPSF IIC0 — — — PERF/ Port F I/O, interrupt, chip PPSF select 3 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 59 Port J I/O, interrupt, TXD of PPSJ SCI2 KWJ0 RXD2 — PERJ/ Port J I/O, interrupt, RXD of PPSJ SCI2 EWAIT ROMCTL — — PUCR Port K I/O, EWAIT input, ROM on control MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 60 PERP/ Disabled Port P I/O, interrupt, channel PPSP 6 of PWM/TIM, SS of SPI2 KWP5 PWM5 MOSI2 TIMIOC5 PERP/ Disabled Port P I/O, interrupt, channel PPSP 5 of PWM/TIM, MOSI of SPI2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 61 Disabled Port T I/O, ECT channels PPST PT[5] IOC[5] VREGAPI — — PERT/ Disabled Port T I/O, ECT channels PPST PT[4:0] IOC[4:0] — — — PERT/ Disabled Port T I/O, ECT channels PPST MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 62 PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital converter ATD0. 1.2.3.6 PAD[31:16] / AN[31:16] — Port AD Input Pins of ATD1 PAD[31:16] are general-purpose input or output pins and analog inputs AN[31:16] of the analog-to-digital converter ATD1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 63 Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Oscillator Conﬁguration). An internal pullup is enabled during reset. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 64 PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 65 (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). It can be conﬁgured as the transmit pin TXD of serial communication interface 4 (SCI4). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 66 PJ6 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be conﬁgured as the receive pin RXCAN for the scalable controller area network controller 0 or 4 (CAN0 or CAN4) or as the serial data pin SDA of the IIC0 module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 67 ACC[2:0] signals are used to indicate the access source of the bus cycle. These pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 68 PL0 / RXD4 — Port L I/O Pin 0 PL0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXD of serial communication interface 4 (SCI4). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 69 PM0 / RXCAN0 — Port M I/O Pin 0 PM0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the scalable controller area network controller 0 (CAN0). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 70 (PWM) channel 1 output, TIM channel 1, or master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 71 1.2.3.75 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial communication interface 0 (SCI0). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 72 VDD. The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS1,VSS2 and VSS3 pins. No static external loading of these pins is permitted. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 73 5.0 V 1.8 V Internal power and ground generated by internal regulator for the internal core. VSS1, VSS2, VSS3 VDDF 2.8 V Internal power and ground generated by internal regulator for the internal NVM. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 74 1.8 V Provides operating voltage and ground for the phased-locked loop. This allows the VSSPLL supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 75 The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-9, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 76 MMCCTL1 register deﬁnes if the on chip ﬂash memory is the memory map, or not. (See Table 1-12.) For a detailed explanation of the ROMON and EROMON bits refer to the MMC description. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 77 Developers use this mode for emulation systems in which the users target application is normal expanded mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 78 (RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed wake up time from this mode is signiﬁcantly shorter. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 79 Supervisor state on completion of each task. This is the default ’state’ following reset and can be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 80 I-bit maskable service request is a conﬁguration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 81 CRG self-clock mode I bit CRGINT (SCMIE) Refer to CRG interrupt section Vector base + $C2 SCI6 I bit SCI6CR2 (TIE, TCIE, RIE, ILIE) Vector base + $C0 IIC0 bus I bit IBCR0 (IBIE) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 82 CAN4RIER (RXFIE) Vector base + $90 CAN4 transmit I bit CAN4TIER (TXEIE[2:0]) Vector base + $8E Port P Interrupt I bit PIEP (PIEP7-PIEP0) Vector base+ $8C PWM emergency shutdown I bit PWMSDN (PWMIE) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 83 Vector base + $52 TIM timer channel 1 I bit TIE (C1I) Vector base + $50 TIM timer channel 2 I bit TIE (C2I) Vector base+ $4E TIM timer channel 3 I bit TIE (C3I) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 84 D-Flash EEE partition. Completion of this phase is indicated by the CCIF ﬂag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 85 If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset. Table 1-15. Initial COP Rate Conﬁguration NV[2:0] in CR[2:0] in FOPT Register COPCTL Register Table 1-16. Initial WCOP Conﬁguration NV[3] in WCOP in FOPT Register COPCTL Register MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 86 ETRIG3 Periodic interrupt timer hardware trigger 1 Consult the ADC block description for information about the analog-to-digital converter module. ADC block description refererences to freeze mode are equivalent to active BDM mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 87 Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does not support access abort of reserved VREG register space. 1.11 S12XEPIM Conﬁguration On smaller derivatives the S12XEPIM module is a subset of the S12XEP100. The registers of the unavailable ports are unimplemented. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 88 =1MΩ ; R speciﬁed by crystal vendor SSPLL Figure 1-11. Full Swing Pierce Oscillator Connections (XCLKS = 0) CMOS-Compatible EXTAL External Oscillator XTAL Not Connected Figure 1-12. External Clock Connections (XCLKS = 0) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 89: Chapter 2 Port Integration Module (S12Xep100Pimv1)
Port AD0 and AD1 associated with two 16-channel ATD modules • Port R associated with 1 stardard timer (TIM) module • Port L associated with 4 SCI modules • Port F associated with IIC, SCI and chip select outputs MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 90 Open drain for wired-or connections • Interrupt inputs with glitch filtering • Reduced input threshold to support low voltage applications External Signal Description This section lists and describes the signals that do connect off-chip. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 91 I/O High-order bidirectional data input/output Mode Conﬁgurable for reduced input threshold dependent GPIO I/O General-purpose I/O PD[7:0] DATA[7:0] I/O Low-order bidirectional data input/output Mode Conﬁgurable for reduced input threshold dependent GPIO I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 92 O Extended external bus address output (multiplexed with access master output) ACC[2:0] GPIO I/O General-purpose I/O PK[3:0] ADDR[19:16] O Extended external bus address output (multiplexed with instruction pipe status bits) IQSTAT[3:0] GPIO I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 93 Serial Communication Interface 1 receive pin GPIO I/O General-purpose I/O TXD0 O Serial Communication Interface 0 transmit pin GPIO I/O General-purpose I/O RXD0 Serial Communication Interface 0 receive pin GPIO I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 94 MSCAN0 receive pin (MISO0) I/O Serial Peripheral Interface 0 master in/slave out pin GPIO I/O General-purpose I/O TXCAN0 O MSCAN0 transmit pin GPIO I/O General-purpose I/O RXCAN0 MSCAN0 receive pin GPIO I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 95 I/O General-purpose I/O with interrupt PWM0 O Pulse Width Modulator output channel 0 MISO1 I/O Serial Peripheral Interface 1 master in/slave out pin (TIMIOC0) I/O Timer Channel 0 input/output GPIO/KWP0 I/O General-purpose I/O with interrupt MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 96 O Serial Communication Interface 6 transmit pin GPIO/KWH1 I/O General-purpose I/O with interrupt (MISO1) I/O Serial Peripheral Interface 1 master in/slave out pin TXD6 O Serial Communication Interface 6 transmit pin GPIO/KWH0 I/O General-purpose I/O with interrupt MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 97 I/O General-purpose I/O GPIO AN[15:0] ATD0 analog inputs AD1 PAD[31:16] GPIO I/O General-purpose I/O GPIO AN[15:0] ATD1 analog inputs PR[7:0] TIMIOC[7:0] I/O Timer Channels 7- 0 input/output GPIO GPIO I/O General-purpose I/O MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 98 3. Only available in emulation modes or in Special Test Mode with IVIS on. 4. Refer to S12X_EBI section. Memory Map and Register Deﬁnition This section provides a detailed description of all Port Integration Module registers. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 99 DDRE3 DDRE2 DDRE 0x000A 0x000B Non-PIM Non-PIM Address Range Address Range 0x000C PUPKE BKPUE PUPEE PUPDE PUPCE PUPBE PUPAE PUCR 0x000D RDPK RDPE RDPD RDPC RDPB RDPA RDRIV = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 100 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 PTIT 0x0242 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 DDRT 0x0243 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 RDRT = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 101 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 0x0251 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 PTIM 0x0252 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 DDRM = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 102 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 0x0261 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 PTIH 0x0262 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 DDRH = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 103 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 PIFJ 0x0270 PT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00 PT0AD0 0x0271 PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 PT1AD0 = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 104 0x027E PER0AD17 PER0AD16 PER0AD15 PER0AD14 PER0AD13 PER0AD12 PER0AD1‘ PER0AD10 PER0AD1 0x027F PER1AD17 PER1AD16 PER1AD15 PER1AD14 PER1AD13 PER1AD12 PER1AD11 PER1AD10 PER1AD1 0x0280– 0x0267 Non-PIM Non-PIM Address Range Address Range = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 105 PERL0 PERL 0x0375 PPSL7 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0 PPSL 0x0376 WOML7 WOML6 WOML5 WOML4 WOML3 WOML2 WOML1 WOML0 WOML 0x0377 PTLRR7 PTLRR6 PTLRR5 PTLRR4 PTLRR = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 106 The conﬁguration bit PS is used for two purposes: 1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 107 1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1. 2. Applicable only on Port P, H, and J. NOTE All register bits in this module are completely synchronous to internal clocks during a register read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 108 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 109 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 110 When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 111 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 112 When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as high-impedance input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 113 This pin can be used as general purpose and IRQ input. Port E general purpose input data and interrupt—Data Register, XIRQ input. This pin can be used as general purpose and XIRQ input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 114 PUPAE Reset = Unimplemented or Reserved Figure 2-11. S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) 1. Read:Anytime in single-chip modes. Write:Anytime, except BKPUE which is writable in Special Test Mode only. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 115 This bit conﬁgures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 116 This bit conﬁgures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 117 Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 2. Reset values in emulation modes are identical to those of the target mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 118 11111 ECLK rate = Bus Clock rate divided by 32 2.3.16 PIM Reserved Register Address 0x001D (PRR) Access: User read Reset = Unimplemented or Reserved Figure 2-14. PIM Reserved Register 1. Read: Always reads 0x00 Write: Unimplemented MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 119 Access: User read Reset = Unimplemented or Reserved Figure 2-16. PIM Reserved Register 1. Read: Always reads 0x00 Write: Unimplemented NOTE Writing to this register when in special modes can alter the pin functionality. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 120 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 121 When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 122 The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer Input Capture always monitors the state of the pin. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as high-impedance input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 123 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 124 1. Read: Always reads 0x00 Write: Unimplemented 2.3.28 PIM Reserved Register Address 0x0247 Access: User read Reset = Unimplemented or Reserved Figure 2-26. PIM Reserved Register 1. Read: Always reads 0x00 Write: Unimplemented MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 125 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 126 Port S Data Direction Register (DDRS) Address 0x024A Access: User read/write DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 Reset Figure 2-29. Port S Data Direction Register (DDRS) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 127 This register conﬁgures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 128 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 129 0 Output buffers operate as push-pull outputs. 2.3.36 PIM Reserved Register Address 0x024F Access: User read Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-34. PIM Reserved Register 1. Read: Always reads 0x00 Write: Unimplemented MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 130 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 131 Port M Input Register (PTIM) Address 0x0251 Access: User read PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-36. Port M Input Register (PTIM) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 132 The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 133 0 Associated pin is conﬁgured as input. NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 134 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input or wired-or output. This bit has no effect if the pin is used as push-pull output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 135 “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no inﬂuence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 136 This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 2-40. Module Routing Summary Module MODRR Related Pins RXCAN TXCAN CAN0 CAN4 Reserved MISO MOSI SPI0 SPI1 SPI2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 137 When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 138 PTIP3 PTIP2 PTIP1 PTIP0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-44. Port P Input Register (PTIP) 1. Read: Anytime. Write:Never, writes to this register have no effect. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 139 0 Associated pin is conﬁgured as input. NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 140 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 141 Port P interrupt enable— PIEP This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt ﬂag masked). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 142 PTH2 PTH1 PTH0 Altern. SCK2 MOSI2 MISO2 SCK1 MOSI1 MISO1 Function TXD5 RXD5 TXD4 RXD4 TXD7 RXD7 TXD6 RXD6 Reset Figure 2-51. Port H Data Register (PTH) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 143 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 144 2.3.55 Port H Data Direction Register (DDRH) Address 0x0262 Access: User read/write DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 Reset Figure 2-53. Port H Data Direction Register (DDRH) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 145 In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 146 This register conﬁgures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 147 0 A falling edge on the associated Port H pin sets the associated ﬂag bit in the PIFH register.A pull-up device is connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 148 PPSH register. To clear this ﬂag, write logic level 1 to the corresponding bit in the PIFH register. Writing a 0 has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 No active edge pending. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 149 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 150 2.3.63 Port J Data Direction Register (DDRJ) Address 0x026A Access: User read/write DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 Reset Figure 2-61. Port J Data Direction Register (DDRJ) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 151 The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 152 This register conﬁgures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 153 0 A falling edge on the associated Port J pin sets the associated ﬂag bit in the PIFJ register.A pull-up device is connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 154 PPSJ register. To clear this ﬂag, write logic level 1 to the corresponding bit in the PIFJ register. Writing a 0 has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 No active edge pending. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 155 When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 156 Port AD0 Data Direction Register 1 (DDR1AD0) Address 0x0273 Access: User read/write DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 Reset Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 157 This register conﬁgures the drive strength of Port AD0 output pins 15 through 8 as either full or reduce. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 158 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 159 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 160 Field Description Port AD1 data direction— DDR0AD1 This register controls the data direction of pins 15 through 8. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 161 PT0AD1 registers, when changing the DDR1AD1 register. NOTE To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 162 This register conﬁgures the drive strength of Port AD1 output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 163 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 164 Port R input data— PTIR This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 165 Port R Reduced Drive Register (RDRR) Address 0x036B Access: User read/write RDRR7 RDRR6 RDRR5 RDRR4 RDRR3 RDRR2 RDRR1 RDRR0 Reset Figure 2-86. Port R Reduced Drive Register (RDRR) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 166 Port R Polarity Select Register (PPSR) Address 0x036D Access: User read/write PPSR7 PPSR6 PPSR5 PPSR4 PPSR3 PPSR2 PPSR1 PPSR0 Reset Figure 2-88. Port R Polarity Select Register (PPSR) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 167 0 TIMIOC7 is available on PR7 Port R routing— PTRRR This register conﬁgures the re-routing of the associated TIM channel. 1 TIMIOC6 is available on PP6 0 TIMIOC6 is available on PR6 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 168 Access: User read/write PTL7 PTLT6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0 Altern. (TXD7) (RXD7) (TXD6) (RXD6) (TXD5) (RXD5) (TXD4) (RXD4) Function Reset Figure 2-91. Port L Data Register (PTL) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 169 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 170 The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 171 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 172 “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no inﬂuence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 173 Access: User read/write PTF7 PTFT6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Altern. (TXD3) (RXD3) (SCL0) (SDA0) (CS3) (CS2) (CS1) (CS0) Function Reset Figure 2-99. Port F Data Register (PTF) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 174 When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 175 The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 176 These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 177 2.3.108 Port F Routing Register (PTFRR) Address 0x037F Access: User read/write PTFRR5 PTFRR4 PTFRR3 PTFRR2 PTFRR1 PTFRR0 Reset = Unimplemented or Reserved Figure 2-106. Port F Routing Register (PTFRR) 1. Read: Anytime. Write: Anytime. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 178 2-103). All registers can be written at any time, however a speciﬁc conﬁguration might not become active. Example 2-1. Selecting a pull-up device This device does not become active while the port is used as a push-pull output. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 179 This register deﬁnes whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-107). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 180 If the pin is used as an output this register turns off the active high drive. This allows wired-or type connections of outputs. 2.4.2.8 Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt ﬂag to enable/disable the interrupt. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 181 Port E pin PE[7] can be used for either general-purpose I/O or as the free-running clock ECLKX2 output running at the Core Clock rate. The clock output is always enabled in emulation modes. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 182 Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem. Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 183 Port J pins PJ[7:6] can be used for either general purpose I/O, or with the CAN4, IIC0 or CAN0 subsystems. Port J pins PJ[5:4] can be used for either general purpose I/O, or with the IIC1 subsystem or as chip select outputs. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 184 Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem. Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 185 ≥ 4 ≥ t Valid bus clocks pulse pulse pval 1. These values include the spread of the oscillator frequency over temper- ature, voltage and process. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 186 It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 187: Chapter 3 Memory Mapping Control (S12Xmmcv4)
The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses, including internal memories and peripherals, are controlled in this module. The local address space for each master is translated to a global memory space. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 188 Non-volatile Memory; Flash EEPROM or ROM 3.1.2 Features The main features of this block are: • Paging capability to support a global 8 Mbytes memory address space • Bus arbitration between the masters CPU, BDM and XGATE MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 189 MMC is inactive during stop mode. 3.1.4.2 Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. 1. Resources are also called targets. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 190 It also provides a brief description of their operation. 1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 191 Table 3-4. External Output Signals Associated with the MMC Available in Modes Signal Description Chip select line 0 (see Table 3-5) Chip select line 1 Chip select line 2 Chip select line 3 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 192 TGMRAMON EEEIFRON PGMIFRON RAMHM EROMON ROMHM ROMON 0x0014 Reserved 0x0015 PPAGE PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0x0016 RPAGE 0x0017 EPAGE = Unimplemented or Reserved Figure 3-2. MMC Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 193 Control of different external stretch mechanism. For more detail refer to the S12X_EBI BlockGuide. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 194 3. When the internal NVM is enabled (see ROMON in Section 3.3.2.5, “MMC Control Register (MMCCTL1)) the CS0 is not asserted in the space occupied by this on-chip memory block. 4. External PPAGE accesses in (NX, EX) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 195 It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value corresponding to normal single chip mode while the device is in emulation single-chip mode or a value corresponding to normal expanded mode while the device is in emulation expanded mode). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 196 RESET Transition done by write access to the MODE register Illegal (MODC, MODB, MODA) pin values. Do not use. (Reserved for future use). Figure 3-5. Mode Transition Diagram when MCU is Unsecured MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 197 Example 3-1. This example demonstrates usage of the GPAGE register #0x5000 ;Set GPAGE offset to the value of 0x5000 MOVB #0x14, GPAGE ;Initialize GPAGE register with the value of 0x14 GLDAA ;Load Accu A from the global address 0x14_5000 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 198 ;Global data accesses to the range 0xXX_80XX can be direct. ;Logical data accesses to the range 0x80XX are direct. <00 ;Load the Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 199 Write: Once in normal and emulation modes and anytime in special modes 0 Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external access). 1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 200 RAM, EEPROM and register space are always considered internal). External application means resources residing outside the MCU are read/written. 2. The external access stretch mechanism is part of the EBI module (refer to EBI Block Guide for details). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 201 Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM PIX[7:0] array pages is to be accessed in the Program Page Window. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 202 Figure 3-14. RPAGE Address Mapping NOTE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RPAGE = 0x00. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 203 EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map format. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 204 The active background debug mode is in control of the CPU code execution and the BDM ﬁrmware is waiting for serial commands sent through the BKGD pin. There is no external bus in this mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 205 Please note that after the MCU enters active BDM mode the BDM ﬁrmware lookup tables and the BDM registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0xFF. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 206 253 *16K paged 16K FLASH Reset Vectors 0xFFFF 0x7F_4000 16K FLASH (PPAGE 0xFD) 0x7F_8000 16K FLASH (PPAGE 0xFE) 0x7F_C000 16K FLASH (PPAGE 0xFF) 0x7F_FFFF Figure 3-17. Expansion of the Local Address Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 207 EPAGE allows accessing up to 256 Kbytes of EEPROM in the system by using the eight EPAGE index bits to page 1 Kbyte blocks into the EEPROM page window located in the local CPU memory space from address 0x0800 to address 0x0BFF. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 208 The generated global address is a result of concatenation of the BDM local address with the BDMGPR register [22:16] in the case of a hardware command or concatenation of the CPU local address and the BDMGPR register [22:16] in the case of a ﬁrmware command (see Figure 3-18). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 209 When the device is operating in expanded modes except emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip resources (unimplemented areas or external memory space) result in accesses to the external bus (see Figure 3-19). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 210 The non-internal resources (unimplemented areas or external space) are used to generate the chip selects (CS0,CS1,CS2 and CS3) (see Figure 3-19), which are only active in normal expanded, emulation expanded (see Section 3.3.2.1, “MMC Control Register (MMCCTL0)). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 211 Unpaged 16K FLASH 0x1F_FFFF External Space 0x8000 16K FLASH window PPAGE 0x3F_FFFF 0xC000 Unimplemented FLASH Unpaged 16K FLASH FLASH_LOW Reset Vectors 0xFFFF FLASH 0x7F_FFFF Figure 3-19. S12XE CPU & BDM Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 212 Bottom address: 0x78_0800 Top address: 0x78_7FFF The gap range in the local memory map 0x8000–0xBFFF will be translated in the global address space: 0x0F_8000 - 0x0F_BFFF (illegal xgate access to system RAM). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 213 Chapter 3 Memory Mapping Control (S12XMMCV4) XGATE Global Memory Map Local Memory Map 0x00_0000 Registers 0x00_07FF 0x0000 Registers XGRAM_LOW 0x0800 0x0F_FFFF FLASH 0x7FFF Unimplemented area 0x78_0800 FLASH 0x78_7FFF 0xFFFF 0x7F_FFFF Figure 3-20. XGATE Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 214 RPAGE = 0xFD 24 Kilobytes 0x0F_A000 - 0x0F_FFFF (Reset value) (0x00 <= RPAGE <= 0xF9) 28 Kilobytes 0x00_0000 - 0x0F_9FFF Normal Operation (0xFA <= RPAGE <= 0xFF) 24 Kilobytes 0x0F_A000 - 0x0F_FFFF MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 215 0xC000 FLASH Unpaged 253 *16K paged 16K FLASH Reset Vectors 0xFFFF ROMHM RAMHM 0x7F_4000 16K FLASH 0x7F_8000 16K FLASH (PPAGE 0xFE) 0x7F_C000 16K FLASH (PPAGE 0xFF) 0x7F_FFFF Figure 3-21. ROMHM, RAMHM Memory Conﬁguration MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 216 RAM Area 0x0F_FFFF 0x0F_A000 EEPROM Area 8K RAM 0x0F_C000 0x13_FFFF 16K RAM 0x0F_E000 External 8K RAM Space Area 0x0F_FFFF 0x0F_FFFF 0x3F_FFFF FLASH Area 0x7F_FFFF Figure 3-22. S12XE System RAM in the Memory Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 217 All internal and external resources are connected to speciﬁc target buses (see Figure 3-23 1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 218 CALL and RTC Instructions CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 219 RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the RTC instruction must be called using the CALL instruction even when the correct page is already present MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 220 A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the misaligned word access is not a PRR, the access will take only 3 cycles. • A byte access to a PRR will take 2 cycles. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 221 FLASH provides the data and all internal actions are made visible to the emulator. 3.5.3.1 ROM Control in Single-Chip Modes In single-chip modes the MCU has no external bus. All memory accesses and program fetches are internal (see Figure 3-24). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 222 In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set, the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the data (see Figure 3-26). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 223 Chapter 3 Memory Mapping Control (S12XMMCV4) Application Memory Flash ROMON = 1 Application Memory ROMON = 0 Figure 3-26. ROM in Normal Expanded Mode MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 224 CPU internal actions (see Figure 3-28). Observer Emulator Flash Application Memory EROMON = 1 Generator Emulator Flash Application Memory EROMON = 0 Figure 3-27. ROMON = 1 in Emulation Expanded Mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 225 In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal FLASH provides the data, otherwise the application memory provides the data (see Figure 3-29). Application Memory ROMON = 0 Application Memory Flash ROMON = 1 Figure 3-29. ROM in Special Test Mode MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 226 Chapter 3 Memory Mapping Control (S12XMMCV4) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 227: Chapter 4 Memory Protection Unit (S12Xmpuv1)
The MPU module monitors the bus activity of each bus master. The data describing each access is fed into multiple address range comparators. The output of the comparators is used to determine if a particular MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 228 — each descriptor has a granularity of 8 Bytes 1. Master 3 can be implemented or left out depending the chip conﬁguration. Please refer to the Device Reference Manual for information about the availability and function of Master 3. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 229 The MPU module can be used in all MCU modes. External Signal Description The MPU module has no external signals. Memory Map and Register Deﬁnition This section provides a detailed description of address space and registers used by the MPU module. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 230 MPUDESC4 0x000B HIGH_ADDR[10:3] MPUDESC5 = Unimplemented or Reserved 1. The module addresses 0x0006−0x000B represent a window in the register map through which different descriptor registers are visible. Figure 4-2. MPU Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 231 AEF bit is set. Also, the non-maskable hardware interrupt for violating accesses coming from the S12X CPU is generated regardless of the state of the AEF bit. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 232 Access violation address bits — The ADDR[15:8] bits contain bits [15:8] of the global address which caused ADDR[15:8] the current access violation interrupt. These bits are undeﬁned if the access error ﬂag bit (AEF) in the MPUFLG register is not set. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 233 0 MPU is disabled for the CPU in supervisor state 1 MPU is enabled for the CPU in supervisor state 2–0 Descriptor select bits — The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register SEL[2:0] window (MPUDESC0—MPUDESC5). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 234 Master select bits to one. Setting all Master select bits of a descriptor to zero disables the descriptor. 4.3.1.7 MPU Descriptor Register 1 (MPUDESC1) Address: Module Base + 0x0007 LOW_ADDR[18:11] Reset Figure 4-9. MPU Descriptor Register 1 (MPUDESC1) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 235 Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this bit is set every attempt to write in the described memory range causes an access violation. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 236 Memory range upper boundary address bits — The HIGH_ADDR[10:3] bits represent bits [10:3] of the HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range. 10:3] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 237 [22:3] of each access. The lower address bits [2:0] are ignored. NOTE A mis-aligned word access to the upper boundary address of a descriptor is always ﬂagged as an access violation. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 238 Therefore this will result in an access violation if the op-code pre-fetch accesses a memory range marked as “No-Execute” (NEX=1). This must be taken into account when deﬁning memory MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 239 Initialize peripherals and other masters for use (i.e. set-up XGATE, Master3 if applicable). • Enable the MPU protection for the S12X CPU in supervisor state, if desired. • Switch the S12X CPU to user state, if desired. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 240 Chapter 4 Memory Protection Unit (S12XMPUV1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 241: Chapter 5 External Bus Interface (S12Xebiv4)
Dependent on the mode, the external bus can be used for data exchange with external memory, peripherals or PRU, and provide visibility to the internal bus externally in combination with an emulator. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 242 Address, data, and control signals are activated on the external bus in normal expanded mode and special test mode. • Emulation modes The external bus is activated to interface to an external tool for emulation of normal expanded mode or normal single-chip mode applications. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 243 Table 5-2 outlines the pin names and gives a brief description of their function. Refer to the SoC section and PIM section for reset states of these pins and associated pull-ups or pull-downs. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 244 (in modes where applicable). 3. Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin depending on conﬁguration and reset state. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 245 Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes, the data is read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 246 1. EWAIT function is enabled if at least one CSx line is conﬁgured respectively in MMCCTL0. Refer to S12X_MMC section and Table 5-6. Table 5-5. External Address Bus Size ASIZ[4:0] Available External Address Lines 00000 None 00001 00010 ADDR1, UDS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 247 If conﬁgured respectively, stretch cycles are added as programmed or dependent on EWAIT in normal expanded mode and emulation expanded mode; function not available in all other operating modes. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 248 Max. of 2 to 9 1 cycle Max. of 2 to 9 1 cycle address access programmed programmed cycles cycles unimplemented area or n cycles of or n cycles of access ext. wait ext. wait MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 249 External read data are also visible on IVDx. During ‘no access’ cycles RW is held in read position while LSTRB is undetermined. All accesses which make use of the external bus interface are considered external accesses. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 250 (for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL (0x0000) from the third until one cycle after the access to indicate continuation. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 251 ADDR[22:20] / ACC[2:0] acc 0 acc 1 ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 0 0000 addr 1 0000 ADDR[15:0] / IVD[15:0] ivd 0 DATA[15:0] (internal read) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 252 0 0000 addr 1 0000 ADDR[15:0] / IVD[15:0] DATA[15:0] (write) data 0 5.4.2.4.3 Read-Write-Read Access Timing Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle) Access #0 Access #1 Access #2 Bus cycle -> MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 253 Read data are not captured by the system in normal expanded mode until the specified setup time before the RE rising edge. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 254 In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 255 Byte read of data on DATA[7:0] at an odd address data(odd) Byte read of data on DATA[15:8] at an even address data(even) Word read at an odd and odd+1 internal RAM address data(odd+1) data(odd) (misaligned - only in emulation modes) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 256 This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 257 2 cycles. Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 258 Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’ Timing considerations: • Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing. • LSTRB has the same timing as RW. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 259 • Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’ • Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’ The associated timing numbers are given in MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 260 2 and 3 additional stretch cycles) Timing considerations: • If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 261: Chapter 6 Interrupt (S12Xintv2)
XGATE module can be nested one level deep. NOTE The HPRIO register and functionality of the original S12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 262 1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). 2. The IRQ interrupt can only be handled by the CPU MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 263 • Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 6.3.2.1, “Interrupt Vector Base Register (IVBR)” for details. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 264 INT_XGPRIO = XGATE Interrupt Priority IVBR = Interrupt Vector Base = Interrupt Processing Level Figure 6-1. XINT Block Diagram External Signal Description The XINT module has no external signals. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 265 0x012C Interrupt Request Conﬁguration Data Register 4 (INT_CFDATA4) 0x012D Interrupt Request Conﬁguration Data Register 5 (INT_CFDATA5) 0x012E Interrupt Request Conﬁguration Data Register 6 (INT_CFDATA6) 0x012F Interrupt Request Conﬁguration Data Register 7 (INT_CFDATA7) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 266 0x012B INT_CFDATA3 R RQST PRIOLVL[2:0] 0x012C INT_CFDATA4 R RQST PRIOLVL[2:0] 0x012D INT_CFDATA5 R RQST PRIOLVL[2:0] 0x012E INT_CFDATA6 R RQST PRIOLVL[2:0] 0x012F INT_CFDATA7 R RQST PRIOLVL[2:0] = Unimplemented or Reserved Figure 6-2. XINT Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 267 XGATE module. Out of reset the priority is set to the lowest active level (“1”). Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 268 (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt conﬁguration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt conﬁguration data register of the vector with the highest address, respectively. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 269 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012B RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 6-9. Interrupt Request Conﬁguration Data Register 3 (INT_CFDATA3) 1. Please refer to the notes following the PRIOLVL[2:0] description below. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 270 Address: 0x012F RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 6-13. Interrupt Request Conﬁguration Data Register 7 (INT_CFDATA7) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 271 The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 272 IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is conﬁgured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 273 If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 274 1. 16 bits vector address based 2. only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor 3. only implemented if device features a Memory Protection Unit (MPU) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 275 Service interrupt, e.g., clear interrupt ﬂags, copy data, etc. • Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 276 Interrupt request channels which are conﬁgured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 277: Chapter 7 Background Debug Module (S12Xbdmv2)
• Enhanced capability for allowing more ﬂexibility in clock rates • SYNC command to determine communication rate • GO_UNTIL command • Hardware handshake protocol to increase the performance of the serial communication MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 278 If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or EEPROM) other than allowing erasure. For more information please see Section 7.4.1, “Security”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 279 BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 280 0x7FFF05 Reserved 0x7FFF06 BDMCCRL R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 7-2. BDM Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 281 3. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). Figure 7-3. BDM Status Register (BDMSTS) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 282 ﬁrst recognized. It will stay set until BDM ﬁrmware is exited by one of the following BDM commands: GO or GO_UNTIL. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 283 Table 7-4. BDM Clock Sources PLLSEL CLKSW BDMCLK Bus clock dependent on oscillator Bus clock dependent on oscillator Alternate clock (refer to the device speciﬁcation to determine the alternate clock source) Bus clock dependent on the PLL MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 284 When entering background debug mode, the BDM CCR HIGH holding register is used to save the high byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be written to modify the CCR value. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 285 Section 7.4.3, “BDM Hardware Commands”) and in secure mode (see Section 7.4.1, “Security”). Firmware commands can only be executed when the system is not secure and is in active background debug mode (BDM). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 286 BDM. However, these registers are not readable by user programs. 1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is provided by the S12X_DBG module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 287 Must be aligned access. WRITE_BYTE 16-bit address Write to memory with standard BDM ﬁrmware lookup table out of map. 16-bit data in Odd address data on low byte; even address data on high byte. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 288 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are received. The ﬁrmware commands are shown in Table 7-7. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 289 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least signiﬁcant bit of the address and will assume an even address from the remaining bits. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 290 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 7.4.6, “BDM Serial Interface” Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 291 The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 292 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 293 High-Impedance High-Impedance Perceived Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 1) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 294 ACK pulse, since the command execution depends upon the CPU bus frequency, which in some cases could be very slow MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 295 READ_BYTE Byte Address Retrieved Command Host Target Host Target BDM Issues the ACK Pulse (out of scale) BDM Executes the BDM Decodes READ_BYTE Command the Command Figure 7-12. Handshake Protocol at Command Level MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 296 When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 297 ACK pulse and the SYNC request pulse. This conﬂict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 298 BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 7.4.3, “BDM Hardware Commands” Section 7.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 299 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 300 All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 301 The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 302 Chapter 7 Background Debug Module (S12XBDMV2) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 303: Chapter 8 S12X Debug (S12Xdbgv3) Module
Change in the program ﬂow due to a conditional branch, indexed jump or interrupt Background Debug Mode Device User Guide, describing the features of the device into which the DBG is integrated MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 304 — Force — This triggers on the ﬁrst instruction boundary after a match occurs. • The following types of breakpoints — CPU12X breakpoint entering BDM on breakpoint (BDM) — CPU12X breakpoint executing SWI on breakpoint (SWI) — XGATE breakpoint MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 305 Table 8-3. Mode Dependent Restriction Summary Comparator Breakpoints Tagging Tracing Enable Active Secure Matches Enabled Possible Possible Possible Only SWI Active BDM not possible when not enabled XGATE only XGATE only XGATE only XGATE only MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 306 Module Memory Map A summary of the registers associated with the S12XDBG sub-block is shown in Table 8-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 307 This represents the contents if the Comparator A or C control register is blended into this address. This represents the contents if the Comparator B or D control register is blended into this address Figure 8-2. Quick Reference to S12XDBG Registers MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 308 TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect. 0 Do not trigger until the state sequencer enters the Final State. 1 Trigger immediately . MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 309 XGATE breakpoint generated CPU12X breakpoint generated Breakpoints generated for CPU12X and XGATE Table 8-7. COMRV Encoding COMRV Visible Comparator Visible Register at 0x0027 Comparator A DBGSCR1 Comparator B DBGSCR2 Comparator C DBGSCR3 Comparator D DBGMFR MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 310 SSF[2:0] = 001. See Table 8-9 Table 8-9. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State 101,110,111 Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 311 1,(2) Both CPU12X and XGATE 1. No range limitations are allowed. Thus tracing operates as if TRANGE = 00. 2. No Detail Mode tracing supported. If TRCMOD = 10, no information is stored. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 312 C and D Comparator Match Control — These bits determine the C and D comparator match mapping as CDCM[1:0] described in Table 8-16. 1–0 A and B Comparator Match Control — These bits determine the A and B comparator match mapping as ABCM[1:0] described in Table 8-17. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 313 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. The POR state is undeﬁned Other resets do not affect the trace buffer contents. . MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 314 ARM bit will be cleared and the tracing session ends. 0000010 64 lines valid, oldest data has been overwritten by most recent data 1111110 1. This applies to Normal/Loop1/PurePC Modes when tracing from either CPU12X or XGATE only. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 315 Table 8-23. State1 Sequencer Next State Selection SC[3:0] Description 0000 Any match triggers to state2 0001 Any match triggers to state3 0010 Any match triggers to Final State 0011 Match2 triggers to State2..Other matches have no effect MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 316 These bits select the targeted next state whilst in State2, based upon the match event. SC[3:0] Table 8-25. State2 —Sequencer Next State Selection SC[3:0] Description 0000 Any match triggers to state1 0001 Any match triggers to state3 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 317 DBGXCTL control register. Table 8-26. DBGSCR3 Field Descriptions Field Description 3–0 These bits select the targeted next state whilst in State3, based upon the match event. SC[3:0] MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 318 A set ﬂag does not inhibit the setting of other ﬂags. Once a ﬂag is set, further triggers on the same channel have no affect. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 319 Figure 8-13. Debug Comparator Control Register (Comparators A and C) Address: 0x0028 COMPE Reset Figure 8-14. Debug Comparator Control Register (Comparators B and D) Read: Anytime. See Table 8-29 for visible register encoding. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 320 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not used for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 321 [22:16] to a logic one or logic zero. This register byte is ignored for XGATE compares. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 322 [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 323 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 324 1 Compare corresponding data bit Functional Description This section provides a complete functional description of the S12XDBG module. If the part is in secure mode, the S12XDBG module can generate breakpoints but tracing is not possible. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 325 If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 326 To detect an access of ADDR[n+1] through a word access of ADDR[n] the comparator can be configured to ADDR[n], DBGxDL is loaded with the data pattern and DBGxDHM is cleared so only the data[n+1] is compared on accesses of ADDR[n]. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 327 Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 328 This can be avoided by setting the upper or lower range limit to $7FFFFF or $000000 respectively. Interrupt vector fetches do not cause taghits MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 329 Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. If conﬁgured for begin or mid aligned tracing, MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 330 The state sequencer allows a deﬁned sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register, MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 331 DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active but tracing of XGATE activity is still possible. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 332 COF addresses are deﬁned as follows for the CPU12X: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 333 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 The execution ﬂow taking into account the IRQ is as follows #SUB_1 MARK1 IRQ_ISR LDAB #$F0 STAB VAR_C1 SUB_1 ADDR1 DBNE A,PART5 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 334 The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst tracing from XGATE or CPU12X only, in Normal or Loop1 modes each array line contains MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 335 XPCM1 XPCL1 XINF0 XPCM0 XPCL0 XGATE Other Modes XINF3 XPCM3 XPCL3 XINF2 XPCM2 XPCL2 CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0 CPU12X Other Modes CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 336 Figure 8-24. XGATE info bit setting Figure 8-24 indicates the XGATE information bit setting when switching between threads, the initial thread starting at SOT1 and continuing at COT1 after the higher priority thread2 has ended. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 337 CPU12X Free Cycle Indicator — This bit indicates if the stored CPU12X address corresponds to a free cycle. CFREE This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 338 The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 339 Thus these bits are ignored if tagged triggering is selected. When conﬁgured for range comparisons and tagging, the ranges are accurate only to word boundaries. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 340 From taghits generated using the external TAGHI and TAGLO pins. Breakpoints generated by the XGATE module or via the BDM BACKGROUND command have no affect on the CPU12X in STOP or WAIT mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 341 Store a further 32 Trace Buffer line entries after trigger Request breakpoint after the 32 further Trace Buffer entries 00,01,10 Terminate tracing and generate breakpoint immediately on trigger 00,01,10 Terminate tracing immediately on trigger Reserved MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 342 BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 343 An XGATE software breakpoint is forced immediately, the tracing session terminated and the XGATE module execution stops. The user can thus determine if an XGATE breakpoint has occurred by reading out the XGATE program counter over the BDM interface. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 344 Chapter 8 S12X Debug (S12XDBGV3) Module MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 345: Chapter 9 Security (S12Xe9Secv2)
Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) • Disable access to internal Flash/EEPROM in expanded modes • Disable debugging features for the CPU and XGATE MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 346 Figure 9-1. Flash Options/Security Byte The meaning of the bits KEYEN[1:0] is shown in Table 9-3. Please refer to Section 9.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 347 Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. • Tracing code execution using the DBG module is disabled. • Debugging XGATE code (breakpoints, single-stepping) is disabled. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 348 In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 349 Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 350 Chapter 9 Security (S12XE9SECV2) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 351: Chapter 10 Xgate (S12Xgatev3)
10-1). Each XGATE request attempts to activate a XGATE channel at a certain priority level. XGATE Channel The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request Vector, Interrupt Flag) which are associated with a particular XGATE Request. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 352 An 8 bit entity. 10.1.2 Features The XGATE module includes these features: • Data movement between various targets (i.e. Flash, RAM, and peripheral modules) • Data manipulation through built in RISC core MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 353 XGATE. Peripheral Interrupts S12X_INT XGATE Interrupt Flags Semaphores RISC Core Software Triggers Software Triggers Interrupt Software Error Logic S12X_DBG Peripherals S12X_MMC Figure 10-1. XGATE Block Diagram MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 354 XGCHID[6:0] XGCHID 0x0003 XGCHPL[2:0] XGCHPL 0x0004 Reserved 0x0005 XGISPSEL[1:0] XGISPSEL 0x0006 XGISP74[15:1] XGISP74 0x0006 XGISP31[15:1] XGISP31 0x0006 XGVBR[15:1] XGVBR = Unimplemented or Reserved Figure 10-2. XGATE Register Summary (Sheet 1 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 355 XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 XGIF 0x0016 XGIF_0F XGIF_0E XGIF_0D XGIF = Unimplemented or Reserved Figure 10-2. XGATE Register Summary (Sheet 2 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 356 XGR1 0x0024 XGR2 XGR2 0x0026 XGR3 XGR3 0x0028 XGR4 XGR4 0x002A XGR5 XGR5 0x002C XGR6 XGR6 0x002E XGR7 XGR7 = Unimplemented or Reserved Figure 10-2. XGATE Register Summary (Sheet 3 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 357 Read: This bit will always read "0". Write: 0 Disable write access to the XGSS in the same bus cycle 1 Enable write access to the XGSS in the same bus cycle MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 358 0 RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 359 This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads. Refer to Section 10.6.1, “Debug Features” for further information. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 360 The XGATE Initial Stack Pointer Select Register (Figure 10-6) determines the register which is mapped to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting 1. Refer to Section 10.6.1, “Debug Features” MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 361 = Unimplemented or Reserved Figure 10-7. XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74) Read: Anytime Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00)) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 362 Module Base +0x0006 XGVBR[15:1] Reset = Unimplemented or Reserved Figure 10-9. XGATE Vector Base Address Register (XGVBR) Read: Anytime Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00)) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 363 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 Reset XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 Reset Figure 10-10. XGATE Channel Interrupt Flag Vector (XGIF) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 364 Unimplemented interrupt ﬂags will always read "0". Section “Interrupts” of the device overview for a list of implemented Interrupts. Read: 0 Channel interrupt is not pending 1 Channel interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the interrupt ﬂag MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 365 Refer to Section 10.5.2, “Outgoing Interrupt Requests” further information. Module Base +0x00018 XGSWT[7:0] XGSWTM[7:0] Reset Figure 10-11. XGATE Software Trigger Register (XGSWT) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 366 The S12X_CPU has access to the semaphores through the XGATE Semaphore Register (Figure 10-12). Refer to section Section 10.4.4, “Semaphores” for details. Module Base +0x0001A XGSEM[7:0] XGSEMM[7:0] Reset Figure 10-12. XGATE Semaphore Register (XGSEM) Read: Anytime Write: Anytime (see Section 10.4.4, “Semaphores”) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 367 Sign Flag — The RISC core’s Sign ﬂag Zero Flag — The RISC core’s Zero ﬂag Overﬂow Flag — The RISC core’s Overﬂow ﬂag Carry Flag — The RISC core’s Carry ﬂag MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 368 Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-15. XGR1 Field Descriptions Field Description 15–0 XGATE Register 1 — The RISC core’s register 1 XGR1[15:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 369 Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-17. XGR3 Field Descriptions Field Description 15–0 XGATE Register 3 — The RISC core’s register 3 XGR3[15:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 370 Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-19. XGR5 Field Descriptions Field Description 15–0 XGATE Register 5 — The RISC core’s register 5 XGR5[15:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 371 XGATE request. Then it executes a code sequence (thread) that is associated with the requested XGATE channel. Each thread can run on a priority level ranging from 1 to 7. Refer to the S12X_INT MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 372 10.4.2 Programmer’s Model Register Block Program Counter (Stack Pointer) Condition Code Register (Data Pointer) R0 = 0 Figure 10-22. Programmer’s Model 1. With the exception of PRR registers (see Section “S12X_MMC”). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 373 The second word is a pointer to the service routine’s data space. This value will be loaded into register R1 before a service routine is executed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 374 XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore register (XGSEM, see Section 10.3.1.10, “XGATE Semaphore Register (XGSEM)”). The RISC core does this through its SSEM and CSEM instructions. IFigure 10-24 illustrates the valid state transitions. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 375 RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 376 When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS instruction, the XGATE prefetches and discards the opcode of the following instruction. The XGATE will perform its software error handling actions (see above) if this opcode fetch is illegal. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 377 Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7) All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values. 1. Only possible if MCU is unsecured MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 378 NOTE In Debug Mode the XGATE will ignore all requests from peripheral modules. 10.6.1.0.1 Entering Debug Mode Debug mode can be entered in four ways: 1. Setting XGDBG to "1" MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 379 Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device • Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device • Single stepping is not possible on a secured device MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 380 Only the condition code register will be updated 10.8.1.2 Inherent Addressing Mode (INH) Instructions that use this addressing mode either have no operands or all operands are in internal XGATE registers. Examples: MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 381 (RD = f()), or both source and target of the operation (RD = f(RD)). Examples: ; PC = R1, R1 = PC+2 ; Trigger IRQ associated with the channel number in R2.L MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 382 10.8.1.12 Index Register plus Immediate Offset (IDO5) (RS, #OFFS5) provides an unsigned offset from the base register. Examples: R4,(R1,#OFFS5) ; loads a byte from (R1+OFFS5) into R4 R4,(R1,#OFFS5) ; stores R4 as a word to (R1+OFFS5) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 383 ; stores data using RB+RI as effective address RS,(RB, RI+) ; stores data using RB+RI as effective address ; followed by an increment of RI depending on ; the size of the operation. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 384 ; R4 = R4 >> 3; shift register R4 by 3 bits to the right R4,R2 ; R4 = R4 >> R2;arithmetic shift register R4 right by the amount of bits contained in R2[3:0]. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 385 S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 386 A thread can only be interrupted by an interrupt request of higher priority. 10.8.5 Instruction Glossary This section describes the XGATE instruction set in alphabetical order. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 387 Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15] | RS2[15] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode ADC RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 388 | RS2[15] & RD[15] Refer to ADDH instruction for #IMM16 operations. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ADD RD, RS1, RS2 ADD RD, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 389 Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15] & IMM8[7] | RD[15] & RD[15] | IMM8[7] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode ADDH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 390 Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode ADDL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 391 Refer to ANDH instruction for #IMM16 operations. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode AND RD, RS1, RS2 AND RD, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 392 Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ANDH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 393 Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ANDL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 394 Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ASR RD, #IMM4 IMM4 IMM4 ASR RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 395 Tests the Carry ﬂag and branches if C = 0. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BCC REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 396 Tests the Carry ﬂag and branches if C = 1. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BCS REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 397 Tests the Zero ﬂag and branches if Z = 1. CCR Effect — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BEQ REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 398 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BFEXT RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 399 Set if the result is $0000; cleared otherwise. 0; cleared. Set if RS = $0000 ; cleared otherwise. 1. Before executing the instruction Code and CPU Cycles Address Source Form Machine Code Cycles Mode BFFO RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 400 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BFINS RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 401 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BFINSI RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 402 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BFINSX RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 403 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BGE REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 404 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BGT REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 405 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BHI REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 406 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BHS REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 407 Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BITH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 408 Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BITL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 409 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BLE REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 410 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BLO REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 411 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BLS REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 412 R0,RS1,RS2 REL9 CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BLT REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 413 Tests the sign ﬂag and branches if N = 1. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BMI REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 414 Tests the Zero ﬂag and branches if Z = 0. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BNE REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 415 Tests the Sign ﬂag and branches if N = 0. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BPL REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 416 PC + $0002 + (REL10 << 1) ⇒ PC Branches always CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BRA REL10 REL10 REL10 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 417 It is not possible to single step over a BRK instruction. This instruction does not advance the program counter. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode PAff MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 418 Tests the Overﬂow ﬂag and branches if V = 0. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BVC REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 419 Tests the Overﬂow ﬂag and branches if V = 1. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode BVS REL9 REL9 REL9 PP/P MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 420 RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode CMP RS1, RS2 CMP RS, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 421 Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise. RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7] Code and CPU Cycles Address Source Form Machine Code Cycles Mode CMPL RS, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 422 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode COM RD, RS COM RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 423 Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode CPC RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 424 Set if there is a carry from the bit 15 of the result; cleared otherwise. RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode CPCH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 425 In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode CSEM #IMM3 IMM3 IMM3 CSEM RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 426 Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode CSL RD, #IMM4 IMM4 IMM4 CSL RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 427 Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode CSR RD, #IMM4 IMM4 IMM4 CSR RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 428 Jumps to the address stored in RD and saves the return address in RD. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode JAL RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 429 1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 430 Loads an 8 bit immediate constant into the high byte of register RD. The low byte is not affected. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode LDH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 431 Loads an 8 bit immediate constant into the low byte of register RD. The high byte is cleared. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode LDL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 432 1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 433 Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode LSL RD, #IMM4 IMM4 IMM4 LSL RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 434 Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode LSR RD, #IMM4 IMM4 IMM4 LSR RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 435 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode MOV RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 436 Code and CPU Cycles Address Source Form Machine Code Cycles Mode NEG RD, RS 0 0 0 1 1 0 0 0 NEG RD 0 0 0 1 1 0 0 0 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 437 No Operation Operation No Operation for one cycle. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 438 Refer to ORH instruction for #IMM16 operations. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode OR RD, RS1, RS2 OR RD, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 439 Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ORH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 440 Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ORL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 441 Set if RD is $0000; cleared otherwise. 0; cleared. Set if the number of ones in the register RD is odd; cleared otherwise. Code and CPU Cycles Address Source Form Machine Code Cycles Mode PAR, RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 442 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ROL RD, #IMM4 IMM4 IMM4 ROL RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 443 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode ROR RD, #IMM4 IMM4 IMM4 ROR RD, RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 444 Terminates the current thread of program execution. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 445 Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15] | RS2[15] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode SBC RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 446 Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode SEX RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 447 Interrupt ﬂags of reserved channels (see Device User Guide) can’t be set. CCR Effects — — — — Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode SIF RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 448 Not affected. Not affected. Set if semaphore is locked by the RISC core; cleared otherwise. Code and CPU Cycles Address Source Form Machine Code Cycles Mode SSEM #IMM3 IMM3 IMM3 SSEM RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 449 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodiﬁed content of the source register is written to the memory: RS.L ⇒ M[RB, RS-1]; RS-1 ⇒ RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 450 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodiﬁed content of the source register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 451 | RS2[15] & RD[15] Refer to SUBH instruction for #IMM16 operations. Code and CPU Cycles Address Source Form Machine Code Cycles Mode SUB RD, RS1, RS2 SUB RD, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 452 Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15] & IMM8[7] | RD[15] & RD[15] | IMM8[7] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode SUBH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 453 Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15] & RD[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode SUBL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 454 RS[2]. Not affected. RS[1]. Not affected. RS[0]. Code and CPU Cycles Address Source Form Machine Code Cycles Mode TFR RD,CCR CCR ⇒ RD TFR CCR,RS RS ⇒ CCR TFR RD,PCPC+4 ⇒ RD MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 455 RS[15] & result[15] Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & result[15] Code and CPU Cycles Address Source Form Machine Code Cycles Mode TST RS MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 456 Refer to XNORH instruction for #IMM16 operations. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode XNOR RD, RS1, RS2 XNOR RD, #IMM16 IMM8 IMM16[7:0] IMM8 IMM16[15:8] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 457 Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode XNORH RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 458 Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Address Source Form Machine Code Cycles Mode XNORL RD, #IMM8 IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 459 AND RD, RS1, RS2 OR RD, RS1, RS2 XNOR RD, RS1, RS2 Arithmetic Triadic For compare use SUB R0,Rs1,Rs2 SUB RD, RS1, RS2 SBC RD, RS1, RS2 ADD RD, RS1, RS2 ADC RD, RS1, RS2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 460 ANDL RD, #IMM8 IMM8 ANDH RD, #IMM8 IMM8 BITL RD, #IMM8 IMM8 BITH RD, #IMM8 IMM8 ORL RD, #IMM8 IMM8 ORH RD, #IMM8 IMM8 XNORL RD, #IMM8 IMM8 XNORH RD, #IMM8 IMM8 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 461 SCI_REGS+$00 ;SCI Baud Rate Register SCICR2 SCI_REGS+$03 ;SCI Control Register 2 SCISR1 SCI_REGS+$04 ;SCI Status Register 1 SCIDRL SCI_REGS+$07 ;SCI Control Register 2 ;TIE bit mask ;TE bit mask ;RE bit mask MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 462 40000000 ;########################################### S12XE VECTOR TABLE ;########################################### $FF10 ;non-maskable interrupts DUMMY_ISR DUMMY_ISR DUMMY_ISR DUMMY_ISR $FFF4 ;non-maskable interrupts DUMMY_ISR DUMMY_ISR DUMMY_ISR $FFFA ;resets START_OF_CODE START_OF_CODE START_OF_CODE ;########################################### DISABLE COP ;########################################### $FF0E $FFFE $C000 START_OF_CODE MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 463 ;########################################### LDAA #128 ;build XGATE vector table #XGATE_VECTORS INIT_XGATE_VECTAB_LOOP MOVW #XGATE_DUMMY_ISR_XG, 4,Y+ DBNE A, INIT_XGATE_VECTAB_LOOP MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC) MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2 ;########################################### COPY XGATE CODE ;########################################### COPY_XGATE_CODE #XGATE_DATA_FLASH COPY_XGATE_CODE_LOOP MOVW 2,X+, 2,Y+ MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 464 R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be deﬁned: One for threads of priority level 7 to 4 (refer to Section 10.3.1.5, “XGATE Initial Stack Pointer for MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 465 Chapter 10 XGATE (S12XGATEV3) Interrupt Priorities 7 to 4 (XGISP74)”) and one for threads of priority level 3 to 1 (refer to Section 10.3.1.6, “XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)”). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 466 Chapter 10 XGATE (S12XGATEV3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 467: Chapter 11 S12Xe Clocks And Reset Generator (S12Xecrgv1)
— Clock switch for either Oscillator or PLL based system clocks • Computer Operating Properly (COP) watchdog timer with time-out clear window. • System Reset generation from the following possible sources: — Power on reset — Low voltage reset MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 468 It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 11.1.3 Block Diagram Figure 11-1 shows a block diagram of the S12XECRG. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 469 RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 470 Figure 11-2. CRG Register Summary NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 471 IPLL (no locking and/or insufﬁcient stability). Table 11-2. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz 48MHz < f <= 80MHz Reserved 80MHz < f <= 120MHz MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 472 The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the ﬁnal divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f (divide by one). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 473 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 11-6. S12XECRG Flags Register (CRGFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 474 11.3.2.5 S12XECRG Interrupt Enable Register (CRGINT) This register enables S12XECRG interrupt requests. Module Base + 0x0004 RTIE LOCKIE SCMIE Reset = Unimplemented or Reserved Figure 11-7. S12XECRG Interrupt Enable Register (CRGINT) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 475 Module Base + 0x0005 XCLKS PLLSEL PSTP PLLWAI RTIWAI COPWAI Reset = Unimplemented or Reserved Figure 11-8. S12XECRG Clock Select Register (CLKSEL) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 476 1 COP stops and initializes the COP counter whenever the part goes into Wait Mode. 11.3.2.7 S12XECRG IPLL Control Register (PLLCTL) This register controls the IPLL functionality. Module Base + 0x0006 PLLON FSTWKP SCME Reset Figure 11-9. S12XECRG IPLL Control Register (PLLCTL) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 477 0 Detection of crystal clock failure causes clock monitor reset (see Section 11.5.1.1, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 11.4.2.2, “Self Clock Mode”). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 478 RTICTL register. The source clock for the RTI is OSCCLK. Table 11-10. RTI Frequency Divide Rates for RTDEC = 0 RTR[6:4] = RTR[3:0] (OFF) 0000 (÷1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 479 0010 (÷3) 4x10 8x10 20x10 40x10 80x10 200x10 400x10 800x10 0011 (÷4) 5x10 10x10 25x10 50x10 100x10 250x10 500x10 1x10 0100 (÷5) 6x10 12x10 30x10 60x10 120x10 300x10 600x10 1.2x10 0101 (÷6) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 480 — Write once in all other modes – Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 481 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in emulation or special modes Table 11-13. COP Watchdog Rates OSCCLK Cycles to Timeout COP disabled MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 482 Writing to this register when in special test modes can alter the S12XECRG’s functionality. Module Base + 0x000A Reset = Unimplemented or Reserved Figure 11-13. Reserved Register (CTCTL) Read: Always read $00 except in special modes MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 483 WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the ﬁrst 75% of the selected period will cause a COP reset. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 484 11-14. Shaded rows indicated that these settings are not recommended. The following rules help to achieve optimum stability and shortest lock time: • Use lowest possible f ratio (SYNDIV value). • Use highest possible REFCLK frequency f MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 485 , and is cleared Lock when the VCO frequency is out of a certain tolerance, ∆ • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 486 PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 487 See Figure 11-17 as an example. CHECK WINDOW 49999 50000 PLLCLK 4096 OSCCLK 4095 OSC OK Figure 11-17. Check Window Example 1. IPLL is running at self clock mode frequency f MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 488 (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running IPLL (f ) and an active VREG during Pseudo Stop Mode. 1. A Clock Monitor Reset will always set the SCME bit to logical’1’. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 489 If the external clock signal has stabilized again, the S12XECRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 11.4.1.4, “Clock Quality Checker” for more information on entering and leaving Self Clock Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 490 S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the IPLL. There are two ways to restart the MCU from Wait Mode: 1. Any reset 2. Any interrupt MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 491 OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature the clock monitor and the oscillator are disabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 492 11-16. Refer to MCU speciﬁcation for related vector addresses and priorities. Table 11-16. Reset Summary Reset Source Local Enable Power on Reset None Low Voltage Reset None External Reset None Illegal Address Reset None Clock Monitor Reset PLLCTL (CME=1, SCME=0) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 493 External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 64 SYSCLK cycles after the low drive is released. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 494 MCU has reached a certain level and asserts power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 495 Table 11-18. S12XECRG Interrupt Vectors Interrupt Source Local Enable Mask Real time interrupt I bit CRGINT (RTIE) LOCK interrupt I bit CRGINT (LOCKIE) SCM interrupt I bit CRGINT (SCMIE) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 496 SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt ﬂag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 497: Chapter 12 Pierce Oscillator (S12Xosclcpv2)
1. Loop controlled Pierce (LCP) oscillator 2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor The oscillator mode selection is described in the Device Overview section, subsection Oscillator Conﬁguration. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 498 EXTAL is the external clock input or the input to the crystal oscillator ampliﬁer. XTAL is the output of the crystal oscillator ampliﬁer. The MCU internal system clock is derived MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 499 (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. Figure 12-3. Full Swing Pierce Oscillator Connections (FSP mode selected) CMOS Compatible EXTAL External Oscillator Level) DDPLL XTAL Not Connected Figure 12-4. External Clock Connections (FSP mode selected) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 500 During wait mode, XOSC is not impacted. 12.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 501: Chapter 13 Analog-To-Digital Converter (Adc12B16Cv1)
The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity. • Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 502 Wait mode. • Freeze Mode In Freeze Mode the ADC12B16C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 503 ATD 9 and DAC ATD 10 AN15 ATD 11 ATD 12 AN14 ATD 13 ATD 14 AN13 ATD 15 AN12 AN11 AN10 Sample & Hold Comparator Analog Figure 13-1. ADC12B16C Block Diagram MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 504 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 13-2. ADC12B16C Register Summary (Sheet 1 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 505 Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x0022 ATDDR9 Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” = Unimplemented or Reserved Figure 13-2. ADC12B16C Register Summary (Sheet 2 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 506 WRAP[3-0] channel conversions. The coding is summarized in Table 13-3. Table 13-3. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 507 AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for external trigger. The coding is summarized in Table 13-6. 6–5 A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 13-5 SRES[1:0] coding. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 508 Reserved 1. Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 509 The external trigger allows to synchronize the start of conversion with external events. External trigger will not work while converting in stop mode. 0 Disable external trigger 1 Enable external trigger MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 510 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 13-10 gives examples ATD results for an input signal range between 0 and 5.12 Volts. Table 13-9. ATDCTL3 Field Descriptions MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 511 = 0 Volts Codes Codes (transfer curve has = 5.12 Volts (resolution=20mV) (resolution=5mV) 1.25mV offset) (resolution=1.25mV) 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 512 ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 SMP2 SMP1 SMP0 PRS[4:0] Reset Figure 13-7. ATD Control Register 4 (ATDCTL4) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 513 Start of conversion means the beginning of the sampling phase. Module Base + 0x0005 SCAN MULT Reset Figure 13-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 514 AN0 (after converting the channel deﬁned by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN15 to AN0. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 515 This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 ETORF FIFOR Reset = Unimplemented or Reserved Figure 13-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 516 Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. 13.3.2.8 ATD Compare Enable Register (ATDCMPE) Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 517 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 518 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 519 0 If result of conversion n is lower or same than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 520 A/D resolution the conversion result is transferred to the ATD result registers. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 521 By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine is automatically powered down. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 522 Therefore, the ﬂag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 523 Table 13-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 13.3.2, “Register Descriptions” for further details. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 524 Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 525: Chapter 14 Enhanced Capture Timer (Ect16B8Cv3)
16-bit modulus down-counter with 8-bit prescaler. • Four user-selectable delay counters for input noise immunity increase. 14.1.2 Modes of Operation • Stop — Timer and modulus counter are off since clocks are stopped. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 526 Interrupt Input Capture 16-Bit PB Overflow IOC7 Pulse Accumulator B Output Compare Interrupt Figure 14-1. ECT Block Diagram 14.2 External Signal Description The ECT module has a total of eight external pins. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 527 14-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 528 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4 0x000C = Unimplemented or Reserved Figure 14-2. ECT Register Summary (Sheet 1 of 5) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 529 TC5 (High) 0x001B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC5 (Low) = Unimplemented or Reserved Figure 14-2. ECT Register Summary (Sheet 2 of 5) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 530 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 DLYCT 0x002A NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 ICOVW = Unimplemented or Reserved Figure 14-2. ECT Register Summary (Sheet 3 of 5) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 531 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT0 (Low) 0x0038 TC15 TC14 TC13 TC12 TC11 TC10 TC0H (High) 0x0039 TC0H (Low) = Unimplemented or Reserved Figure 14-2. ECT Register Summary (Sheet 4 of 5) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 532 Table 14-2. TIOS Field Descriptions Field Description Input Capture or Output Compare Channel Conﬁguration IOS[7:0] 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 533 7 output compare. Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred from the output compare 7 data register to the timer port. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 534 Module Base + 0x0005 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 Reset Figure 14-8. Timer Count Register Low (TCNT) Read: Anytime Write: Writable in special modes. All bits reset to zero. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 535 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. The pulse accumulators do not stop in freeze mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 536 When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 537 Clear OCx output line to zero Set OCx output line to one NOTE To enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be cleared. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 538 Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) 14.3.2.10 Timer Interrupt Enable Register (TIE) Module Base + 0x000C Reset Figure 14-15. Timer Interrupt Enable Register (TIE) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 539 TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. See Table 14-15. Table 14-15. Prescaler Selection Prescale Factor MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 540 C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0. If the delay counter is enabled, the CxF ﬂag will not be set until after the delay. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 541 14.3.2.14 Timer Input Capture/Output Compare Registers 0–7 Module Base + 0x0010 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 14-19. Timer Input Capture/Output Compare Register 0 High (TC0) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 542 Figure 14-24. Timer Input Capture/Output Compare Register 2 Low (TC2) Module Base + 0x0016 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 14-25. Timer Input Capture/Output Compare Register 3 High (TC3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 543 Figure 14-30. Timer Input Capture/Output Compare Register 5 Low (TC5) Module Base + 0x001C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 14-31. Timer Input Capture/Output Compare Register 6 High (TC6) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 544 14.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL) Module Base + 0x0020 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI Reset = Unimplemented or Reserved Figure 14-35. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 545 1 Interrupt requested if PAIF is set Table 14-19. Pin Action PAMOD PEDGE Pin Action Falling edge Rising edge Divide by 64 clock enabled with pin high level Divide by 64 clock enabled with pin low level MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 546 Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event PAIF mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 547 14.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0) Module Base + 0x0024 PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) Reset Figure 14-39. Pulse Accumulators Count Register 1 (PACN1) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 548 14.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL) Module Base + 0x0026 MCZI MODMC RDMCL MCEN MCPR1 MCPR0 ICLAT FLMC Reset Figure 14-41. 16-Bit Modulus Down-Counter Control Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 549 PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Table 14-23. Modulus Counter Prescaler Select MCPR1 MCPR0 Prescaler Division MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 550 14.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR) Module Base + 0x0028 PA3EN PA2EN PA1EN PA0EN Reset = Unimplemented or Reserved Figure 14-43. Input Control Pulse Accumulators Register (ICPAR) Read: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 551 Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register TSCR1. Table 14-27. Delay Counter Select when PRNT = 0 DLY1 DLY0 Delay Disabled MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 552 14.3.2.23 Input Control Overwrite Register (ICOVW) Module Base + 0x002A NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 Reset Figure 14-45. Input Control Overwrite Register (ICOVW) Read: Anytime Write: Anytime All bits reset to zero. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 553 0x0000. 1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value 0x00FF indicates a count of 255 or more. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 554 Disables the timer channel IO port. Output Compare actions will not affect on the channel pin; the output compare flag will still be set on an Output Compare event. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 555 The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. Table 14-33. Precision Timer Prescaler Selection Examples when PRNT = 1 Prescale PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Factor MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 556 The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Table 14-35. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 Prescaler PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 Division Rate MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 557 Figure 14-51. Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not affect the current status of the bit. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 558 Figure 14-53. 8-Bit Pulse Accumulators Holding Register 2 (PA2H) Module Base + 0x0034 PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1H0 Reset = Unimplemented or Reserved Figure 14-54. 8-Bit Pulse Accumulators Holding Register 1 (PA1H) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 559 If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load register. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 560 Figure 14-59. Timer Input Capture Holding Register 0 Low (TC0H) Module Base + 0x003A TC15 TC14 TC13 TC12 TC11 TC10 Reset = Unimplemented or Reserved Figure 14-60. Timer Input Capture Holding Register 1 High (TC1H) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 561 Figure 14-64. Timer Input Capture Holding Register 3 High (TC3H) Module Base + 0x003F Reset = Unimplemented or Reserved Figure 14-65. Timer Input Capture Holding Register 3 Low (TC3H) Read: Anytime Write: Has no effect. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 562 Section 14.4.1.1, “IC Channels”). 14.4 Functional Description This section provides a complete functional description of the ECT block, detailing the operation of the design from the end user perspective in a number of subsections. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 563 (MDC Latch Enable) Pin Logic EDG6 TC6 Capture/Compare Reg. EDG2 SH26 Comparator Pin Logic EDG7 TC7 Capture/Compare Reg. EDG3 SH37 Figure 14-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 0 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 564 (MDC Latch Enable) Pin Logic EDG6 TC6 Capture/Compare Reg. EDG2 SH26 Comparator Pin Logic EDG7 TC7 Capture/Compare Reg. EDG3 SH37 Figure 14-67. Detailed Timer Block Diagram in Latch Mode when PRNT = 1 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 565 TC6 Capture/Compare Reg. Read TC1H EDG2 Hold Reg. SH26 Comparator Read TC0H Pin Logic EDG7 TC7 Capture/Compare Reg. Hold Reg. EDG3 SH37 Figure 14-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 0 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 566 Read TC1H EDG2 Hold Reg. SH26 Comparator Read TC0H Pin Logic EDG7 TC7 Capture/Compare Reg. Hold Reg. EDG3 SH37 Figure 14-69. Detailed Timer Block Diagram in Queue Mode when PRNT = 1 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 567 8-Bit PAC2 (PACN2) Edge Detector Delay Counter PA2H Holding Register Interrupt 8, 12,16, ..., 1024 EDG3 8-Bit PAC3 (PACN3) Edge Detector Delay Counter PA3H Holding Register Figure 14-70. 8-Bit Pulse Accumulators Block Diagram MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 568 Edge Delay Detector Counter Set CxF TCx Input Interrupt Capture Register BUFEN • LATQ • TFMOD TCxH I.C. Holding Register Figure 14-72. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 569 If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. In case of latching, the contents of its holding register are overwritten. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 570 3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. Input pulses with a duration of DLY_CNT or longer are accepted. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 571 When queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. At the same time the pulse accumulator is cleared. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 572 Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. — Modulus down counter Any access to the MCCNT register clears the MCZF flag in the MCFLG register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 573 Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.4.2 Reset The reset state of each individual bit is listed within the register description section (Section 14.3, “Memory Map and Register Deﬁnition”) which details the registers and their bit-ﬁelds. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 574 14.4.3.5 Pulse Accumulator A Overﬂow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A overﬂow interrupt to be serviced by the system controller. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 575 Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.4.3.6 Timer Overﬂow Interrupt This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced by the system controller. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 576 Chapter 14 Enhanced Capture Timer (ECT16B8CV3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 577: Chapter 15 Inter-Integrated Circuit (Iicv3)
Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identiﬁcation interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 578 This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus speciﬁcation. 15.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus speciﬁcation. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 579 Figure 15-2. IIC Register Summary 15.3.1.1 IIC Address Register (IBAD) Module Base +0x0000 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 Reset = Unimplemented or Reserved Figure 15-3. IIC Bus Address Register (IBAD) Read and write anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 580 IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown Table 15-4. Table 15-4. I-Bus Tap and Prescale Values IBC2-0 SCL Tap SDA Tap (bin) (clocks) (clocks) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 581 SCL to SDA changing, the SDA hold time. IBC7–6 deﬁnes the multiplier factor MUL. The values of MUL are shown in the Table 15-6. SCL Divider SDA Hold MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 582 IBC[7:0] = 0x00 to 0x0F. Table 15-7. IIC Divider and Hold Values (Sheet 1 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) MUL=1 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 583 Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7. IIC Divider and Hold Values (Sheet 2 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 584 SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MUL=2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 585 1532 1538 3840 1916 1922 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 1026 3068 3074 7680 1026 3836 3842 MUL=4 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 586 Table 15-7. IIC Divider and Hold Values (Sheet 5 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1016 1028 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 587 15.3.1.3 IIC Control Register (IBCR) Module Base + 0x0002 IBEN IBIE MS/SL Tx/Rx TXAK IBSWAI RSTA Reset = Unimplemented or Reserved Figure 15-6. IIC Bus Control Register (IBCR) Read and write anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 588 IIC module, then clocks would restart and the IIC would resume from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 589 This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit. Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 590 In master transmit mode, the ﬁrst byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 591 Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described brieﬂy in the following sections and illustrated in Figure 15-10. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 592 (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. START Condition STOP Condition Figure 15-11. Start and Stop Conditions MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 593 ﬁrst. This is called repeated START. A STOP signal is deﬁned as a low-to-high transition of SDA while SCL at logical 1 (see Figure 15-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 594 ﬁrst device to complete its high period pulls the SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 15-12. IIC-Bus Clock Synchronization MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 595 In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast and receives data until the GCEN is disabled or the master device releases the bus or generates a new MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 596 Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 597 CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION IBFREE BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 598 If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 599 MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 600 Write Data To IBDR Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 15-15. Flow-Chart of Typical IIC Interrupt Routine MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 601 Chapter 15 Inter-Integrated Circuit (IICV3) Block Description CAUTION When IIC is conﬁgured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 602 Chapter 15 Inter-Integrated Circuit (IICV3) Block Description MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 603: Chapter 16 Scalable Controller Area Network (S12Mscanv3)
MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed application software. 16.1.1 Glossary ACK: Acknowledge of CAN message CAN: Controller Area Network CRC: Cyclic Redundancy Code EOF: End of Frame FIFO: First-In-First-Out Memory IFS: Inter-Frame Sequence MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 604 Flexible maskable identiﬁer ﬁlter supports two full-size (32-bit) extended identiﬁer ﬁlters, or four 16-bit ﬁlters, or eight 8-bit ﬁlters 1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 605 CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 606 0x0000 RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CANCTL0 0x0001 SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM CANCTL1 = Unimplemented or Reserved u = Unaffected Figure 16-3. MSCAN Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 607 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CANRXERR 0x000F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CANTXERR 0x0010–0x0013 CANIDAR0–3 = Unimplemented or Reserved u = Unaffected Figure 16-3. MSCAN Register Summary (continued) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 608 (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 609 Mode”). This bit must be conﬁgured before sleep mode entry for the selected function to take effect. 0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN 1 Wake-up enabled — The MSCAN is able to restart MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 610 10. RSTAT1 and RSTAT0 are not affected by initialization mode. 16.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 611 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 612 Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing BRP[5:0] (see Table 16-6). Table 16-5. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 613 TSEG1[3:0] of the sample point (see Figure 16-44). Time segment 1 (TSEG1) values are programmable as shown in Table 16-9. 1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 614 Every ﬂag has an associated interrupt enable bit in the CANRIER register. Module Base + 0x0004 RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF Reset: = Unimplemented Figure 16-8. MSCAN Receiver Flag Register (CANRFLG) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 615 TxWRN: 96 < transmit error counter ≤ 127 TxERR: 127 < transmit error counter ≤ 255 Bus-Off: transmit error counter > 255 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 616 (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 617 RXSTAT[1:0] ﬂags deﬁne an additional bus-off state for the receiver (see Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 16.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 618 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 16.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 619 (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 620 The ABTAKx ﬂag is cleared whenever the corresponding TXE ﬂag is cleared. 0 The message was not aborted. 1 The message was aborted. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 621 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. • LDAA CANTFLG; value read is 0b0000_0110 • STAA CANTBSEL; value written is 0b0000_0110 • LDAA CANTBSEL; value read is 0b0000_0010 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 622 Filter”). Table 16-19 summarizes the different settings. Table 16-18. Identiﬁer Acceptance Mode Settings IDAM1 IDAM0 Identiﬁer Acceptance Mode Two 32-bit acceptance ﬁlters Four 16-bit acceptance ﬁlters Eight 8-bit acceptance ﬁlters Filter closed MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 623 Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality. 16.3.2.14 MSCAN Miscellaneous Register (CANMISC) This register provides additional features. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 624 Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 625 (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 16.4.3, “Identiﬁer Acceptance Filter”). For extended identiﬁers, all four acceptance and mask registers are applied. For standard identiﬁers, only the ﬁrst two (CANIDAR0/1, CANIDMR0/1) are applied. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 626 Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits AC[7:0] of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 627 ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 628 If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identiﬁer bits 1 Ignore corresponding acceptance code register bit MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 629 If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identiﬁer bits 1 Ignore corresponding acceptance code register bit MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 630 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit priority registers are 0 out of reset. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 631 ID16 ID15 IDR1 0x00X2 ID14 ID13 ID12 ID11 ID10 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLC3 DLC2 DLC1 DLC0 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 632 The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 633 Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[17:15] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 634 In the case of a transmit buffer, this ﬂag deﬁnes the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 635 ﬂag is set as received and indicates to the CPU how to process the buffer identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send. 0 Standard format (11 bit) 1 Extended format (29 bit) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 636 DLR register. Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7) Reset: Figure 16-34. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 637 0. The data byte count ranges from 0 to 8 for a data frame. Table 16-34 shows the effect of setting the DLC bits. Table 16-34. Data Length Codes Data Length Code Data Byte Count DLC3 DLC2 DLC1 DLC0 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 638 MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers. Module Base + 0xXXXE TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Reset: Figure 16-37. Time Stamp Register — High Byte (TSRH) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 639 “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 16.4 Functional Description 16.4.1 General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 640 CPU bus MSCAN PRIO TXE2 Transmitter PRIO Figure 16-39. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 641 The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 642 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF ﬂag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 643 Four identiﬁer acceptance ﬁlters, each to be applied to 1. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 644 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 16-40. 32-bit Maskable Identiﬁer Acceptance Filter MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 645 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 16-41. 16-bit Maskable Identiﬁer Acceptance Filters MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 646 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 16-42. 8-bit Maskable Identiﬁer Acceptance Filters MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 647 If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 648 (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 16-44. Segments within the Bit Time MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 649 The MSCAN module behaves as described within this speciﬁcation in all normal system operation modes. 16.4.4.2 Special Modes The MSCAN module behaves as described within this speciﬁcation in all special system operation modes. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 650 SLPRQ = X SLPAK = 0 SLPAK = 1 SLPAK = X SLPAK = X CSWAI = X CSWAI = X STOP SLPRQ = X SLPRQ = X SLPAK = X SLPAK = X MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 651 If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. • If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 652 CAN bus activity occurs and WUPE = 1 • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 653 Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 16-46., “Initialization Request/Acknowledge Cycle”). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 654 Such glitches can result from—for example—electromagnetic interference within noisy environments. 16.4.6 Reset Initialization The reset state of each individual bit is listed in Section 16.3.2, “Register Descriptions,” which details all the registers and their bit-ﬁelds. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 655 An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: • Overrun — An overrun condition of the receiver FIFO as described in Section 16.4.2.3, “Receive Structures,” occurred. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 656 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the conﬁguration registers in initialization mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 657 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in Section 16.3.2.14, “MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 658 Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 659: Chapter 17 Periodic Interrupt Timer (S12Pit24B8Cv2)
Eight time-out trigger output signals available to trigger peripheral modules. • Start of timer channels can be aligned to each other. 17.1.3 Modes of Operation Refer to the device overview for a detailed explanation of the chip modes. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 660 16-Bit Timer 6 Interface Trigger 6 Interrupt 7 Time-Out 7 16-Bit Timer 7 Interface Trigger 7 Figure 17-1. PIT24B8C Block Diagram 17.2 External Signal Description The PIT module has no external pins. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 661 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 PITCNT0 (Low) 0x000C PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PITLD1 (High) = Unimplemented or Reserved Figure 17-2. PIT Register Summary (Sheet 1 of 3) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 662 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PITCNT4 (High) 0x001B PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 PITCNT4 (Low) = Unimplemented or Reserved Figure 17-2. PIT Register Summary (Sheet 2 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 663 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PITCNT7 (High) 0x0027 PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 PITCNT7 (Low) = Unimplemented or Reserved Figure 17-2. PIT Register Summary (Sheet 3 of 3) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 664 17.3.0.2 PIT Force Load Timer Register (PITFLT) Module Base + 0x0001 PFLT7 PFLT6 PFLT5 PFLT4 PFLT3 PFLT2 PFLT1 PFLT0 Reset Figure 17-4. PIT Force Load Timer Register (PITFLT) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 665 1 The corresponding PIT channel is enabled. 17.3.0.4 PIT Multiplex Register (PITMUX) Module Base + 0x0003 PMUX7 PMUX6 PMUX5 PMUX4 PMUX3 PMUX2 PMUX1 PMUX0 Reset Figure 17-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 666 PIT Time-Out Flag Register (PITTF) Module Base + 0x0005 PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Reset Figure 17-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 667 PIT Load Register 0 to 7 (PITLD0–7) Module Base + 0x0008, 0x0009 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset Figure 17-11. PIT Load Register 0 (PITLD0) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 668 Figure 17-16. PIT Load Register 5 (PITLD5) Module Base + 0x0020, 0x0021 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset Figure 17-17. PIT Load Register 6 (PITLD6) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 669 PCNT PCNT PCNT PCNT PCNT Reset Figure 17-20. PIT Count Register 1 (PITCNT1) Module Base + 0x0012, 0x0013 R PCNT PCNT PCNT PCNT PCNT PCNT Reset Figure 17-21. PIT Count Register 2 (PITCNT2) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 670 PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access PCNT[15:0] for the count register must take place in one clock cycle as a 16-bit access. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 671 Timer 5 PITLD5 Register time-out 5 PITCNT5 Register PFLT6 Timer 6 PITLD6 Register time-out 6 PITCNT6 Register PFLT7 Timer 7 PITLD7 Register PMUX7 time-out 7 PITCNT7 Register Figure 17-27. PIT24B8C Detailed Block Diagram MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 672 (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant bits set, as shown in Figure 17-28. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 673 For load register values PITLD = 0x0001 and PITMTLD = 0x0002 the ﬂag setting, trigger timing and a restart with force load is shown in Figure 17-28. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 674 ; ch0 connected to micro timer 0 MOVB #$63,PITMTLD0 ; micro time base 0 equals 100 clock cycles MOVW #$0004,PITLD0 ; time base 0 eq. 5 micro time bases 0 =5*100 = 500 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 675 ; loop until interrupt ;******************** Channel 0 Interupt Routine *************************************************** CH0_ISR: LDAA PITTF ; 8 bit read of PIT time out ﬂags MOVB #$01,PITTF ; clear PIT channel 0 time out ﬂag ; return to MAIN MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 676 Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 677: Chapter 18 Periodic Interrupt Timer (S12Pit24B4Cv2)
Four time-out trigger output signals available to trigger peripheral modules. • Start of timer channels can be aligned to each other. 18.1.3 Modes of Operation Refer to the device overview for a detailed explanation of the chip modes. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 678 This section consists of register descriptions in address order of the PIT. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 679 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 PITLD1 (Low) 0x000E PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PITCNT1 (High) = Unimplemented or Reserved Figure 18-2. PIT Register Summary (Sheet 1 of 2) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 680 PITSWAI PITFRZ PFLMT1 PFLMT0 Reset = Unimplemented or Reserved Figure 18-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 681 PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding 16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will always return zero. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 682 PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down- counting. 0 The corresponding PIT channel is disabled. 1 The corresponding PIT channel is enabled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 683 To avoid this, the corresponding PTF ﬂag has to be cleared ﬁrst. 0 Interrupt of the corresponding PIT channel is disabled. 1 Interrupt of the corresponding PIT channel is enabled. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 684 Figure 18-9. PIT Micro Timer Load Register 0 (PITMTLD0) Module Base + 0x0007 PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 Reset Figure 18-10. PIT Micro Timer Load Register 1 (PITMTLD1) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 685 Module Base + 0x0014, 0x0015 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset Figure 18-14. PIT Load Register 3 (PITLD3) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 686 Figure 18-17. PIT Count Register 2 (PITCNT2) Module Base + 0x0016, 0x0017 R PCNT PCNT PCNT PCNT PCNT PCNT Reset Figure 18-18. PIT Count Register 3 (PITCNT3) Read: Anytime Write: Has no meaning or effect MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 687 Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter will load its start value as speciﬁed in the PITMTLD0 or PITMTLD1 register and will start down-counting. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 688 8-Bit Force Load 16-Bit Force Load PTF Flag PITTRIG Time-Out Period Time-Out Period After Restart Note 1. The PTF ﬂag clearing depends on the software Figure 18-20. PIT Trigger and Flag Signal Timing MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 689 Do not use the BSET instructions. Do not use any C-constructs that compile to BSET instructions. “BSET ﬂag_register, #mask” must not be used for ﬂag clearing because BSET is a read- MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 690 ;******************** Channel 0 Interupt Routine *************************************************** CH0_ISR: LDAA PITTF ; 8 bit read of PIT time out ﬂags MOVB #$01,PITTF ; clear PIT channel 0 time out ﬂag ; return to MAIN MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 691: Chapter 19 Pulse-Width Modulator (S12Pwm8B8Cv1)
Eight 8-bit channel or four 16-bit channel PWM resolution • Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies • Programmable clock select logic • Emergency shutdown MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 692 Channel 1 PWM1 Period and Duty Counter Channel 0 PWM0 Period and Duty Counter Figure 19-1. PWM Block Diagram 19.2 External Signal Description The PWM module has a total of 8 external pins. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 693 MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. The ﬁgure below shows the registers associated MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 694 PSWAI PFRZ PWMCTL 0x0006 PWMTST 0x0007 PWMPRSC 0x0008 Bit 7 Bit 0 PWMSCLA 0x0009 Bit 7 Bit 0 PWMSCLB = Unimplemented or Reserved Figure 19-2. PWM Register Summary (Sheet 1 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 695 Bit 0 PWMPER0 0x0015 Bit 7 Bit 0 PWMPER1 0x0016 Bit 7 Bit 0 PWMPER2 0x0017 Bit 7 Bit 0 PWMPER3 = Unimplemented or Reserved Figure 19-2. PWM Register Summary (Sheet 2 of 3) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 696 Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 697 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 698 0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is reached. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 699 1 Clock SA is the clock source for PWM channel 1. Pulse Width Channel 0 Clock Select PCLK0 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 700 PCKA1 PCKA0 Value of Clock A Bus clock Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 701 The PWMCTL register provides for various control of the PWM module. Module Base + 0x0005 CON67 CON45 CON23 CON01 PSWAI PFRZ Reset = Unimplemented or Reserved Figure 19-8. PWM Control Register (PWMCTL) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 702 PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 703 This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0007 Reset = Unimplemented or Reserved Figure 19-10. Reserved Register (PWMPRSC) Read: Always read $00 in normal modes MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 704 Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Module Base + 0x0009 Bit 7 Bit 0 Reset Figure 19-12. PWM Scale B Register (PWMSCLB) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 705 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 706 PWMx Period = Channel Clock Period * PWMPERx CenterAligned Output (CAEx = 1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For boundary case programming values, please refer to Section 19.4.2.8, “PWM Boundary Cases”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 707 To calculate the output duty cycle (high time as a% of period) for a particular channel: • Polarity = 0 (PPOL x =0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% • Polarity = 1 (PPOLx = 1) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 708 1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as “0”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 709 A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 710 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 711 Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 712 (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 713 There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 714 When the channel is disabled (PWMEx = 0), the counter stops. When a MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 715 Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 716 Figure 19-21. PWM Left Aligned Output Example Waveform 19.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 717 PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 718 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 19-24. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 719 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 720 • The 8-bit up/down counter is conﬁgured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 721 A description of the registers involved and affected due to this interrupt is explained in Section 19.3.2.15, “PWM Shutdown Register (PWMSDN)”. The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 722 Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 723: Chapter 20 Serial Communication Interface (S12Sciv5)
IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Signiﬁcant Bit MSB: Most Signiﬁcant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 724 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 725 The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage. 20.3 Memory Map and Register Deﬁnition This section provides a detailed description of all the SCI registers. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 726 Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero Those registers are accessible if the AMAP bit in the SCISR2 register is set to one MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 727 Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 728 Figure 20-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 729 1 Even parity 1 Odd parity Table 20-5. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 730 Module Base + 0x0001 RXEDGIE BERRIE BKDIE Reset = Unimplemented or Reserved Figure 20-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 731 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 20-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 20-19) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 732 SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 733 ﬂag clearing. Module Base + 0x0004 TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 20-10. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 734 RDRF ﬂag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 735 0 Normal polarity 1 Inverted polarity MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 736 Module Base + 0x0007 Reset Figure 20-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 737 CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 738 The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 739 The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 20-15 below. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 740 A frame with nine data bits has a total of 11 bits. Table 20-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits 1. The address bit identiﬁes the frame as an address character. See Section 20.4.6.6, “Receiver Wakeup”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 741 Error SBR[12:0] Clock (Hz) Clock (Hz) Baud Rate 609,756.1 38,109.8 38,400 308,642.0 19,290.1 19,200 153,374.2 9585.9 9,600 76,687.1 4792.9 4,800 38,402.5 2400.2 2,400 1302 19,201.2 1200.1 1,200 2604 9600.6 600.0 5208 4800.0 300.0 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 742 TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 743 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 744 Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 745 TDRE ﬂag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 746 If the bit error detect feature is disabled, the bit error interrupt ﬂag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ﬂag may be set incorrectly. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 747 After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 748 Table 20-17. Start Bit Veriﬁcation RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 749 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 20-19 summarizes the results of the stop bit samples. Table 20-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 750 RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 20-23. Start Bit Search Example 2 MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 751 ﬂag. Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 20-25. Start Bit Search Example 4 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 752 (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 753 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 754 The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 755 Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. Transmitter Receiver Figure 20-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 756 RXPOL and TXPOL are not the same. 20.5 Initialization/Application Information 20.5.1 Reset Initialization Section 20.3.2, “Register Descriptions”. 20.5.2 Modes of Operation 20.5.2.1 Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 20.4.5.2, “Character Transmission”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 757 The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 758 The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 759 The SCI interrupt request can be used to bring the CPU out of wait mode. 20.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 760 Chapter 20 Serial Communication Interface (S12SCIV5) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 761: Chapter 21 Serial Peripheral Interface (S12Spiv5)
Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 21.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 762 Figure 21-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 763 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data when it is conﬁgured as master. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 764 SPC0 SPICR2 0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved 0x0007 Reserved = Unimplemented or Reserved Figure 21-2. SPI Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 765 SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 766 Module Base +0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 21-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 767 Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 768 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 769 39.06 kbit/s 1280 19.53 kbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s 223.21 kbit/s 111.61 kbit/s 55.80 kbit/s MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 770 (SPICR2)”. The ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 771 2. Data in SPIDRH is undeﬁned in this case. 3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 772 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 21-10). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 773 The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 774 If the SS input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 775 SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 776 Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 777 MOSI signal is the output from the master. The SS pin of the master must be either high or reconﬁgured as a general-purpose output not affecting the SPI. 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 778 , and t are guaranteed for the master mode and required for the slave mode. Figure 21-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 779 A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 780 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 21-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 781 (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 21-3. BaudRateDivisor = (SPPR + 1) • 2 (SPR + 1) Eqn. 21-3 MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 782 The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 783 In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 784 SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 785 The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing process which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 786 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 787: Chapter 22 Timer Module (Tim16B8Cv2)
Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 22.1.1 Features The TIM16B8CV2 includes these distinctive features: MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 788 Timer counter keep on running, unless TSFRZ in TSCR (0x0006) is set to 1. Wait: Counters keep on running, unless TSWAI in TSCR (0x0006) is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR (0x0006) is cleared to 0. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 789 Output compare Timer channel 7 Channel 6 interrupt Input capture IOC6 Output compare PA overflow Channel 7 interrupt 16-bit Input capture IOC7 Pulse accumulator Output compare PA input interrupt Figure 22-1. TIM16B8CV2 Block Diagram MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 790 Edge detector Interrupt PACNT Divide by 64 M clock Figure 22-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 22-3. Interrupt Flag Setting MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 791 This pin serves as input capture or output compare for channel 3. 22.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin This pin serves as input capture or output compare for channel 2. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 792 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 TCNTH 0x0005 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 TCNTL = Unimplemented or Reserved Figure 22-5. TIM16B8CV2 Register Summary (Sheet 1 of 3) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 793 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 PACNTH 0x0023 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 PACNTL 0x0024–0x002B Reserved = Unimplemented or Reserved Figure 22-5. TIM16B8CV2 Register Summary (Sheet 2 of 3) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 794 1 The corresponding channel acts as an output compare. 22.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset Figure 22-7. Timer Compare Force Register (CFORC) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 795 OC7D bit. 22.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Reset Figure 22-9. Output Compare 7 Data Register (OC7D) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 796 Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the ﬁrst count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 797 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 798 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 Reset Figure 22-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 Reset Figure 22-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 799 EDG6A EDG5B EDG5A EDG4B EDG4A Reset Figure 22-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset Figure 22-17. Timer Control Register 4 (TCTL4) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 800 Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in C7I:C0I the TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set, the corresponding ﬂag is enabled to cause a interrupt. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 801 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 802 Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 803 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 804 CLK[1:0] Pulse Accumulator Overﬂow Interrupt Enable PAOVI 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 805 When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the ﬂags in the PAFLG register. Timer module must stay enabled (TEN=1) while clearing these bits. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 806 Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock ﬁrst. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 807 22.3.2.19 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 22-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 808 PTPS2 PTPS1 PTPS0 Factor 22.4 Functional Description This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to the detailed timer block diagram in Figure 22-30 as necessary. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 809 Figure 22-30. Detailed Timer Block Diagram 22.4.1 Prescaler The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 810 Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 811 The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF ﬂag to generate interrupt requests. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 812 22.6.3 Pulse Accumulator Overﬂow Interrupt (PAOVF) This active high output will be asserted by the module to request a timer pulse accumulator overﬂow interrupt to be serviced by the system controller. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 813 Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.6.4 Timer Overﬂow Interrupt (TOF) This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced by the system controller. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 814 Chapter 22 Timer Module (TIM16B8CV2) Block Description MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 815: Chapter 23 Voltage Regulator (S12Vregl3V3V1)
Only the POR is available in this mode, LVD, LVR and HTD are disabled. The API is available. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 816 Figure 23-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output voltages. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 817 Select Bus Clock LVD: Low Voltage Detect REG: Regulator Core LVR: Low Voltage Reset CTRL: Regulator Control POR: Power-on Reset API: Auto. Periodical Interrupt HTD: High Temperature Detect Figure 23-1. VREG_3V3 Block Diagram MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 818 Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 819 This section provides a detailed description of all registers accessible in VREG_3V3. If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within it’s memory slice. See device level speciﬁcation for details. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 820 This section describes all the VREG_3V3 registers and their individual bits. emperature 23.3.2.1 Control Register (VREGHTCL) The VREGHTCL register allows to conﬁgure the VREG temperature sense features. 0x02F0 HTDS VSEL HTEN HTIE HTIF Reset = Unimplemented or Reserved MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 821 Note: On entering the reduced power mode the HTIF is not cleared by the VREG. 23.3.2.2 Control Register (VREGCTRL) The VREGCTRL register allows the conﬁguration of the VREG_3V3 low-voltage detect features. 0x02F1 LVDS LVIE LVIF Reset = Unimplemented or Reserved Figure 23-3. Control Register (VREGCTRL) MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 822 Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer APIFE when set. 0 Autonomous periodical interrupt is disabled. 1 Autonomous periodical interrupt is enabled and timer starts running. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 823 APITR[0] Decreases period less than APITR[1] 23.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt rate. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 824 0003 8 * bus clock period 0004 10 * bus clock period 0005 12 * bus clock period ..FFFD 131068 * bus clock period FFFE 131070 * bus clock period MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 825 0 The temperature sense offset is disabled 1 The temperature sense offset is enabled 3–0 High Temperature Trimming Bits — See Table 23-11 for trimming effects. HTTR[3:0] Table 23-11. Trimming Effect Trimming Effect HTTR[3] Increases V twice of HTTR[2] MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 826 ) and continuously updates the status ﬂag LVDS. Interrupt ﬂag LVIF is set whenever status ﬂag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode or Shutdown Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 827 APIE = 1. The timer is started automatically again after it has set APIF. The procedure to change APICLK or APIR[15:0] is ﬁrst to clear APIFE, then write to APICLK or APIR[15:0], and afterwards set APIFE. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 828 (LVR)”. 23.4.11 Interrupts This section describes all interrupts originated by VREG_3V3. The interrupt vectors requested by VREG_3V3 are listed in Table 23-13. Vector addresses and interrupt priorities are deﬁned at MCU level. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 829 As soon as the conﬁgured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 830 Chapter 23 Voltage Regulator (S12VREGL3V3V1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 831: Chapter 24 128 Kbyte Flash Module (S12Xftm128K2V1)
Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 832 Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight ECC bits for single bit fault correction and double bit fault detection within the phrase. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 833 Ability to disable EEE operation and allow priority access to the D-Flash memory • Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory 24.1.2.4 User Buffer RAM Features • Up to 2 Kbytes of RAM for user access MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 834 Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 24.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 24-1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 835 Scratch RAM sector 0 512x16 sector 1 Buffer RAM sector 31 1Kx16 Tag RAM 64x16 Figure 24-1. FTM128K2 Block Diagram 24.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 836 Refer to Section 24.3.2.9, “P-Flash Protection Register (FPROT)” EEE Protection byte 0x7F_FF0D Refer to Section 24.3.2.10, “EEE Protection Register (EPROT)” Flash Nonvolatile byte 0x7F_FF0E Refer to Section 24.3.2.14, “Flash Option Register (FOPT)” MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 837 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 838 Flash Conﬁguration Field P-Flash END = 0x7F_FFFF 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 24-2. P-Flash Memory Map Table 24-4. Program IFR Fields Global Address Size Field Description (PGMIFRON) (Bytes) 0x40_0000 – 0x40_0007 Device ID MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 839 Memory Controller Scratch RAM (TMGRAMON = 1) 0x12_4000 – 0x12_DFFF 40,960 Reserved 0x12_E000 – 0x12_FFFF 8,192 Reserved 0x13_0000 – 0x13_F7FF 63,488 Reserved 0x13_F800 – 0x13_FFFF 2,048 Buffer RAM (User and EEE) 1. MMCCTL1 register bit MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 840 Buffer RAM EEE Partition 0x13_FEC0 Protectable Region (EEE only) 0x13_FF00 64, 128, 192, 256, 320, 384, 448, 512 bytes 0x13_FF40 0x13_FF80 0x13_FFC0 Buffer RAM END = 0x13_FFFF Figure 24-3. EEE Resource Memory Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 841 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 ERSERIE PGMERIE EPVIOLIE ERSVIE1 ERSVIE0 DFDIE SFDIE FERCNFG Figure 24-4. FTM128K2 Register Summary MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 842 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 0x000E FECCRHI ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 Figure 24-4. FTM128K2 Register Summary (continued) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 843 FDIV[6:0] based on OSCCLK frequency. Please refer to Section 24.4.1, “Flash Command Operations,” for more information. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 844 29.40 30.45 0x1C 30.45 31.50 0x1D 31.50 32.55 0x1E 32.55 33.60 0x1F 1. FDIV shown generates an FCLK frequency of >0.8 MHz 2. FDIV shown generates an FCLK frequency of 1.05 MHz MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 845 Table 24-11. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 1. Preferred KEYEN state to disable backdoor key access. Table 24-12. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 846 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 24.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 847 SFDIE interrupt enable in the FERCNFG register is set (see Section 24.3.2.6) 24.3.2.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 848 24.3.2.8) 1 An interrupt will be requested whenever the SFDIF ﬂag is set (see Section 24.3.2.8) 24.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 849 Flash command or during the Flash reset sequence. See Section 24.4.2, “Flash Command Description,” and Section 24.6, “Initialization” for details. 24.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reﬂects the error status of internal Flash operations. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 850 0 to the ERSVIF0 ﬂag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred to the D-Flash EEE partition. 0 No EEE sector format error detected 1 EEE sector format error detected MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 851 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 852 1. For range sizes, refer to Table 24-21 Table 24-22. Table 24-21. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x7F_F800–0x7F_FFFF 2 Kbytes 0x7F_F000–0x7F_FFFF 4 Kbytes 0x7F_E000–0x7F_FFFF 8 Kbytes 0x7F_C000–0x7F_FFFF 16 Kbytes MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 853 Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 854 FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 24-14. P-Flash Protection Scenarios MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 855 F in Figure 24-15. To change the EEE protection that will be loaded during the reset sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 856 24.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 857 Table 24-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] deﬁning Flash command 0, Global address [22:16] Global address [15:8] Global address [7:0] Data 0 [15:8] Data 0 [7:0] MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 858 The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register (see Section 24.3.2.4). Once ECC fault information has been stored, no other MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 859 Global address [15:0] Data 0 [15:0] Data 1 [15:0] (P-Flash only) Data 2 [15:0] (P-Flash only) Data 3 [15:0] (P-Flash only) Not used, returns 0x0000 when read Not used, returns 0x0000 when read MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 860 Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper NV[7:0] use of the NV bits. 24.3.2.15 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 861 This Flash register is reserved for factory testing. Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 24-25. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 862 The FCCOB parameter ﬁelds must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter ﬁelds is controlled via the CCOBIX bits in the FCCOBIX register (see Section 24.3.2.3). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 863 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 24-26. Generic Flash Command Write Sequence Flowchart MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 864 2. Unsecured Normal Expanded mode. 3. Unsecured Special Single Chip mode. 4. Unsecured Special Mode. 5. Secured Normal Single Chip mode. 6. Secured Normal Expanded mode. 7. Secured Special Single Chip mode. 8. Secured Special Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 865 Set User Margin Speciﬁes a user margin read level for all P-Flash blocks. 0x0D Level Set Field Margin Speciﬁes a ﬁeld margin read level for all P-Flash blocks (special modes only). 0x0E Level MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 866 Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 867 The FCCOB upper global address bits determine which block must be veriﬁed. Table 24-35. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of the 0x02 Flash block to be veriﬁed MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 868 Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF ﬂag will set after the Erase Verify P-Flash Section operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 869 Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 870 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 871 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 872 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF Set if any area of the buffer RAM EEE partition is protected 1. As found in the memory map for FTM256K2. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 873 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 874 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF Set if any area of the buffer RAM EEE partition is protected 1. As found in the memory map for FTM256K2. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 875 None 24.4.2.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of a specific P-Flash or D-Flash block. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 876 User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 877 Set if an invalid global address [22:16] is supplied FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None 1. As deﬁned by the memory map for FTM256K2. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 878 Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 24-7) • Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 24-7) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 879 Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased. The CCIF ﬂag will set after the Erase Verify D- Flash Section operation has completed. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 880 D-Flash block. No protection checks are made in the Program D-Flash operation on the D-Flash block, only access error checks. The CCIF ﬂag is set when the operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 881 Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF ﬂag will set after the Erase D-Flash Sector operation has completed. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 882 Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if Full Partition D-Flash or Partition D-Flash command not previously run FSTAT FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 883 (Partition D-Flash Command Section 24.4.2.14), the following reset values are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector Count = 0x_00, Ready Sector Count = 0x_00. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 884 Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 24-7) • Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 24-7) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 885 1. As deﬁned by the maximum ERPART for FTM256K2. 24.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 886 Section 24.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 24.3.2.7, “Flash Status Register (FSTAT)”, and Section 24.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 24-27. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 887 SEC bits of the FSEC register (see Table 24-12). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash conﬁguration ﬁeld at global address 0x7F_FF0F. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 888 0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 889 CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12XE-Family Reference Manual Rev. 1.19 Freescale Semiconductor...
Page 890 Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 891: Chapter 25 256 Kbyte Flash Module (S12Xftm256K2V1)
- Corrected Error Handling table for Load Data Field command 25.4.2/25-928 - Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash, and EEPROM Emulation Query commands 25.3.1/25-896 - Corrected P-Flash IFR Accessibility table MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 892 RAM not required for EEE can be partitioned to provide volatile memory space for applications. Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 893 Dedicated commands to control access to the D-Flash memory over EEE operation • Single bit fault correction and double bit fault detection within a word during read operations • Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 894 Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 25.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 25-1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 895 Scratch RAM sector 0 512x16 sector 1 Buffer RAM sector 127 2Kx16 Tag RAM 128x16 Figure 25-1. FTM256K2 Block Diagram 25.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 896 Refer to Section 25.3.2.9, “P-Flash Protection Register (FPROT)” EEE Protection byte 0x7F_FF0D Refer to Section 25.3.2.10, “EEE Protection Register (EPROT)” Flash Nonvolatile byte 0x7F_FF0E Refer to Section 25.3.2.14, “Flash Option Register (FOPT)” MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 897 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 898 8 Kbytes (up to 29 Kbytes) 0x7F_C000 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 Flash Conﬁguration Field P-Flash END = 0x7F_FFFF 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 25-2. P-Flash Memory Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 899 Memory Controller Scratch RAM (TMGRAMON = 1) 0x12_4000 – 0x12_DFFF 40,960 Reserved 0x12_E000 – 0x12_FFFF 8,192 Reserved 0x13_0000 – 0x13_EFFF 61,440 Reserved 0x13_F000 – 0x13_FFFF 4,096 Buffer RAM (User and EEE) 1. MMCCTL1 register bit MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 900 Buffer RAM EEE Partition 0x13_FEC0 Protectable Region (EEE only) 0x13_FF00 64, 128, 192, 256, 320, 384, 448, 512 bytes 0x13_FF40 0x13_FF80 0x13_FFC0 Buffer RAM END = 0x13_FFFF Figure 25-3. EEE Resource Memory Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 901 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 ERSERIE PGMERIE EPVIOLIE ERSVIE1 ERSVIE0 DFDIE SFDIE FERCNFG Figure 25-4. FTM256K2 Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 902 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 0x000E FECCRHI ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 Figure 25-4. FTM256K2 Register Summary (continued) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 903 FDIV[6:0] based on OSCCLK frequency. Please refer to Section 25.4.1, “Flash Command Operations,” for more information. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 904 29.40 30.45 0x1C 30.45 31.50 0x1D 31.50 32.55 0x1E 32.55 33.60 0x1F 1. FDIV shown generates an FCLK frequency of >0.8 MHz 2. FDIV shown generates an FCLK frequency of 1.05 MHz MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 905 KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 1. Preferred KEYEN state to disable backdoor key access. Table 25-12. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 906 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 25.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 907 SFDIE interrupt enable in the FERCNFG register is set (see Section 25.3.2.6) 25.3.2.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 908 25.3.2.8) 1 An interrupt will be requested whenever the SFDIF ﬂag is set (see Section 25.3.2.8) 25.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 909 Flash command or during the Flash reset sequence. See Section 25.4.2, “Flash Command Description,” and Section 25.6, “Initialization” for details. 25.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reﬂects the error status of internal Flash operations. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 910 0 to the ERSVIF0 ﬂag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred to the D-Flash EEE partition. 0 No EEE sector format error detected 1 EEE sector format error detected MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 911 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 912 1. For range sizes, refer to Table 25-21 Table 25-22. Table 25-21. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x7F_F800–0x7F_FFFF 2 Kbytes 0x7F_F000–0x7F_FFFF 4 Kbytes 0x7F_E000–0x7F_FFFF 8 Kbytes 0x7F_C000–0x7F_FFFF 16 Kbytes MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 913 Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 914 FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 25-14. P-Flash Protection Scenarios MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 915 P-Flash sector containing the EEE protection byte must be unprotected, then the EEE protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 916 25.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 917 Table 25-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] deﬁning Flash command 0, Global address [22:16] Global address [15:8] Global address [7:0] Data 0 [15:8] Data 0 [7:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 918 The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register (see Section 25.3.2.4). Once ECC fault information has been stored, no other MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 919 Global address [15:0] Data 0 [15:0] Data 1 [15:0] (P-Flash only) Data 2 [15:0] (P-Flash only) Data 3 [15:0] (P-Flash only) Not used, returns 0x0000 when read Not used, returns 0x0000 when read MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 920 Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper NV[7:0] use of the NV bits. 25.3.2.15 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 921 This Flash register is reserved for factory testing. Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 25-25. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 922 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 923 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic command write sequence is shown in Figure 25-26. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 924 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 25-26. Generic Flash Command Write Sequence Flowchart MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 925 2. Unsecured Normal Expanded mode. 3. Unsecured Special Single Chip mode. 4. Unsecured Special Mode. 5. Secured Normal Single Chip mode. 6. Secured Normal Expanded mode. 7. Secured Special Single Chip mode. 8. Secured Special Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 926 Set User Margin Speciﬁes a user margin read level for all P-Flash blocks. 0x0D Level Set Field Margin Speciﬁes a ﬁeld margin read level for all P-Flash blocks (special modes only). 0x0E Level MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 927 Suspend all current erase and program activity related to EEPROM emulation but leave 0x14 Emulation current EEE tags set. EEPROM Returns EEE partition and status variables. 0x15 Emulation Query 0x20 Partition D-Flash Partition an area of the D-Flash block for user access. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 928 Set if a Load Data Field command sequence is currently active FSTAT FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read FERSTAT EPVIOLIF None MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 929 Table 25-37. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of 0x03 a P-Flash block Global address [15:0] of the ﬁrst phrase to be veriﬁed Number of phrases to be veriﬁed MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 930 Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 931 Data Field command sequence will be cancelled if any command other than Load Data Field or the future Program P-Flash is launched. Similarly, if an error occurs after launching a Load Data Field or Program P-Flash command, the associated Load Data Field command sequence will be cancelled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 932 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 933 The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 934 During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF ﬂag will set after the Erase All Blocks operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 935 Set if an area of the selected P-Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF None MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 936 P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller veriﬁes that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 937 Verify Backdoor Access Key command are aborted (set ACCERR) until a power down reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 938 Table 25-58. Valid Set User Margin Level Settings CCOB Level Description (CCOBIX=001) 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 1. Read margin to the erased state 2. Read margin to the programmed state MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 939 Valid margin level settings for the Set Field Margin Level command are deﬁned in Table 25-61. Table 25-61. Valid Set Field Margin Level Settings CCOB Level Description (CCOBIX=001) 0x0000 Return to Normal Level 0x0001 User Margin-1 Level MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 940 If unexpected results are encountered when checking Flash memory contents at ﬁeld margin levels, the Flash memory contents should be erased and reprogrammed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 941 Running the Full Partition D-Flash command a second time will result in the previous partition values and the entire D-Flash memory being erased. The data value written corresponds to the number of 256 byte sectors allocated for either direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 942 Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will verify the selected section of D-Flash memory is erased. The CCIF ﬂag will set after the Erase Verify D- Flash Section operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 943 Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred to the Memory Controller and be programmed. The CCOBIX index value at Program D-Flash command launch determines how many words will be programmed in the D-Flash block. No protection checks are MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 944 Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF ﬂag will set after the Erase D-Flash Sector operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 945 Set if a Load Data Field command sequence is currently active Set if Full Partition D-Flash or Partition D-Flash command not previously run FSTAT FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 946 (Partition D-Flash Command Section 25.4.2.15), the following reset values are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector Count = 0x_00, Ready Sector Count = 0x_00. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 947 RAM EEE space to support EEE) • Erase verify the D-Flash block and the EEE nonvolatile information register • Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see Table 25-7) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 948 None 25.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 949 Section 25.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 25.3.2.7, “Flash Status Register (FSTAT)”, and Section 25.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 25-27. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 950 SEC bits of the FSEC register (see Table 25-12). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash conﬁguration ﬁeld at global address 0x7F_FF0F. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 951 0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 952 If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 953 - Updated Command Error Handling tables based on parent-child relationship with FTM512K3 26.4.2/26-989 - Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash, and EEPROM Emulation Query commands 26.3.1/26-958 - Corrected P-Flash IFR Accessibility table MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 954 Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for applications. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 955 Ability to program up to one phrase in each P-Flash block simultaneously. • Flexible protection scheme to prevent accidental program or erase of P-Flash memory. 26.1.2.2 D-Flash Features • Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 956 Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 26.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 26-1. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 957 Scratch RAM sector 0 512x16 sector 1 Buffer RAM sector 127 2Kx16 Tag RAM 128x16 Figure 26-1. FTM384K2 Block Diagram 26.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 958 Refer to Section 26.3.2.9, “P-Flash Protection Register (FPROT)” EEE Protection byte 0x7F_FF0D Refer to Section 26.3.2.10, “EEE Protection Register (EPROT)” Flash Nonvolatile byte 0x7F_FF0E Refer to Section 26.3.2.14, “Flash Option Register (FOPT)” MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 959 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 960 Flash Conﬁguration Field P-Flash END = 0x7F_FFFF 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 26-2. P-Flash Memory Map Table 26-4. Program IFR Fields Global Address Size Field Description (PGMIFRON) (Bytes) 0x40_0000 – 0x40_0007 Device ID MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 961 Memory Controller Scratch RAM (TMGRAMON = 1) 0x12_4000 – 0x12_DFFF 40,960 Reserved 0x12_E000 – 0x12_FFFF 8,192 Reserved 0x13_0000 – 0x13_EFFF 61,440 Reserved 0x13_F000 – 0x13_FFFF 4,096 Buffer RAM (User and EEE) 1. MMCCTL1 register bit MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 962 Buffer RAM EEE Partition 0x13_FEC0 Protectable Region (EEE only) 0x13_FF00 64, 128, 192, 256, 320, 384, 448, 512 bytes 0x13_FF40 0x13_FF80 0x13_FFC0 Buffer RAM END = 0x13_FFFF Figure 26-3. EEE Resource Memory Map MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 963 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX 0x0003 ECCRIX2 ECCRIX1 ECCRIX0 FECCRIX 0x0004 CCIE IGNSF FDFD FSFD FCNFG 0x0005 ERSERIE PGMERIE EPVIOLIE ERSVIE1 ERSVIE0 DFDIE SFDIE FERCNFG Figure 26-4. FTM384K2 Register Summary MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 964 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 0x000E FECCRHI ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 Figure 26-4. FTM384K2 Register Summary (continued) MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 965 FDIV[6:0] based on OSCCLK frequency. Please refer to Section 26.4.1, “Flash Command Operations,” for more information. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 966 29.40 30.45 0x1C 30.45 31.50 0x1D 31.50 32.55 0x1E 32.55 33.60 0x1F 1. FDIV shown generates an FCLK frequency of >0.8 MHz 2. FDIV shown generates an FCLK frequency of 1.05 MHz MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 967 KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 1. Preferred KEYEN state to disable backdoor key access. Table 26-12. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 968 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 26.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 969 SFDIE interrupt enable in the FERCNFG register is set (see Section 26.3.2.6) 26.3.2.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 970 26.3.2.8) 1 An interrupt will be requested whenever the SFDIF ﬂag is set (see Section 26.3.2.8) 26.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 971 Flash command or during the Flash reset sequence. See Section 26.4.2, “Flash Command Description,” and Section 26.6, “Initialization” for details. 26.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reﬂects the error status of internal Flash operations. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 972 0 to the ERSVIF0 ﬂag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred to the D-Flash EEE partition. 0 No EEE sector format error detected 1 EEE sector format error detected MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 973 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 974 1. For range sizes, refer to Table 26-21 Table 26-22. Table 26-21. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x7F_F800–0x7F_FFFF 2 Kbytes 0x7F_F000–0x7F_FFFF 4 Kbytes 0x7F_E000–0x7F_FFFF 8 Kbytes 0x7F_C000–0x7F_FFFF 16 Kbytes MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 975 Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 976 FLASH START 0x7F_8000 0x7F_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 26-14. P-Flash Protection Scenarios MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 977 F in Figure 26-15. To change the EEE protection that will be loaded during the reset sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 978 26.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 979 Table 26-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] deﬁning Flash command 0, Global address [22:16] Global address [15:8] Global address [7:0] Data 0 [15:8] Data 0 [7:0] MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 980 The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register (see Section 26.3.2.4). Once ECC fault information has been stored, no other MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 981 Global address [15:0] Data 0 [15:0] Data 1 [15:0] (P-Flash only) Data 2 [15:0] (P-Flash only) Data 3 [15:0] (P-Flash only) Not used, returns 0x0000 when read Not used, returns 0x0000 when read MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 982 Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper NV[7:0] use of the NV bits. 26.3.2.15 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 983 This Flash register is reserved for factory testing. Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 26-25. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 984 CCIF command completion ﬂag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF ﬂag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 985 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 26-26. Generic Flash Command Write Sequence Flowchart MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 986 2. Unsecured Normal Expanded mode. 3. Unsecured Special Single Chip mode. 4. Unsecured Special Mode. 5. Secured Normal Single Chip mode. 6. Secured Normal Expanded mode. 7. Secured Special Single Chip mode. 8. Secured Special Mode. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 987 Set User Margin Speciﬁes a user margin read level for all P-Flash blocks. 0x0D Level Set Field Margin Speciﬁes a ﬁeld margin read level for all P-Flash blocks (special modes only). 0x0E Level MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 988 Suspend all current erase and program activity related to EEPROM emulation but leave 0x14 Emulation current EEE tags set. EEPROM Returns EEE partition and status variables. 0x15 Emulation Query 0x20 Partition D-Flash Partition an area of the D-Flash block for user access. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 989 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read FERSTAT EPVIOLIF None 1. As found in the memory map for FTM512K3. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 990 Table 26-37. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] of 0x03 a P-Flash block Global address [15:0] of the ﬁrst phrase to be veriﬁed Number of phrases to be veriﬁed MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 991 Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 992 Data Field command sequence will be cancelled if any command other than Load Data Field or the future Program P-Flash is launched. Similarly, if an error occurs after launching a Load Data Field or Program P-Flash command, the associated Load Data Field command sequence will be cancelled. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 993 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 994 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF None 1. As deﬁned by the memory map for FTM512K3. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 995 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF None 1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 996 Upon clearing CCIF to launch the Erase P-Flash Block command, the Memory Controller will erase the selected P-Flash block and verify that it is erased. The CCIF ﬂag will set after the Erase P-Flash Block operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 997 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 998 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation FERSTAT EPVIOLIF Set if any area of the buffer RAM EEE partition is protected MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 999 Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 26.3.2.2) FSTAT Set if the backdoor key has mismatched since the last power down FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None MC9S12XE-Family Reference Manual , Rev. 1.19 Freescale Semiconductor...
Page 1000 Set if an invalid global address [22:16] is supplied FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None 1. As deﬁned by the memory map for FTM512K3. MC9S12XE-Family Reference Manual , Rev. 1.19 1000 Freescale Semiconductor...

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Mc9s12xep100 Hcs12x

Freescale Semiconductor MC9S12XE Series Reference Manual

Chapter 26 384 Kbyte Flash Module (S12XFTM384K2V1)

Chapter 27 512 Kbyte Flash Module (S12XFTM512K3V1)

Chapter 28 768 Kbyte Flash Module (S12XFTM768K4V2)

Chapter 29 1024 Kbyte Flash Module (S12XFTM1024K5V2)

Appendix A Electrical Characteristics

Appendix B Package Information

Appendix Cpcb Layout Guidelines

Appendix D Derivative Differences

Appendix E Detailed Register Address Map

Appendix F Ordering Information

Chapter 1 Device Overview MC9S12XE-Family

Chapter 2 Port Integration Module (S12XEP100PIMV1)

Chapter 3 Memory Mapping Control (S12XMMCV4)

Chapter 4 Memory Protection Unit (S12XMPUV1)

Chapter 5 External Bus Interface (S12XEBIV4)

Chapter 6 Interrupt (S12XINTV2)

Chapter 7 Background Debug Module (S12XBDMV2)

Chapter 8 S12X Debug (S12XDBGV3) Module

Chapter 9 Security (S12XE9SECV2)

Chapter 10 XGATE (S12XGATEV3)

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)

Chapter 12 Pierce Oscillator (S12XOSCLCPV2)

Chapter 13 Analog-To-Digital Converter (ADC12B16CV1)

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)

Chapter 15 Inter-Integrated Circuit (IICV3)

Chapter 16 Scalable Controller Area Network (S12MSCANV3)

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)

Chapter 20 Serial Communication Interface (S12SCIV5)

Chapter 21 Serial Peripheral Interface (S12SPIV5)

Chapter 22 Timer Module (TIM16B8CV2)

Chapter 23 Voltage Regulator (S12VREGL3V3V1)

Chapter 24 128 Kbyte Flash Module (S12XFTM128K2V1)

Chapter 25 256 Kbyte Flash Module (S12XFTM256K2V1)

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