Freescale Semiconductor ColdFire MCF5212 Manuals

Manuals and User Guides for Freescale Semiconductor ColdFire MCF5212. We have 1 Freescale Semiconductor ColdFire MCF5212 manual available for free PDF download: Reference Manual

Freescale Semiconductor ColdFire MCF5212 Reference Manual (544 pages)

Integrated Microcontroller

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 4 MB

Table of Contents
5
Paragraph Number

6
About this Book

27
- Audience
  27
- Organization
  27
- Conventions
  29
- Register Figure Conventions
  30
- Acronyms and Abbreviations
  31
- Terminology Conventions
  32
Chapter 1 Overview

35
- MCF5213 Family Configurations
  36
- Block Diagram
  37
- Part Numbers and Packaging
  37
- Features
  38
- V2 Core Overview
  42
- Integrated Debug Module
  43
- Jtag
  43
- On-Chip Memories
  44
- Sram
  44
- Flash Memory
  44
- Power Management
  44
- Flexcan
  44
- Uarts
  45
- I 2 C Bus
  45
- Qspi
  45
- Fast ADC
  45
- DMA Timers (DTIM0-DTIM3)
  45
- General Purpose Timer (GPT)
  46
- Periodic Interrupt Timers (PIT0 and PIT1)
  46
- Pulse-Width Modulation (PWM) Timers
  46
- Software Watchdog Timer
  46
- Phase-Locked Loop (PLL)
  46
- Interrupt Controller (INTC)
  47
- DMA Controller
  47
- Reset
  47
- Gpio
  47
Chapter 2 Signal Descriptions

49
- Introduction
  49
- Overview
  49
- Reset Signals
  55
- PLL and Clock Signals
  55
- Mode Selection
  55
- External Interrupt Signals
  56
- Queued Serial Peripheral Interface (QSPI)
  56
- I 2 C I/O Signals
  57
- UART Module Signals
  57
- 2.10 DMA Timer Signals
  57
- 2.11 ADC Signals
  58
- 2.12 General Purpose Timer Signals
  58
- 2.13 Pulse-Width Modulator Signals
  58
- 2.14 Debug Support Signals
  58
- 2.15 Ezport Signal Descriptions
  60
- 2.16 Power and Ground Pins
  60
Chapter 3 Coldfire Core

61
- Processor Pipelines
  61
- Memory Map/Register Description
  62
- Data Registers (D0-D7)
  64
- Address Registers (A0-A6)
  64
- Supervisor/User Stack Pointers (A7 and OTHER_A7)
  64
- Condition Code Register (CCR)
  65
- Program Counter (PC)
  66
- Vector Base Register (VBR)
  66
- Status Register (SR)
  67
- Memory Base Address Registers (RAMBAR, FLASHBAR)
  68
- Instruction Set Architecture (ISA_A+)
  68
- Exception Processing Overview
  69
- Exception Stack Frame Definition
  70
- Processor Exceptions
  72
- Access Error Exception
  72
- Address Error Exception
  72
- Illegal Instruction Exception
  72
- Divide-By-Zero
  73
- Privilege Violation
  74
- Trace Exception
  74
- Unimplemented Line-A Opcode
  74
- Unimplemented Line-F Opcode
  74
- Debug Interrupt
  75
- RTE and Format Error Exception
  75
- TRAP Instruction Exception
  75
- Interrupt Exception
  75
- Fault-On-Fault Halt
  75
- Reset Exception
  75
- Instruction Execution Timing
  79
- Timing Assumptions
  79
- MOVE Instruction Execution Times
  80
- Standard One Operand Instruction Execution Times
  81
- Standard Two Operand Instruction Execution Times
  82
- Miscellaneous Instruction Execution Times
  83
- MAC Instruction Execution Times
  84
- Branch Instruction Execution Times
  85
Chapter 4 Multiply-Accumulate Unit (MAC)

87
- Multiply-Accumulate Unit
  87
- Introduction to the MAC
  87
- General Operation
  88
- Memory Map/Register Definition
  89
- MAC Status Register (MACSR)
  89
- Fractional Operation Mode
  91
- Rounding
  91
- Saving and Restoring the MAC Programming Model
  92
- Muls/Mulu
  92
- Scale Factor in MAC or MSAC Instructions
  92
- Mask Register (MASK)
  93
- Accumulator Register (ACC)
  94
- MAC Instruction Set Summary
  94
- MAC Instruction Execution Times
  95
- Data Representation
  95
- MAC Opcodes
  95
Chapter 5 Static RAM (SRAM)

101
- Introduction
  101
- Overview
  101
- Features
  101
- Memory Map/Register Description
  101
- SRAM Base Address Register (RAMBAR)
  102
- Initialization/Application Information
  103
- SRAM Initialization Code
  104
- Power Management
  104
Chapter 6 Clock Module

105
- Introduction
  105
- Features
  105
- Modes of Operation
  105
- Normal PLL Mode
  105
- 1:1 PLL Mode
  106
- External Clock Mode
  106
- Low-Power Mode Operation
  106
- Block Diagram
  106
- Signal Descriptions
  108
- Extal
  108
- Xtal
  108
- Clkout
  108
- Clkmod[1:0]
  108
- Rsto
  109
- Memory Map and Registers
  109
- Register Descriptions
  109
- Synthesizer Control Register (SYNCR)
  109
- Synthesizer Status Register (SYNSR)
  111
- Low-Power Divider Register (LPDR)
  113
- Functional Description
  114
- System Clock Modes
  114
- Clock Operation During Reset
  114
- System Clock Generation
  115
- PLL Operation
  115
- Phase and Frequency Detector (PFD)
  116
- Charge Pump/Loop Filter
  116
- Voltage Control Output (VCO)
  117
- Multiplication Factor Divider (MFD)
  117
- PLL Lock Detection
  117
- PLL Loss of Lock Conditions
  118
- PLL Loss of Lock Reset
  118
- Loss of Clock Detection
  119
- Loss of Clock Reset
  119
- Alternate Clock Selection
  119
- Loss of Clock in Stop Mode
  120
Chapter 7 Power Management

125
- Introduction
  125
- Features
  125
- Memory Map/Register Definition
  125
- Peripheral Power Management Registers (PPMRH, PPMRL)
  126
- Peripheral Power Management Register Low (PPMRL)
  128
- Low-Power Interrupt Control Register (LPICR)
  129
- Peripheral Power Management Set Register (PPMRS)
  131
- Peripheral Power Management Clear Register (PPMRC)
  131
- Low-Power Control Register (LPCR)
  132
- IPS Bus Timeout Monitor
  133
- Functional Description
  134
- Low-Power Modes
  134
- Run Mode
  135
- Wait Mode
  135
- Doze Mode
  135
- Stop Mode
  135
- Peripheral Shut down
  135
- Peripheral Behavior in Low-Power Modes
  136
- Coldfire Core
  136
- Static Random-Access Memory (SRAM)
  136
- Flash
  136
- System Control Module (SCM)
  136
- DMA Controller (DMA0-DMA3)
  136
- UART Modules (UART0, UART1, and UART2)
  136
- I2C Module
  137
- Queued Serial Peripheral Interface (QSPI)
  137
- DMA Timers (DTIM0-DTIM3)
  137
- Interrupt Controllers (INTC0, INTC1)
  137
- I/O Ports
  138
- Reset Controller
  138
- Chip Configuration Module
  138
- Clock Module
  138
- Edge Port
  139
- Programmable Interrupt Timers (PIT0-PIT1)
  139
- Flexcan
  139
- Bdm
  141
- PWM Module
  141
- Jtag
  141
- Summary of Peripheral State During Low-Power Modes
  141
Chapter 8 Chip Configuration Module (CCM)

143
- Introduction
  143
- Features
  143
- External Signal Descriptions
  143
- Rcon
  144
- Clkmod[1:0]
  144
- Jtag_En
  144
- Test
  144
- Memory Map/Register Definition
  144
- Programming Model
  144
- Memory Map
  145
- Register Descriptions
  145
- Chip Configuration Register (CCR)
  145
- Reset Configuration Register (RCON)
  146
- Chip Identification Register (CIR)
  146
Chapter 9 Reset Controller Module

149
- Introduction
  149
- Features
  149
- Block Diagram
  149
- Signals
  150
- Rsti
  150
- Rsto
  150
- Memory Map and Registers
  150
- Reset Control Register (RCR)
  151
- Reset Status Register (RSR)
  152
- Functional Description
  153
- Reset Sources
  153
- Power-On Reset
  154
- External Reset
  154
- Loss-Of-Clock Reset
  154
- Loss-Of-Lock Reset
  154
- Software Reset
  154
- LVD Reset
  154
- Reset Control Flow
  154
- Synchronous Reset Requests
  156
- Internal Reset Request
  156
- Power-On Reset/Low-Voltage Detect Reset
  156
- Concurrent Resets
  156
- Reset Flow
  156
- Reset Status Flags
  157
Chapter 10 System Control Module (SCM)

159
- Introduction
  159
- Overview
  159
- Features
  159
- Memory Map and Register Definition
  160
- Register Descriptions
  161
- Internal Peripheral System Base Address Register (IPSBAR)
  161
- Memory Base Address Register (RAMBAR)
  162
- Core Reset Status Register (CRSR)
  164
- Core Watchdog Control Register (CWCR)
  165
- Core Watchdog Service Register (CWSR)
  166
- Internal Bus Arbitration
  167
- Overview
  167
- Arbitration Algorithms
  168
- Round-Robin Mode
  168
- Fixed Mode
  168
- Bus Master Park Register (MPARK)
  168
- System Access Control Unit (SACU)
  170
- Overview
  170
- Features
  170
- Memory Map/Register Definition
  171
- Master Privilege Register (MPR)
  172
- Peripheral Access Control Registers (PACR0-PACR8)
  172
- Grouped Peripheral Access Control Registers (GPACR0 & GPACR1)
  174
Chapter 11 General Purpose I/O Module

177
- Introduction
  177
- Overview
  178
- Features
  178
- Signal Descriptions
  178
- Memory Map/Register Definition
  178
- Ports Memory Map
  178
- Register Descriptions
  180
- Port Output Data Registers (Portn)
  180
- Port Data Direction Registers (Ddrn)
  181
- Port Pin Data/Set Data Registers (Portnp/Setn)
  183
- Port Clear Output Data Registers (Clrn)
  185
- Pin Assignment Registers
  186
- Dual-Function Pin Assignment Registers
  187
- Quad Function Pin Assignment Registers
  187
- Port NQ Pin Assignment Register (PNQPAR)
  189
- Pad Control Registers
  189
- Pin Slew Rate Register (PSRR)
  189
- Pin Drive Strength Register (PDSR)
  191
- Ports Interrupts
  191
Chapter 12 Interrupt Controller Module

193
Chapter 13 Edge Port Module (EPORT)

211
- Introduction
  211
- Low-Power Mode Operation
  211
- Interrupt/General-Purpose I/O Pin Descriptions
  212
- Memory Map and Registers
  213
- Memory Map
  213
- Registers
  213
- EPORT Pin Assignment Register (EPPAR)
  214
- EPORT Data Direction Register (EPDDR)
  214
- Edge Port Interrupt Enable Register (EPIER)
  215
- Edge Port Data Register (EPDR)
  215
- Edge Port Pin Data Register (EPPDR)
  216
- Edge Port Flag Register (EPFR)
  216
Chapter 14 DMA Controller Module

219
- Introduction
  219
- Overview
  219
- Features
  220
- DMA Transfer Overview
  221
- Memory Map/Register Definition
  221
- DMA Request Control (DMAREQC)
  222
- Source Address Registers (Sarn)
  223
- Destination Address Registers (Darn)
  223
- Byte Count Registers (Bcrn) and DMA Status Registers (Dsrn)
  224
- DMA Control Registers (Dcrn)
  226
- Functional Description
  229
- Transfer Requests (Cycle-Steal and Continuous Modes)
  230
- Dual-Address Data Transfer Mode
  230
- Channel Initialization and Startup
  231
- Channel Prioritization
  231
- Programming the DMA Controller Module
  231
- Data Transfer
  232
- Auto-Alignment
  232
- Bandwidth Control
  232
- Termination
  233
- Document Revision History
  233
Chapter 15 Coldfire Flash Module (CFM)

235
- Introduction
  235
- Overview
  235
- Features
  236
- External Signal Description
  237
- Memory Map and Register Definition
  237
- Memory Map
  237
- Flash Base Address Register (FLASHBAR)
  238
- Register Descriptions
  241
- CFMMCR - CFM Module Configuration Register
  241
- CFMCLKD - CFM Clock Divider Register
  242
- CFMSEC - CFM Security Register
  243
- CFMPROT - CFM Protection Register
  244
- CFMSACC - CFM Supervisor Access Register
  246
- CFMDACC - CFM Data Access Register
  247
- CFMUSTAT - CFM User Status Register
  247
- CFMCMD - CFM Command Register
  249
- CFMCLKSEL - CFM Clock Select Register
  250
- Functional Description
  250
- General
  250
- Flash Normal Mode
  251
- Read Operation
  251
- Write Operation
  251
- Program, Erase, and Verify Operations
  251
- Writing the CFMCLKD Register
  251
- Command Write Sequence
  252
- Bus Arbitration During Write Operations
  253
- Flash Normal Mode Commands
  253
- Blank Check
  253
- Page Erase Verify
  255
- Program
  257
- Page Erase
  258
- Mass Erase
  260
- Flash Normal Mode Illegal Operations
  263
- Stop Mode
  263
- Flash Security Operation
  264
- Backdoor Access Sequence
  264
- Blank Check
  265
- JTAG Lockout Recovery
  265
Chapter 16

267
- Features
  267
- Modes of Operation
  267
- External Signal Description
  268
- Overview
  268
- Detailed Signal Descriptions
  268
- EZPCK - Ezport Clock
  268
- EZPCS - Ezport Chip Select
  269
- EZPD - Ezport Serial Data in
  269
- EZPQ - Ezport Serial Data out
  269
- Command Definition
  269
- Command Descriptions
  270
- Write Enable
  270
- Write Disable
  270
- Read Status Register
  270
- Write Configuration Register
  271
- Read Data
  272
- Read Data at High Speed
  272
- Page Program
  272
- Sector Erase
  273
- Bulk Erase
  273
- 16.4.1.10 Reset Chip
  273
- Functional Description
  273
- Initialization/Application Information
  274
Chapter 17 Programmable Interrupt Timers (PIT0-PIT1)

275
- Introduction
  275
- Overview
  275
- Block Diagram
  275
- Low-Power Mode Operation
  275
- Memory Map/Register Definition
  276
- PIT Control and Status Register (Pcsrn)
  277
- PIT Modulus Register (Pmrn)
  278
- PIT Count Register (Pcntrn)
  279
- Functional Description
  279
- Set-And-Forget Timer Operation
  279
- Free-Running Timer Operation
  280
- Timeout Specifications
  280
- Interrupt Operation
  280
Chapter 18 General Purpose Timer Module (GPT)

283
- Introduction
  283
- Features
  283
- Block Diagram
  284
- Low-Power Mode Operation
  285
- Signal Description
  285
- Gpt[2:0]
  285
- Gpt3
  285
- Syncn
  286
- Memory Map and Registers
  286
- GPT Input Capture/Output Compare Select Register (GPTIOS)
  287
- GPT Compare Force Register (GPCFORC)
  288
- GPT Output Compare 3 Mask Register (GPTOC3M)
  288
- GPT Output Compare 3 Data Register (GPTOC3D)
  289
- GPT Counter Register (GPTCNT)
  289
- GPT System Control Register 1 (GPTSCR1)
  290
- GPT Toggle-On-Overflow Register (GPTTOV)
  291
- GPT Control Register 1 (GPTCTL1)
  291
- GPT Control Register 2 (GPTCTL2)
  292
- GPT Interrupt Enable Register (GPTIE)
  292
- GPT System Control Register 2 (GPTSCR2)
  293
- GPT Flag Register 1 (GPTFLG1)
  294
- GPT Flag Register 2 (GPTFLG2)
  294
- GPT Channel Registers (Gptcn)
  295
- Pulse Accumulator Control Register (GPTPACTL)
  295
- Pulse Accumulator Flag Register (GPTPAFLG)
  296
- Pulse Accumulator Counter Register (GPTPACNT)
  297
- GPT Port Data Register (GPTPORT)
  298
- GPT Port Data Direction Register (GPTDDR)
  298
- Functional Description
  298
- Prescaler
  299
- Input Capture
  299
- Output Compare
  299
- Pulse Accumulator
  300
- Event Counter Mode
  300
- Gated Time Accumulation Mode
  300
- General-Purpose I/O Ports
  301
- Reset
  303
- Interrupts
  303
- GPT Channel Interrupts (Cnf)
  303
- Pulse Accumulator Overflow (PAOVF)
  303
- Pulse Accumulator Input (PAIF)
  304
- Timer Overflow (TOF)
  304
Chapter 19 DMA Timers (DTIM0-DTIM3)

305
- Introduction
  305
- Overview
  305
- Features
  306
- Memory Map/Register Definition
  306
- DMA Timer Mode Registers (Dtmrn)
  307
- DMA Timer Extended Mode Registers (Dtxmrn)
  308
- DMA Timer Event Registers (Dtern)
  309
- DMA Timer Reference Registers (Dtrrn)
  310
- DMA Timer Capture Registers (Dtcrn)
  311
- DMA Timer Counters (Dtcnn)
  311
- Functional Description
  312
- Prescaler
  312
- Capture Mode
  312
- Reference Compare
  312
- Output Mode
  312
- Initialization/Application Information
  313
- Code Example
  313
- Calculating Time-Out Values
  314
Chapter 20 Queued Serial Peripheral Interface (QSPI)

315
- Introduction
  315
- Block Diagram
  315
- Overview
  316
- Features
  316
- Modes of Operation
  316
- External Signal Description
  316
- Memory Map/Register Definition
  317
- QSPI Mode Register (QMR)
  317
- QSPI Delay Register (QDLYR)
  319
- QSPI Wrap Register (QWR)
  320
- QSPI Interrupt Register (QIR)
  320
- QSPI Address Register (QAR)
  321
- QSPI Data Register (QDR)
  322
- Command RAM Registers (QCR0-QCR15)
  322
- Functional Description
  323
- Qspi Ram
  325
- Receive RAM
  325
- Transmit RAM
  326
- Command RAM
  326
- Baud Rate Selection
  326
- Transfer Delays
  327
- Transfer Length
  328
- Data Transfer
  328
- Initialization/Application Information
  329
Chapter 21 UART Modules

331
- Introduction
  331
- Overview
  331
- Features
  332
- External Signal Description
  332
- Memory Map/Register Definition
  333
- UART Mode Registers 1 (Umr1N)
  335
- UART Mode Register 2 (Umr2N)
  336
- UART Status Registers (Usrn)
  337
- UART Clock Select Registers (Ucsrn)
  339
- UART Command Registers (Ucrn)
  339
- UART Receive Buffers (Urbn)
  341
- UART Transmit Buffers (Utbn)
  342
- UART Input Port Change Registers (Uipcrn)
  342
- UART Auxiliary Control Register (Uacrn)
  343
- UART Interrupt Status/Mask Registers (Uisrn/Uimrn)
  343
- UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
  345
- UART Input Port Register (Uipn)
  345
- UART Output Port Command Registers (Uop1N/Uop0N)
  346
- Functional Description
  346
- Transmitter/Receiver Clock Source
  346
- Programmable Divider
  347
- Calculating Baud Rates
  347
- Internal Bus Clock Baud Rates
  347
- External Clock
  347
- Transmitter and Receiver Operating Modes
  347
- Transmitter
  348
- Receiver
  350
- Fifo
  351
- Looping Modes
  352
- Automatic Echo Mode
  352
- Local Loop-Back Mode
  352
- Remote Loop-Back Mode
  353
- Multidrop Mode
  353
- Bus Operation
  355
- Read Cycles
  355
- Write Cycles
  355
- Initialization/Application Information
  355
- Interrupt and DMA Request Initialization
  355
- Setting up the UART to Generate Core Interrupts
  355
- Setting up the UART to Request DMA Service
  356
- UART Module Initialization Sequence
  357
Chapter 22

363
- Introduction
  363
- Overview
  363
- Features
  364
- Memory Map/Register Definition
  365
- I 2 C Address Register (I2ADR)
  365
- I 2 C Frequency Divider Register (I2FDR)
  366
- I 2 C Control Register (I2CR)
  367
- I 2 C Status Register (I2SR)
  367
- I 2 C Data I/O Register (I2DR)
  369
- Functional Description
  369
- START Signal
  369
- Slave Address Transmission
  370
- Data Transfer
  370
- Acknowledge
  371
- STOP Signal
  371
- Repeated START
  371
- Clock Synchronization and Arbitration
  373
- Handshaking and Clock Stretching
  374
- Initialization/Application Information
  374
- Initialization Sequence
  374
- Generation of START
  374
- Post-Transfer Software Response
  375
- Generation of STOP
  375
- Generation of Repeated START
  376
- Slave Mode
  376
- Arbitration Lost
  376
Chapter 23 Analog-To-Digital Converter (ADC)

379
- Introduction
  379
- Features
  379
- Block Diagram
  380
- Memory Map and Register Definition
  380
- Control 1 Register (CTRL1)
  381
- Control 2 Register (CTRL2)
  383
- CTRL2 under Sequential Scan Modes
  383
- CTRL2 under Parallel Scan Modes
  384
- Zero Crossing Control Register (ADZCC)
  386
- Channel List 1 and 2 Registers (ADLST1 and ADLST2)
  386
- Sample Disable Register (ADSDIS)
  388
- Status Register (ADSTAT)
  389
- Limit Status Register (ADLSTAT)
  391
- Zero Crossing Status Register (ADZCSTAT)
  392
- Result Registers (Adrsltn)
  392
- Low and High Limit Registers (Adllmtn and Adhlmtn)
  393
- Offset Registers (Adofsn)
  395
- Power Control Register (POWER)
  395
- Voltage Reference Register (CAL)
  398
- Functional Description
  399
- Input MUX Function
  401
- ADC Sample Conversion
  403
- Single-Ended Samples
  404
- Differential Samples
  404
- ADC Data Processing
  405
- Sequential Vs. Parallel Sampling
  406
- Scan Sequencing
  407
- Scan Configuration and Control
  408
- Interrupt Sources
  410
- Power Management
  410
- Power Management Modes
  410
- Power Management Details
  411
- ADC STOP Mode of Operation
  412
- ADC Clock
  412
- General
  412
- Description of Clock Operation
  413
- ADC Clock Resynchronization at Start of Scan
  414
Chapter 24

417
- Introduction
  417
- Overview
  417
- Memory Map/Register Definition
  418
- PWM Enable Register (PWME)
  419
- PWM Polarity Register (PWMPOL)
  419
- PWM Clock Select Register (PWMCLK)
  420
- PWM Prescale Clock Select Register (PWMPRCLK)
  421
- PWM Center Align Enable Register (PWMCAE)
  422
- PWM Control Register (PWMCTL)
  422
- PWM Scale a Register (PWMSCLA)
  423
- PWM Scale B Register (PWMSCLB)
  424
- PWM Channel Counter Registers (Pwmcntn)
  425
- PWM Channel Period Registers (Pwmpern)
  426
- PWM Channel Duty Registers (Pwmdtyn)
  426
- PWM Shutdown Register (PWMSDN)
  427
- Functional Description
  428
- PWM Clock Select
  428
- Prescaled Clock (a or B)
  429
- Scaled Clock (SA or SB)
  430
- Clock Select
  430
- PWM Channel Timers
  430
- PWM Enable
  431
- PWM Polarity
  431
- PWM Period and Duty
  431
- PWM Timer Counters
  432
- Left-Aligned Outputs
  433
- Left-Aligned Output Example
  433
- Center-Aligned Outputs
  434
- Center-Aligned Output Example
  435
- PWM 16-Bit Functions
  435
- PWM Boundary Cases
  436
Chapter 25

439
- Introduction
  439
- Block Diagram
  439
- The CAN System
  440
- Features
  441
- Modes of Operation
  441
- Normal Mode
  441
- Freeze Mode
  441
- Module Disabled Mode
  442
- Loop-Back Mode
  442
- Listen-Only Mode
  443
- External Signal Description
  443
- Memory Map/Register Definition
  443
- Flexcan Configuration Register (CANMCR)
  444
- Flexcan Control Register (CANCTRL)
  446
- Flexcan Free Running Timer Register (TIMER)
  448
- Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)
  449
- Flexcan Error Counter Register (ERRCNT)
  450
- Flexcan Error and Status Register (ERRSTAT)
  451
- Interrupt Mask Register (IMASK)
  453
- Interrupt Flag Register (IFLAG)
  454
- Message Buffer Structure
  454
- Rx Individual Masking Registers (RXIMR0-15)
  458
- 25.3.11 Functional Overview
  458
- 25.3.12 Transmit Process
  458
- 25.3.13 Arbitration Process
  459
- 25.3.14 Receive Process
  460
- 25.3.14.1 Self-Received Frames
  461
- 25.3.15 Matching Process
  461
- 25.3.16 Message Buffer Handling
  461
- Serial Message Buffers (Smbs)
  461
- 25.3.16.2 Message Buffer Deactivation
  461
- 25.3.16.3 Locking and Releasing Message Buffers
  462
- 25.3.17 CAN Protocol Related Frames
  463
- 25.3.17.1 Remote Frames
  463
- 25.3.17.2 Overload Frames
  463
- 25.3.18 Time Stamp
  464
- 25.3.19 Bit Timing
  464
- Initialization/Application Information
  466
- Interrupts
  467
Chapter 26 Debug Module

469
- Introduction
  469
- Block Diagram
  469
- Overview
  469
- Signal Descriptions
  470
- Real-Time Trace Support
  471
- Begin Execution of Taken Branch (PST = 0X5)
  473
- Memory Map/Register Definition
  474
- Shared Debug Resources
  475
- Configuration/Status Register (CSR)
  475
- BDM Address Attribute Register (BAAR)
  478
- Address Attribute Trigger Register (AATR)
  478
- Trigger Definition Register (TDR)
  480
- Program Counter Breakpoint/Mask Registers (PBR0-3, PBMR)
  483
- Address Breakpoint Registers (ABLR, ABHR)
  485
- Data Breakpoint and Mask Registers (DBR, DBMR)
  486
- Background Debug Mode (BDM)
  487
- CPU Halt
  487
- BDM Serial Interface
  488
- Receive Packet Format
  489
- Transmit Packet Format
  490
- BDM Command Set
  490
- Coldfire BDM Command Format
  492
- Extension Words as Required
  492
- Command Sequence Diagrams
  493
- Command Set Descriptions
  494
- Read A/D Register (Rareg/Rdreg)
  494
- Write A/D Register (Wareg/Wdreg)
  495
- Read Memory Location (Read)
  495
- Write Memory Location (Write)
  497
- Dump Memory Block (Dump)
  498
- Fill Memory Block (Fill)
  500
- Resume Execution (Go)
  501
- No Operation (Nop)
  502
- Synchronize PC to the PST/DDATA Lines (Sync_Pc)
  502
- Read Control Register (Rcreg)
  503
- BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
  504
- Write Control Register (Wcreg)
  505
- Read Debug Module Register (Rdmreg)
  506
- Write Debug Module Register (Wdmreg)
  506
- Real-Time Debug Support
  507
- Theory of Operation
  507
- Emulator Mode
  509
- Concurrent BDM and Processor Operation
  509
- Processor Status, Debug Data Definition
  510
- User Instruction Set
  510
- Supervisor Instruction Set
  515
- Freescale-Recommended BDM Pinout
  515
Chapter 27 IEEE 1149.1 Test Access Port (JTAG)

517
- Introduction
  517
- Block Diagram
  517
- Features
  518
- Modes of Operation
  518
- External Signal Description
  518
- JTAG Enable (JTAG_EN)
  518
- Test Clock Input (TCLK)
  519
- Test Mode Select/Breakpoint (TMS/BKPT)
  519
- Test Data Input/Development Serial Input (TDI/DSI)
  519
- Test Reset/Development Serial Clock (TRST/DSCLK)
  520
- Test Data Output/Development Serial Output (TDO/DSO)
  520
- Memory Map/Register Definition
  520
- Instruction Shift Register (IR)
  520
- IDCODE Register
  520
- Bypass Register
  521
- JTAG_CFM_CLKDIV Register
  521
- TEST_CTRL Register
  521
- Boundary Scan Register
  522
- Functional Description
  522
- JTAG Module
  522
- TAP Controller
  522
- JTAG Instructions
  523
- IDCODE Instruction
  524
- SAMPLE/PRELOAD Instruction
  524
- EXTEST Instruction
  525
- TEST_LEAKAGE Instruction
  525
- ENABLE_TEST_CTRL Instruction
  525
- HIGHZ Instruction
  525
- 27.4.3.7 LOCKOUT_RECOVERY Instruction
  525
- CLAMP Instruction
  526
- BYPASS Instruction
  526
- Initialization/Application Information
  526
- Restrictions
  526
- Nonscan Chain Operation
  526

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Table of Contents

Paragraph Number

About this Book

Chapter 1 Overview

Chapter 2 Signal Descriptions

Chapter 3 Coldfire Core

Chapter 4 Multiply-Accumulate Unit (MAC)

Chapter 5 Static RAM (SRAM)

Chapter 6 Clock Module

Chapter 7 Power Management

Chapter 8 Chip Configuration Module (CCM)

Chapter 9 Reset Controller Module

Chapter 10 System Control Module (SCM)

Chapter 11 General Purpose I/O Module

Chapter 12 Interrupt Controller Module

Chapter 13 Edge Port Module (EPORT)

Chapter 14 DMA Controller Module

Chapter 15 Coldfire Flash Module (CFM)

Chapter 16

Chapter 17 Programmable Interrupt Timers (PIT0-PIT1)

Chapter 18 General Purpose Timer Module (GPT)

Chapter 19 DMA Timers (DTIM0-DTIM3)

Chapter 20 Queued Serial Peripheral Interface (QSPI)

Chapter 21 UART Modules

Chapter 22

Chapter 23 Analog-To-Digital Converter (ADC)

Chapter 24

Chapter 25

Chapter 26 Debug Module

Chapter 27 IEEE 1149.1 Test Access Port (JTAG)

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