Freescale Semiconductor MC9S12C Family Reference Manual

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MC9S12C Family

MC9S12GC Family

Reference Manual

HCS12

Microcontrollers

MC9S12C128

Rev 01.24

05/2010

freescale.com

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Page 1 MC9S12C Family MC9S12GC Family Reference Manual HCS12 Microcontrollers MC9S12C128 Rev 01.24 05/2010 freescale.com...
Page 2 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices.
Page 3: Table Of Contents
Appendix D Derivative Differences ....... 685 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 4 Appendix E Ordering Information ....... . 686 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 5 2.1.1 Features ............. . 73 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 6 4.4.2 Stretched Bus Cycles ........... 151 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 7 6.4.9 SYNC — Request Timed Reference Pulse ........187 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 8 8.3.2 Register Descriptions ........... 230 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 9 9.6.3 Self-Clock Mode Interrupt ..........286 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 10 12.1 Introduction ..............347 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 11 13.5.3 Recovery from Wait Mode ..........411 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 12 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin ....439 15.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin ....439 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 13 16.5.2 Low-Voltage Reset ........... . . 469 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 14 19.1.2 Features ............. 537 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 15 21.4.1 Flash Command Operations ..........630 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 16 C.1 General ..............681 Appendix D Derivative Differences Appendix E Ordering Information MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 17: Mc9S12C And Mc9S12Gc Device Overview (Mc9S12C128)
— DBG12 (enhanced debug12 module, including breakpoints and change-of-ﬂow trace buffer) — MEBI (multiplexed expansion bus interface) available only in 80-pin package version • Wake-up interrupt inputs: — Up to 12 port bits available for wake up interrupt function with digital ﬁltering Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 18 — One 8-channel module with 10-bit resolution — External conversion trigger capability • Available on MC9S12C Family: — One 1M bit per second, CAN 2.0 A, B software compatible module — Five receive and three transmit buffers — Flexible identiﬁer ﬁlter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit —...
Page 19 — Special single-chip mode with active background debug mode — Special test mode (Freescale use only) — Special peripheral mode (Freescale use only) • Low power modes: — Stop mode — Pseudo stop mode — Wait mode Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 20 I/O Driver 5V Voltage Regulator 5V & I/O DD1,2 SS1,2 PLL 2.5V A/D Converter 5V is bonded internally to V DDPLL for 52- and 48-Pin packages SSPLL Figure 1-1. MC9S12C-Family / MC9S12GC-Family Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 21 Scalable controller area network (MSCAN) 0x0180–0x023F Reserved 0x0240–0x027F Port integration module (PIM) 0x0280–0x03FF Reserved 1. External memory paging is not supported on this device (Section 1.7.1, “PPAGE”). 2. Not available on MC9S12GC Family devices Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 22 The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is: 0x0000–0x03FF: Register Space 0x0000–0x0FFF: 4K RAM (only 3K visible 0x0400–0x0FFF) Flash erase sector size is 1024 bytes Figure 1-2. MC9S12C128 and MC9S12GC128 User Conﬁgurable Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 23 The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is: 0x0000–0x03FF: Register Space 0x0000–0x0FFF: 4K RAM (only 3K visible 0x0400–0x0FFF) Flash erase sector size is 1024 bytes Figure 1-3. MC9S12C96 and MC9S12GC96 User Conﬁgurable Memory Map Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 24 The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is: 0x0000–0x03FF: Register space 0x0000–0x0FFF: 4K RAM (only 3K visible 0x0400–0x0FFF) Flash erase sector size is 1024 Bytes Figure 1-4. MC9S12C64 and MC9S12GC64 User Conﬁgurable Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 25 The flash page 0x003E is visible at 0x4000–0x7FFF in the memory map if ROMHM = 0. In the figure ROMHM = 1 removing page 0x003E from 0x4000–0x7FFF. Figure 1-5. MC9S12C32 and MC9S12GC32 User Conﬁgurable Memory Map Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 26 The 16K ﬂash array page 0x003F is also visible in the PPAGE window when PPAGE register contents are odd. Flash Erase Sector Size is 512 Bytes Figure 1-6. MC9S12GC16 User Conﬁgurable Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 27 Read: 0x000B MODE MODC MODB MODA IVIS Write: Read: 0x000C PUCR PUPKE PUPEE PUPBE PUPAE Write: Read: 0x000D RDRIV RDPK RDPE RDPB RDPA Write: Read: 0x000E EBICTL ESTR Write: Read: 0x000F Reserved Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 28 Read: 0x0018 Reserved Write: 0x0019–0x0019 VREG3V3 (Voltage Regulator) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: LVDS $0019 VREGCTRL LVIE LVIF Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 29 0x0022 DBGTBH Write: Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0023 DBGTBL Write: Read: 0x0024 DBGCNT Write: Read: 0x0025 DBGCCX PAGSEL EXTCMP Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 30 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0032 Reserved Write: Read: $0033 Reserved Write: 1. Only applicable in special emulation-only bond outs, for emulation of extended memory map. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 31 Bit 8 0x0044 TCNT (hi) Write: Read: Bit 7 Bit 0 0x0045 TCNT (lo) Write: Read: 0x0046 TSCR1 TSWAI TSFRZ TFFCA Write: Read: 0x0047 TTOV TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 32 TC5 (lo) Bit 7 Bit 0 Write: Read: 0x005C TC6 (hi) Bit 15 Bit 8 Write: Read: 0x005D TC6 (lo) Bit 7 Bit 0 Write: Read: 0x005E TC7 (hi) Bit 15 Bit 8 Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 33 Read: 0x006E Reserved Write: Read: 0x006F Reserved Write: 0x0070–0x007F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0x0070– Reserved 0x007F Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 34 0x0090 ATDDR0H Write: Read: Bit7 Bit6 0x0091 ATDDR0L Write: Read: Bit15 Bit8 0x0092 ATDDR1H Write: Read: Bit7 Bit6 0x0093 ATDDR1L Write: Read: Bit15 Bit8 0x0094 ATDDR2H Write: Read: Bit7 Bit6 0x0095 ATDDR2L Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 35 Read: 0x00C9 SCIBDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Write: Read: 0x00CA SCICR1 LOOPS SCISWAI RSRC WAKE Write: Read: 0x00CB SCICR2 TCIE ILIE Write: Read: TDRE RDRF IDLE 0x00CC SCISR1 Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 36 SPIBR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Write: Read: SPIF SPTEF MODF 0x00DB SPISR Write: Read: 0x00DC Reserved Write: Read: 0x00DD SPIDR Bit7 Bit0 Write: Read: 0x00DE Reserved Write: Read: 0x00DF Reserved Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 37 Write: Read: $00F2 PWMPER0 Bit 7 Bit 0 Write: Read: $00F3 PWMPER1 Bit 7 Bit 0 Write: Read: $00F4 PWMPER2 Bit 7 Bit 0 Write: Read: $00F5 PWMPER3 Bit 7 Bit 0 Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 38 CANBTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 0x0144 CANRFLG WUPIF CSCIF OVRIF Write: Read: 0x0145 CANRIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 39 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0xXXX0 Standard ID Read: ID10 CANxRIDR0 Write: Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 0xXXX1 Standard ID Read: IDE=0 CANxRIDR1 Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 40 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Write: Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 0xxx1E CANxTTSRH Write: Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 0xxx1F CANxTTSRL Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 41 Read: 0x024F Reserved Write: Read: 0x0250 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 Write: Read: PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 0x0251 PTIM Write: Read: 0x0252 DDRM DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 42 Reserved Write: Read: 0x0263 Reserved Write: Read: 0x0264 Reserved Write: Read: 0x0265 Reserved Write: Read: 0x0266 Reserved Write: Read: 0x0267 Reserved Write: Read: 0x0268 PTJ7 PTJ6 Write: Read: PTIJ7 PTIJ6 0x0269 PTIJ Write: MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 43 0x027F Write: 0x0280–0x03FF Reserved Space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0x0280– Reserved 0x2FF Write: Read: 0x0300 Unimplemented –0x03FF Write: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 44 Control (MMC) Block Guide for further details. Table 1-4. Memory Size Registers Device Register Name Value MEMSIZ0 MC9S12GC16 MEMSIZ1 MEMSIZ0 MC9S12C32, MC9S12GC32 MEMSIZ1 MEMSIZ0 MC9S12C64, MC9S12GC64 MEMSIZ1 MEMSIZ0 MC9S12C96,MC9S12GC96 MEMSIZ1 MEMSIZ0 MC9S12C128, MC9S12GC128 MEMSIZ1 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 45 MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to Port T in an 80QFP option, the associated PWM channels are then mapped to both Port P and Port T Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 46 PAD04/AN04 MC9S12C-Family / PAD03/AN03 MC9S12GC-Family PAD02/AN02 IOC4/PT4 PAD01/AN01 IOC5/PT5 PAD00/AN00 IOC6/PT6 IOC7/PT7 MODC/BKGD * Signals shown in Bold italic are not available on the 48-pin package Figure 1-8. Pin Assignments in 52-Pin LQFP MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 47 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PAD07/AN07 PW3/IOC3/PT3 PAD06/AN06 PAD05/AN05 PAD04/AN04 MC9S12C-Family / MC9S12GC-Family PAD03/AN03 IOC4/PT4 PAD02/AN02 IOC5/PT5 PAD01/AN01 IOC6/PT6 PAD00/AN00 IOC7/PT7 MODC/BKGD XIRQ/PE0 Figure 1-9. Pin Assignments in 48-Pin LQFP Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 48 PP[6] KWP[6] ROMCTL Disabled PPSP enable. PERP/ Port P I/O pin, keypad wake-up, PW5 output PP[5] KWP[5] Disabled PPSP PERP/ Port P I/O pin, keypad wake-up, PWM output PP[4:3] KWP[4:3] PW[4:3] Disabled PPSP MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 49 This applies to the following pins: (48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2] Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 50 E-clock tags the high half of the instruction word being read into the instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 51 Figure 1-11. Colpitts Oscillator Connections (PE7 = 1) EXTAL Crystal or Ceramic Resonator XTAL SSPLL 1. RS can be zero (shorted) when used with higher frequency crystals, refer to manufacturer’s data. Figure 1-12. Pierce Oscillator Connections (PE7 = 0) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 52 This pin is also used as TAGLO in special expanded modes and is multiplexed with the LSTRB function. This pin is not available in the 48- / 52-pin package versions. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 53 MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. During MCU expanded modes of operation, this pin is used to enable Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 54 PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module if available. 1.3.4.26 PM0 / RXCAN — Port M I/O Pin 0 PM0 is a general purpose input or output pin and the receive pin, RXCAN, of the CAN module if available. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 55 . This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if V is tied to ground. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 56 MCU as possible. Bypass requirements depend on MCU pin load. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 57 ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 58 Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 59 (RTI) or watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full stop mode, but the wake up time from this mode is signiﬁcantly shorter. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 60 0xFFE4, 0xFFE5 Standard timer channel 5 I bit TIE (C5I) 0x00E4 0xFFE2, 0xFFE3 Standard timer channel 6 I bit TIE (C6I) 0x00E2 0xFFE0, 0xFFE1 Standard timer channel 7 I bit TIE (C7I) 0x00E0 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 61 0x008E 0xFF8C, 0xFF8D Reserved 0xFF8C, 0xFF8D PWM Emergency Shutdown I bit PWMSDN(PWMIE) 0x008C 0xFF8A, 0xFF8B VREG LVI I bit CTRL0 (LVIE) 0x008A 0xFF80 to 0xFF89 Reserved 1. Not available on MC9S12GC Family members Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 62 (except MC9S12GC16) Page 3E is also visible in the 0x4000–0x7FFF range if ROMHM is cleared and ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the 0x0000–0x3FFF range if ROMON is set... MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 63 In this reset state the pull-ups provide a deﬁned state and prevent a ﬂoating input, thereby preventing unnecessary current ﬂow at the input stage. To prevent unnecessary current ﬂow in production package options, the states of DDRK and PUPKE should not be changed by software. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 64 Furthermore in order to use a port AD pin as an analog input, the corresponding DDRAD bit must be cleared to conﬁgure the pin as an input MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 65 PLL loop ﬁlter resistor Pierce mode only R4 / R PLL loop ﬁlter resistor Quartz — — 1. In 48LQFP and 52LQFP package versions, V is not available. Thus 470nF must be connected to Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 66 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-15. Recommended PCB Layout (48 LQFP) Colpitts Oscillator MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 67 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-16. Recommended PCB Layout (52 LQFP) Colpitts Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 68 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-17. Recommended PCB Layout (80 QFP) Colpitts Oscillator MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 69 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-18. Recommended PCB Layout for 48 LQFP Pierce Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 70 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-19. Recommended PCB Layout for 52 LQFP Pierce Oscillator MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 71 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) Figure 1-20. Recommended PCB Layout for 80QFP Pierce Oscillator Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 72 Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 73: Chapter 2 Port Integration Module (Pim9C32)
5-V output drive with two selectable drive strength • 5-V digital and analog input • Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt inputs with glitch ﬁltering Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 74 Port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 75 Chapter 2 Port Integration Module (PIM9C32) Block Description when mapping PWM channels to Port T in an 80QFP option, the associated PWM channels are then mapped to both Port P and Port T. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 76 Port AD PAD[7:0] ATD[7:0] ATD analog inputs GPIO[7:0] General purpose I/O Port A PA[7:0] ADDR[15:8]/ Refer to MEBI Block Guide. DATA[15:8]/ GPIO Port B PB[7:0] ADDR[7:0]/ Refer to MEBI Block Guide. DATA[7:0]/ GPIO MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 77 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0x0005 PPST PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 1 of 3) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 78 — — PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 0x0019 PTIP = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 2 of 3) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 79 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 0x0035 PPSAD PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 0x0036– Reserved 0x003F = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 3 of 3) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 80 Output, reduced drive to 1 Disabled Rising edge 1. Applicable only on ports P and J. NOTE All bits of all registers in this module are completely synchronous to internal clocks during a register read. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 81 2. TIMEN[x] means that the timer is enabled (TSCR1[7]), the related channel is conﬁgured for output compare function (TIOS[x] or special output on a timer overﬂow event — conﬁgurable in TTOV[x]) and the timer output is routed to the port pin (TCTL1/TCTL2). Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 82 1 Associated pin is conﬁgured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 83 This bit has no effect if the port is used as output. Out of reset no pull device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 84 4–0 Module Routing Register Port T — This register selects the module connected to port T. MODRR[4:0] 0 Associated pin is connected to TIM module 1 Associated pin is connected to PWM module MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 85 3–0 Port S Input Register — This register always reads back the status of the associated pins. This also can be PTIS[3:0] used to detect overload or short circuit conditions on output pins. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 86 1 Associated pin is conﬁgured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 87 (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 88 (open-drain). A logic level of “1” is not driven. This bit has no inﬂuence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 89 5–0 Port M Input Register — This register always reads back the status of the associated pins. This also can be PTIM[5:0] used to detect overload or short circuit conditions on output pins. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 90 1 Associated pin is conﬁgured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 91 (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 92 (open-drain). A logic level of “1” is not driven. This bit has no inﬂuence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 93 Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be also used to detect overload or short circuit conditions on output pins. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 94 Reduced Drive Port P — This register conﬁgures the drive strength of each port P output pin as either full or RDRP[7:0] reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 95 1 Rising edge on the associated port P pin sets the associated ﬂag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 96 Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated ﬂag. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 97 Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 98 Reduced Drive Port J — This register conﬁgures the drive strength of each port J output pin as either full or RDRJ[7:6] reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 99 1 Rising edge on the associated port J pin sets the associated ﬂag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 100 Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated ﬂag. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 101 Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 102 Reduced Drive Port AD — This register conﬁgures the drive strength of each port AD output pin as either full RDRAD[7:0] or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 103 1 A pull-down device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD and if the port is used as input. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 104 Data Direction Register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-46). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 105 DDRD[n] must be set NOTE: To use PORTAD[n], located in the ATD as an input port register, DDRD[n] must be cleared and ATDDIEN[n] must be set. Please refer to ATD Block Guide for details. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 106 < 10 pulse pulse µs Valid >= 4 Bus clocks >= 10 pval pval 1. These values include the spread of the oscillator frequency over temperature, voltage and process. pulse Figure 2-48. Pulse Illustration MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 107 The reset values of all registers are given in Section 2.3.2, “Register Descriptions”. 2.5.1 Reset Initialization All registers including the data registers get set/reset asynchronously. Table 2-39 summarizes the port properties after reset initialization. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 108 Power consumption will increase the more the voltages on general purpose input pins deviate from the supply voltages towards mid-range because the digital input buffers operate in the linear region. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 109: Chapter 3 Module Mapping Control (Mmcv4)
The MMC is the sub-module which controls memory map assignment and selection of internal resources and external space. Internal buses between the core and memories and between the core and peripherals is controlled in this module. The memory expansion is generated in this module. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 110 Initialization of Internal RAM Position Register (INITRM) 0x0011 Initialization of Internal Registers Position Register (INITRG) 0x0012 Initialization of Internal EEPROM Position Register (INITEE) 0x0013 Miscellaneous System Control Register (MISC) 0x0014 Reserved — — MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 111 Table 3-1. MMC Memory Map (continued) Address Register Access Offset 0x0017 Reserved — — 0x001C Memory Size Register 0 (MEMSIZ0) 0x001D Memory Size Register 1 (MEMSIZ1) 0x0030 Program Page Index Register (PPAGE) 0x0031 Reserved — Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 112 0x001C R REG_SW0 EEP_SW1 EEP_SW0 RAM_SW2 RAM_SW1 RAM_SW0 MEMSIZ0 0x001D R ROM_SW1 ROM_SW0 PAG_SW1 PAG_SW0 MEMSIZ1 0x0030 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 PPAGE 0x0031 Reserved = Unimplemented Figure 3-2. MMC Register Summary MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 113 RAM High-Align — RAMHAL speciﬁes the alignment of the internal RAM array. RAMHAL 0 Aligns the RAM to the lowest address (0x0000) of the mappable space 1 Aligns the RAM to the higher address (0xFFFF) of the mappable space Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 114 Internal Register Map Position — These four bits in combination with the leading zero supplied by bit 7 of REG[14:11] INITRG determine the upper ﬁve bits of the base address for the system’s internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7FFF). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 115 Enable EEPROM — This bit is used to enable the EEPROM memory in the memory map. EEON 0 Disables the EEPROM from the memory map. 1 Enables the EEPROM in the memory map at the address selected by EE[15:11]. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 116 This bit is used to enable the FLASH EEPROM or ROM memory in the memory map. 0 Disables the FLASH EEPROM or ROM from the memory map. 1 Enables the FLASH EEPROM or ROM in the memory map. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 117 Starting address location affected by INITRG register setting. Reset = Unimplemented or Reserved Figure 3-8. Reserved Test Register 1 (MTST1) Read: Anytime Write: No effect — this register location is used for internal test purposes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 118 Table 3-9. Allocated RAM Memory Space Allocated INITRM RAM Reset ram_sw2:ram_sw0 RAM Space Mappable Region Bits Used Base Address 2K bytes 2K bytes RAM[15:11] 0x0800 4K bytes 4K bytes RAM[15:12] 0x0000 6K bytes 8K bytes RAM[15:13] 0x0800 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 119 The MEMSIZ1 register reﬂects the state of the FLASH or ROM physical memory space and paging switches at the core boundary which are conﬁgured at system integration. This register allows read visibility to the state of these switches. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 120 The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 121 Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM PIX[5:0] array pages is to be accessed in the program page window as shown in Table 3-14. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 122 Select Priority and Mode Considerations Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers, MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 123 XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 124 The partitioning as deﬁned in Table 3-17 applies only to the allocated memory space and the actual on-chip memory sizes implemented in the system may differ. Please refer to the device overview chapter for actual sizes. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 125 The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and reﬁlls the queue. Execution resumes with the next instruction after the CALL. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 126 Page Window Access ROMHM XAB19:14 0x0000–0x3FFF 0x3D 0x4000–0x7FFF 0x3E 0x8000–0xBFFF PIX[5:0] 0xC000–0xFFFF 0x3F Table 3-19. 16K Byte Physical FLASH/ROM Allocated Address Space Page Window Access ROMHM XAB19:14 0x0000–0x3FFF 0x3D 0x4000–0x7FFF 0x3E 0x8000–0xBFFF PIX[5:0] 0xC000–0xFFFF 0x3F MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 127 0x3D 0x4000–0x7FFF 0x3E 0x8000–0xBFFF External PIX[5:0] Internal 0xC000–0xFFFF 0x3F Table 3-21. 64K Byte Physical FLASH/ROM Allocated Address Space Page Window Access ROMHM XAB19:14 0x0000–0x3FFF 0x3D 0x4000–0x7FFF 0x3E 0x8000–0xBFFF External PIX[5:0] Internal 0xC000–0xFFFF 0x3F Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 128 These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register. 16K FLASH (UNPAGED) 0xFF00 VECTORS 0xFFFF NORMAL SINGLE CHIP Figure 3-12. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 129: Chapter 4 Multiplexed External Bus Interface (Mebiv3)
Control register to enable/disable reduced output drive on ports A, B, E, and K • Control register to conﬁgure external clock behavior • Control register to conﬁgure IRQ pin operation • Logic to capture and synchronize external interrupt pin inputs Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 130 IRQ interrupt XIRQ interrupt PE0/XIRQ IRQ CTL TAG CTL BDM tag info BKGD BKGD/MODC/TAGHI mode Control signal(s) Data signal (unidirectional) Data signal (bidirectional) Data bus (unidirectional) Data bus (bidirectional) Figure 4-1. MEBI Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 131 • Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals. External Signal Description In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins.
Page 132 At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. IPIPE0 Instruction pipe status bit 0, enabled by PIPOE bit in PEAR. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 133 On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 134 Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and AB9 and AB8 and DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2 DB9/DB1 DB8/DB0 Figure 4-2. Port A Data Register (PORTA) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 135 NOTE To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 136 It is reset to 0x00 so the DDR does not override the three-state control signals. Table 4-3. DDRA Field Descriptions Field Description Data Direction Port A DDRA 0 Conﬁgure the corresponding I/O pin as an input 1 Conﬁgure the corresponding I/O pin as an output MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 137 It is reset to 0x00 so the DDR does not override the three-state control signals. Table 4-4. DDRB Field Descriptions Field Description Data Direction Port B DDRB 0 Conﬁgure the corresponding I/O pin as an input 1 Conﬁgure the corresponding I/O pin as an output Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 138 Starting address location affected by INITRG register setting. Reset = Unimplemented or Reserved Figure 4-8. Reserved Register Module Base + 0x0007 Starting address location affected by INITRG register setting. Reset = Unimplemented or Reserved Figure 4-9. Reserved Register MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 139 It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from being inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 140 Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 141 In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and R/W are conﬁgured out of reset as bus control signals. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 142 Note: R/W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra I/O pin. If R/W is needed it should be enabled before any external writes. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 143 Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 144 Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 145 The polarity of these pull resistors is determined by chip integration. Please refer to the device overview chapter to determine the polarity of these resistors. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 146 The reduced drive function is independent of which function is being used on a particular port. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 147 Special: write anytime 0 E never stretches (always free running). 1 E stretches high during stretched external accesses and remains low during non-visible internal accesses. This bit has no effect in single-chip modes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 148 Normal, emulation, and special modes: read or write anytime 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. Note: When IRQEN = 0, the edge detect latch is disabled. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 149 They can be viewed as expanded addresses XAB19–XAB14 of the 20-bit address used to access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for general-purpose I/O depending upon the state of the EMK bit in the MODE register. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 150 Table 4-15. Access Type vs. Bus Control Pins LSTRB Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write of an even address 8-bit write of an odd address MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 151 Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conﬂicts (must not be used) Normal Expanded Wide, BDM allowed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 152 Port E, bit 4 can be conﬁgured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 153 LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 154 I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 155 Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 156 Operation in Wait Mode The MEBI does not contain any options for reducing power in wait mode. 4.4.5.3 Operation in Stop Mode The MEBI will cease to function after execution of a CPU STOP instruction. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 157: Chapter 5 Interrupt (Intv1)
HIGHEST PRIORITY I-INTERRUPT INTERRUPTS INTERRUPT INPUT REGISTERS READ DATA BUS XMASK AND CONTROL REGISTERS IMASK WAKEUP QUALIFIED INTERRUPTS INTERRUPT PENDING RESET FLAGS PRIORITY DECODER VECTOR REQUEST VECTOR ADDRESS Figure 5-1. INTV1 Block Diagram Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 158 Interrupts may be tested in special modes through the use of the interrupt test registers. • Emulation modes The INT operates the same in emulation modes as in normal modes. • Low power modes Section 5.4.1, “Low-Power Modes,” for details MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 159 Starting address location affected by INITRG register setting. WRTINT ADR3 ADR2 ADR1 ADR0 Reset = Unimplemented or Reserved Figure 5-2. Interrupt Test Control Register (ITCR) Read: See individual bit descriptions Write: See individual bit descriptions Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 160 (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always return 0s in normal modes. Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 161 The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 162 I interrupt. The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces the promoted interrupt source. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 163 Crystal monitor reset 0xFFFA–0xFFFB COP reset 0xFFF8–0xFFF9 Unimplemented opcode trap 0xFFF6–0xFFF7 Software interrupt instruction (SWI) or BDM vector request 0xFFF4–0xFFF5 XIRQ signal 0xFFF2–0xFFF3 IRQ signal 0xFFF0–0xFF00 Device-speciﬁc I-bit maskable interrupt sources (priority in descending order) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 164 Chapter 5 Interrupt (INTV1) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 165: Chapter 6 Background Debug Module (Bdmv4)
BDMV4: SYNC command to determine communication rate • BDMV4: GO_UNTIL command • BDMV4: Hardware handshake protocol to increase the performance of the serial communication • Active out of reset in special single-chip mode Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 166 If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 167 This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 168 Table 6-1. INT Memory Map Register Access Address 0xFF00 Reserved — 0xFF01 BDM Status Register (BDMSTS) 0xFF02– Reserved — 0xFF05 0xFF06 BDM CCR Holding Register (BDMCCR) 0xFF07 BDM Internal Register Position (BDMINR) 0xFF08– Reserved — 0xFF0B MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 169 0xFF07 REG14 REG13 REG12 REG11 BDMINR 0xFF08 Reserved 0xFF09 Reserved 0xFF0A Reserved 0xFF0B Reserved = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 6-2. BDM Register Summary Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 170 BDM hardware or standard ﬁrmware lookup table as part of BDM command execution. • ENBDM should only be set via a BDM hardware command if the BDM ﬁrmware commands are needed. (This does not apply in special single-chip mode). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 171 ﬁrst recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 172 Table 6-3. BDM Clock Sources PLLSEL CLKSW BDMCLK Bus clock Bus clock Alternate clock (refer to the device overview chapter to determine the alternate clock source) Bus clock dependent on the PLL MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 173 BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the ﬁrst 32K bytes of the 64K byte address space. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 174 ﬁrmware in the standard BDM ﬁrmware lookup table. When BDM is activated by the breakpoint sub- 1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a breakpoint or a debug sub-block. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 175 CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 176 BDM ﬁrmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM ﬁrmware lookup table and BDM registers become visible in the on-chip memory map at 0xFF00–0xFFFF, and the CPU begins executing the standard BDM MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 177 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 178 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 6.4.6, “BDM Serial Interface,” Section 6.3.2.1, “BDM Status Register (BDMSTS),” for information on how serial clock rate is selected. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 179 The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 180 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 181 DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 6-9. BDM Target-to-Host Serial Bit Timing (Logic 0) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 182 If the CPU enters WAIT or STOP prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 183 This means that in the case of a WAIT or STOP instruction being executed, the ACK would be prevented from being issued. If not aborted, the ACK would remain pending indeﬁnitely. See the handshake abort procedure described in Section 6.4.8, “Hardware Handshake Abort Procedure.” Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 184 SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. NOTE Figure 6-12 does not represent the signals in a true timing scale MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 185 It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 186 The ACK pulse related to this command could be aborted using the SYNC command. The TAGGO command will not issue an ACK pulse because this would interfere with the tagging function shared on the same pin. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 187 BDM ﬁrmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 188 If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 189 As the clocks restart from stop mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 190 Chapter 6 Background Debug Module (BDMV4) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 191: Chapter 7 Debug Module (Dbgv1)
— Compare on any 16K page (page) • At forced breakpoints compare address on read or write • High and/or low byte data compares • Comparator C can provide an additional tag or force breakpoint (enhancement for BKP mode) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 192 — Source address of taken conditional branches (long, short, bit-conditional, and loop constructs) — Destination address of indexed JMP, JSR, and CALL instruction. — Destination address of RTI, RTS, and RTC instructions — Vector address of interrupts, except for SWI and BDM vectors MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 193 — Proﬁle: poll target from external device 7.1.3 Block Diagram Figure 7-1 is a block diagram of this module in breakpoint mode. Figure 7-2 is a block diagram of this module in debug mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 194 DATA HIGH DATA/ADDRESS BKP1H COMPARATOR ADDRESS HIGH HIGH MUX DATA LOW DATA/ADDRESS ADDRESS LOW BKP1L COMPARATOR LOW MUX READ DATA HIGH COMPARATOR READ DATA LOW COMPARATOR Figure 7-1. DBG Block Diagram in BKP Mode MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 195 In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 196 However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are DBGEN and ARM Name Bit 7 Bit 0 0x0020 DBGEN TRGSEL BEGIN DBGBRK CAPMOD DBGC1 0x0021 DBGSC = Unimplemented or Reserved Figure 7-3. DBG Register Summary MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 197 Bit 7 Bit 0 BKP0L 0x002D DBGCBX PAGSEL EXTCMP BKP1X 0x002E DBGCBH Bit 15 Bit 8 BKP1H 0x002F DBGCBL Bit 7 Bit 0 BKP1L = Unimplemented or Reserved Figure 7-3. DBG Register Summary (continued) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 198 Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace BEGIN buffer. See Section 7.4.2.8.1, “Storing with Begin-Trigger,” and Section 7.4.2.8.2, “Storing with End-Trigger,” for more details. 0 Trigger at end of stored data 1 Trigger before storing data MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 199 CPU on each access of trace buffer address. Refer to Section 7.4.2.6, “Capture Modes,” for more information. Table 7-4. CAPMOD Encoding CAPMOD Description Normal LOOP1 DETAIL PROFILE Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 200 0100 A then event only B 0101 A and B (full mode) 0110 A and Not B (full mode) 0111 Inside range 1000 Outside range 1001 Reserved ↓ (Defaults to A only) 1111 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 201 (See Section 7.4.2.9, “Reading Data from Trace Buffer”). Because reads will reﬂect the contents of the trace buffer RAM, the reset state is undeﬁned. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 202 64 words valid; if BEGIN = 1, the ARM bit will be cleared. A breakpoint will be generated if DBGBRK = 1 000001 64 words valid, oldest data has been overwritten by most recent data 111111 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 203 2. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00. 3. Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra space. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 204 Starting address location affected by INITRG register setting. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset = Unimplemented or Reserved Figure 7-12. Debug Comparator C Register Low (DBGCCL) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 205 Background Debug Mode Enable — This bit determines if the breakpoint causes the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). 0 Go to software interrupt on a break request 1 Go to BDM on a break request Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 206 1. In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s. 2. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data. Figure 7-14. Debug Control Register 3 (DBGC3) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 207 Read/Write Comparator A Value Bit — The RWA bit controls whether read or write is used in compare for comparator A. The RWA bit is not used if RWAEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 208 Table 7-18. Breakpoint Mask Bits for Data Breakpoints (Full Mode) BKBMBH:BKBMBL Data Compare DBGCBX DBGCBH DBGCBL High and low byte compare High byte Low byte No compare 1. Expansion addresses for breakpoint B are not applicable in this mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 209 DBGCxH[7:0] = XAB[15:14], AB[13:8] 1. See Figure 7-16. 2. See Figure 7-10 (note that while this ﬁgure provides extended comparisons for comparator C, the ﬁgure also pertains to comparators A and B in DBG mode only). Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 210 15:0 address bus bits [15:0] to a logic 1 or logic 0. See Table 7-20. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 211 Starting address location affected by INITRG register setting. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset Figure 7-20. Debug Comparator B Register High (DBGCBH) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 212 When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 213 This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the breakpoint sub-block. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 214 DBGCBH and DBGCBL. Comparator C can be used as a breakpoint generator or as the address comparison unit in the loop1 mode. Matches on comparator A, B, and C are signaled to the trace buffer MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 215 The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also determines whether a request to break the CPU should occur. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 216 B may not complete the trigger sequence. This occurs when A and B are in the instruction queue at the same time. Basically the A trigger has not yet occurred, so the B instruction is not tagged. Generally, if address B is at MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 217 (and thus will cause a trigger in this mode) unless the access is to a RAM that manages misaligned accesses in a single clock cycle. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 218 3 — Reduces to effectively “B only” 4 — Works same as A then B 5 — Reduces to effectively “A only” — B not compared 6 — Only accurate to word boundaries MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 219 Loop1 mode does not support paged memory, and inhibits duplicate entries in the trace buffer based solely on the CPU address. There is a remote possibility of an erroneous address match if program ﬂow alternates between paged and unpaged memory space. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 220 When the trigger condition is met, the DBG module will become de-armed and no more data will be stored. If MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 221 The type of breakpoint based on comparators A and B is determined by TRGSEL in the DBGC1 register (TRGSEL = 1 for tagged breakpoint, TRGSEL = 0 for forced breakpoint). Table 7-26 illustrates the type of breakpoint that will occur based on the debug run. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 222 The DBG module is disabled after reset. The DBG module cannot cause a MCU reset. Interrupts The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an SWI interrupt will be generated. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 223: Chapter 8 Analog-To-Digital Converter (Atd10B8C)
• Continuous conversion mode. • Multiple channel scans. 8.1.2 Modes of Operation 8.1.2.1 Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 224 SAMPLE & HOLD AN4 / PAD4 – AN3 / PAD3 COMPARATOR AN2 / PAD2 AN1 / PAD1 AN0 / PAD0 ATD INPUT ENABLE REGISTER ANALOG PORT AD DATA REGISTER Figure 8-1. ATD10B8C Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 225 This pin serves as the analog input channel 0. It can be conﬁgured as general-purpose digital I/O. 8.2.9 is the high reference voltage and V is the low reference voltage for ATD conversion. 8.2.10 These pins are the power supplies for the analog circuitry of the ATD10B8C block. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 226 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 0x000E Unimplemented PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x000F PORTAD = Unimplemented or Reserved Figure 8-2. ATD Register Summary (Sheet 1 of 4) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 227 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0x001C ATDDR6H BIT 1 BIT 0 0x001D ATDDR6L = Unimplemented or Reserved Figure 8-2. ATD Register Summary (Sheet 2 of 4) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 228 BIT 0 BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0x001B ATDDR5L = Unimplemented or Reserved Figure 8-2. ATD Register Summary (Sheet 3 of 4) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 229 Figure 8-2. ATD Register Summary (Sheet 4 of 4) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 230 = Unimplemented or Reserved Figure 8-4. Reserved Register (ATDCTL1) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 231 ATD conversions processes with external events. 0 Disable external trigger 1 Enable external trigger Note: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 232 Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-4 shows S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 S2C, S1C Family. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 233 Table 8-4. Conversion Sequence Length Coding Number of Conversions per Sequence Table 8-5. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 234 Table 8-7. Sample Time Select SMP1 SMP0 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 235 1. Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2. Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 236 In the case of multi-channel scans (MULT = 1), this selection code represents the ﬁrst channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 237 7FC0 FFC0 5.100 7F00 FF00 5.080 7E00 FE00 2.580 0100 8100 2.560 0000 8000 2.540 FF00 7F00 0.020 8100 0100 0.000 8000 0000 Table 8-12. Analog Input Channel Select Coding Analog Input Channel Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 238 B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 239 = Unimplemented or Reserved Figure 8-10. Reserved Register (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 240 Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result in unpredictable ATD behavior. Table 8-15. Special Channel Select Coding Analog Input Channel Reserved ) / 2 Reserved MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 241 B) If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx C) If AFFC = 1 and read of result register ATDDRx 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 242 Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 243 DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justiﬁed format. Signed data selected for right justiﬁed format is ignored. Read: Anytime Write: Anytime, no effect in normal modes Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 244 10-bit data BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-bit data Reset Figure 8-18. Right Justiﬁed, ATD Conversion Result Register, Low Byte (ATDDRxL) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 245 The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of V to V (A/D reference potentials) will result in a non-railed digital output codes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 246 ﬂag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 247 8.5.1.2 Step 2 Wait for the ATD Recovery Time before you proceed with Step 3. Example: Use the CPU in a branch loop to wait for a deﬁned number of bus clocks. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 248 Power down ATD by writing ADPU=0 in ATDCTL2. Resets At reset the ATD10B8C is in a power down state. The reset state of each individual bit is listed within Section 8.3.2, “Register Descriptions” which details the registers and their bit-ﬁeld. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 249 8-20. Refer to MCU speciﬁcation for related vector address and priority. Table 8-20. ATD10B8C Interrupt Vectors Interrupt Source Local Enable Mask Sequence complete interrupt I bit ASCIE in ATDCTL2 Section 8.3.2, “Register Descriptions” for further details. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 250 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 251: Chapter 9 Clocks And Reset Generator (Crgv4)
— Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 252 It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 9.1.3 Block Diagram Figure 9-1 shows a block diagram of the CRGV4. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 253 PLL. Refer to the device overview chapter for calculation of PLL loop ﬁlter (XFC) components. If PLL usage is not required the XFC pin must be tied to V DDPLL Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 254 0x000B CRG COP Arm/Timer Reset (ARMCOP) 1. CTFLG is intended for factory test purposes only. 2. FORBYP is intended for factory test purposes only. 3. CTCTL is intended for factory test purposes only. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 255 COPWAI CLKSEL 0x0006 PLLON AUTO SCME PLLCTL 0x0007 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 RTICTL 0x0008 WCOP RSBCK COPCTL 0x0009 FORBYP 0x000A CTCTL = Unimplemented or Reserved Figure 9-3. CRG Register Summary Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 256 = Unimplemented or Reserved Figure 9-4. CRG Synthesizer Register (SYNR) Read: anytime Write: anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 257 = Unimplemented or Reserved Figure 9-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRGV4 functionality. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 258 Track Status Bit — TRACK reﬂects the current state of PLL track condition. This bit is cleared in self-clock mode. TRACK Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 259 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self-Clock Mode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 260 While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 261 PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 262 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Reset = Unimplemented or Reserved Figure 9-11. CRG RTI Control Register (RTICTL) Read: anytime Write: anytime NOTE A write to this register initializes the RTI counter. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 263 1110 (÷15) OFF* 16x2 16x2 16x2 16x2 16x2 16x2 16x2 1111 (÷ 16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 264 (before time-out) reinitializing the COP counter via the ARMCOP register. Table 9-9. COP Watchdog Rates OSCCLK Cycles to Time Out COP disabled 1. OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x0055/0x00AA to the ARMCOP register) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 265 CRG’s functionality. Module Base + 0x000A Reset = Unimplemented or Reserved Figure 9-14. Reserved Register (CTCTL) Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 266 Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the speciﬁed bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 267 The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the ﬁnal reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 268 (ACQ = 0). • After entering tracking mode software must wait a given time (t ) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 269 SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 270 49999 50000 clock 1 2 3 4 5 4096 OSCCLK 4095 osc ok Figure 9-19. Check Window Example 1. VCO clock cycles are generated by the PLL when running at minimum frequency f MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 271 PLL (f ) and an active VREG during pseudo-stop mode or wait mode 1. A Clock Monitor Reset will always set the SCME bit to logical’1’ Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 272 RTI”). At the end of the RTI time-out period the RTIF ﬂag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 273 PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 9.4.4, “Clock Quality Checker” for more information on entering and leaving self-clock mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 274 CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit, disables the PLL, disables the core clocks and ﬁnally disables the remaining system clocks. As soon as all clocks are switched off wait mode is active. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 275 CM fail ext.RESET Exit Wait w. SCME=1 CMRESET Exit Wait Mode SCMIE=1 Generate SCM Interrupt SCM=1 (Wakeup from Wait) Exit Wait Mode Enter Enter Continue w. normal OP Figure 9-23. Wait Mode Entry/Exit Sequence Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 276 If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 9-11 summarizes the outcome of a clock loss while in wait mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 277 External RESET is applied. – Exit Wait Mode in SCM using PLL clock (f ) as system clock, – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 278 (PSTP = 0) is entered from self-clock mode an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 279 Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: • External reset • Clock monitor fail • Wake-up interrupt Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 280 MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 9-12 summarizes the outcome of a clock loss while in pseudo-stop mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 281 External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (f ) as system clock – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 282 The reset values of registers and signals are provided in Section 9.3, “Memory Map and Register MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 283 External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 284 If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055 or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 285 Figure 9-26. RESET Pin Tied to V (by a Pull-Up Resistor) Clock Quality Check RESET (no Self-Clock Mode) Internal POR 128 SYSCLK 64 SYSCLK Internal RESET Figure 9-27. RESET Pin Held Low Externally Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 286 SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt ﬂag (SCMIF) is set to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 287: Chapter 10 Scalable Controller Area Network (S12Mscanv2)
CPU bus: CPU related read/write data bus CAN bus: CAN protocol related serial bus oscillator clock: Direct clock from external oscillator bus clock: CPU bus realated clock CAN clock: CAN protocol related clock Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 288 Internal timer for time-stamping of received and transmitted messages • Three low-power modes: sleep, power down, and MSCAN enable • Global initialization of conﬁguration registers 1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 289 CAN bus and has current protection against defective CAN or defective stations. CAN node 2 CAN node n CAN node 1 CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 10-2. CAN System Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 290 MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 291 0x000E R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CANRXERR 0x000F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CANTXERR = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 292 The CANCTL0 register provides various control bits of the MSCAN module as described below. Module Base + 0x0000 RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Reset: = Unimplemented Figure 10-4. MSCAN Control Register 0 (CANCTL0) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 293 Wake-Up Enable — This conﬁguration bit allows the MSCAN to restart from sleep mode when trafﬁc on CAN is WUPE detected (see Section 10.4.5.4, “MSCAN Sleep Mode”). 0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN 1 Wake-up enabled — The MSCAN is able to restart Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 294 10. RSTAT1 and RSTAT0 are not affected by initialization mode. 10.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 295 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 296 CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running — The MSCAN operates normally 1 Initialization mode active — The MSCAN has entered initialization mode MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 297 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles Table 10-5. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 298 Time Segment 2 1 Tq clock cycle 2 Tq clock cycles 7 Tq clock cycles 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 10-34 for valid settings. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 299 Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are read- only; write of 1 clears ﬂag; write of 0 is ignored. 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 300 2. To ensure data integrity, do not read the receive buffer registers while the RXF ﬂag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF ﬂag is cleared may result in a CPU fault condition. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 301 CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 302 (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx ﬂags when not in initialization mode; write of 1 clears ﬂag, write of 0 is ignored MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 303 Table 10-12. CANTIER Register Field Descriptions Field Description Transmitter Empty Interrupt Enable TXEIE[2:0] 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 304 (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE ﬂag is set. 0 No abort request 1 Abort request pending MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 305 The ABTAKx ﬂag is cleared whenever the corresponding TXE ﬂag is cleared. 0 The message was not aborted. 1 The message was aborted. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 306 LDD CANTFLG; value read is 0b0000_0110 • STD CANTBSEL; value written is 0b0000_0110 • LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 307 Table 10-18. Identiﬁer Acceptance Hit Indication IDHIT2 IDHIT1 IDHIT0 Identiﬁer Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 308 = Unimplemented Figure 10-17. MSCAN Receive Error Counter (CANRXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 309 For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 310 Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits AC[7:0] of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 311 Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits AC[7:0] of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 312 If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identiﬁer bits 1 Ignore corresponding acceptance code register bit MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 313 If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identiﬁer bits 1 Ignore corresponding acceptance code register bit Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 314 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit priority registers are 0 out of reset. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 315 (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF ﬂag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 316 Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[28:21] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 317 Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[14:7] most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 318 ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 10-29. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 319 In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Module Base + 0x00X2 Reset: = Unused; always read ‘x’ Figure 10-31. Identiﬁer Register 2 — Standard Mapping Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 320 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7) Reset: Figure 10-33. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping Table 10-30. DSR0–DSR7 Register Field Descriptions Field Description Data bits 7:0 DB[7:0] MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 321 All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority ﬁeld wins the prioritization. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 322 TSR8 Reset: Figure 10-36. Time Stamp Register — High Byte (TSRH) Module Base + 0xXXXF TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Reset: Figure 10-37. Time Stamp Register — Low Byte (TSRL) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 323 “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 10.4 Functional Description 10.4.1 General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 324 CPU bus MSCAN PRIO TXE2 Transmitter PRIO Figure 10-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 325 The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 326 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF ﬂag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 327 Four identiﬁer acceptance ﬁlters, each to be applied to 1. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 328 IDR2 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 10-39. 32-bit Maskable Identiﬁer Acceptance Filter MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 329 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 10-40. 16-bit Maskable Identiﬁer Acceptance Filters Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 330 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 10-41. 8-bit Maskable Identiﬁer Acceptance Filters MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 331 The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 332 (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 10-43. Segments within the Bit Time MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 333 The MSCAN module behaves as described within this speciﬁcation in all normal system operation modes. 10.4.4.2 Special Modes The MSCAN module behaves as described within this speciﬁcation in all special system operation modes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 334 For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 335 The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a ﬁxed synchronization delay and its current activity: Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 336 If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 10-45). WUPE must be set before entering sleep mode to take effect. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 337 CAN Activity & Sleep Idle SLPRQ (CAN Activity & WUPE) | CAN Activity CAN Activity & CAN Activity SLPRQ Tx/Rx Message Active CAN Activity Figure 10-45. Simpliﬁed State Transitions for Entering/Leaving Sleep Mode Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 338 INITAK ﬂag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 339 Descriptions,” which details all the registers and their bit-ﬁelds. 10.4.7 Interrupts This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated ﬂags. Each interrupt is listed and described separately. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 340 CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx- warning, Tx/Rx-error, bus-off) the MSCAN ﬂags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT ﬂags (see Section 10.3.2.5, MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 341 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the conﬁguration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 342 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 343: Chapter 11 Oscillator (Oscv2)
Amplitude limitation controlled Colpitts oscillator mode suitable for power and emission critical applications • Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 344 EXTAL input frequency. In full stop mode (PSTP = 0) the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The Crystal circuit is changed from standard.
Page 345 XCLKS signal. Refer to the device overview chapter for polarity of the XCLKS pin. Table 11-1. Clock Selection Based on XCLKS XCLKS Description Colpitts oscillator selected Pierce oscillator/external clock selected Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 346 11.5 Interrupts OSCV2 contains a clock monitor, which can trigger an interrupt or reset. The control bits and status bits for the clock monitor are described in the CRG block description chapter. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 347: Chapter 12 Pulse-Width Modulator (Pwm8B6Cv1)
There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 348 PWM4 — Pulse Width Modulator Channel 4 Pin This pin serves as waveform output of PWM channel 4. 12.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin This pin serves as waveform output of PWM channel 3. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 349 PWM8B6CV1 module. NOTE Register address = base address + address offset, where the base address is deﬁned at the MCU level and the address offset is deﬁned at the module level. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 350 1. PWMTST is intended for factory test purposes only. 2. PWMPRSC is intended for factory test purposes only. 3. PWMSCNTA is intended for factory test purposes only. 4. PWMSCNTB is intended for factory test purposes only. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 351 Bit 0 PWMSCLB 0x000A PWMSCNTA 0x000B PWMSCNTB 0x000C Bit 7 Bit 0 PWMCNT0 0x000D Bit 7 Bit 0 PWMCNT1 0x000E Bit 7 Bit 0 PWMCNT2 = Unimplemented or Reserved Figure 12-2. PWM Register Summary Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 352 Bit 0 PWMPER3 0x001C Bit 7 Bit 0 PWMPER4 0x001D Bit 7 Bit 0 PWMPER5 0x001E PWM5IN PWMIF PWMIE PWMLVL PWM5INL PWM5ENA PWMSDB PWMRSTRT = Unimplemented or Reserved Figure 12-2. PWM Register Summary (continued) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 353 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 354 0 PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 355 NOTE Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 356 NOTE PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime. If the clock prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 357 If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference Section 12.4.2.5, “Left Aligned Outputs,” Section 12.4.2.6, “Center Aligned Outputs,” for a more detailed description of the PWM output modes. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 358 0 Channel 0 operates in left aligned output mode. 1 Channel 0 operates in center aligned output mode. 12.3.2.6 PWM Control Register (PWMCTL) The PWMCTL register provides for various control of the PWM module. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 359 0 registers become the high-order bytes of the double-byte channel. Reference Section 12.4.2.7, “PWM 16-Bit Functions,” for a more detailed description of the concatenation PWM function. NOTE Change these bits only when both corresponding channels are disabled. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 360 PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 361 = Unimplemented or Reserved Figure 12-10. Reserved Register (PWMPRSC) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 362 Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Module Base + 0x0009 Bit 7 Bit 0 Reset Figure 12-12. PWM Scale B Register (PWMSCLB) Read: anytime Write: anytime (causes the scale counter to load the PWMSCLB value). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 363 = Unimplemented or Reserved Figure 12-14. Reserved Register (PWMSCNTB) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 364 PWM cycle to occur. Module Base + 0x000C Bit 7 Bit 0 Reset Figure 12-15. PWM Channel Counter Registers (PWMCNT0) Module Base + 0x000D Bit 7 Bit 0 Reset Figure 12-16. PWM Channel Counter Registers (PWMCNT1) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 365 The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to 0x0000) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 366 Figure 12-21. PWM Channel Period Registers (PWMPER0) Module Base + 0x0013 Bit 7 Bit 0 Reset Figure 12-22. PWM Channel Period Registers (PWMPER1) Module Base + 0x0014 Bit 7 Bit 0 Reset Figure 12-23. PWM Channel Period Registers (PWMPER2) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 367 In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 368 Figure 12-27. PWM Channel Duty Registers (PWMDTY0) Module Base + 0x0019 Bit 7 Bit 0 Reset Figure 12-28. PWM Channel Duty Registers (PWMDTY1) Module Base + 0x001A Bit 7 Bit 0 Reset Figure 12-29. PWM Channel Duty Registers (PWMDTY2) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 369 The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. Module Base + 0x00E PWM5IN PWMIF PWMIE PWMLVL PWM5INL PWM5ENA PWMRSTRT Reset = Unimplemented or Reserved Figure 12-33. PWM Shutdown Register (PWMSDN) Read: anytime Write: anytime Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 370 PWM5ENA and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if PWM5ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 371 A is determined by the PCKA2, PCKA1, and PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, and PCKB0 bits also in the PWMPRCLK register. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 372 Clock B/2, B/4, B/6,..B/512 PCLK4 Count = 1 8-Bit Down Counter Clock to PWM Ch 5 Load Clock SB PCLK5 PWMSCLB DIV 2 PRESCALE SCALE CLOCK SELECT Figure 12-34. PWM Clock Select Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 373 Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 374 From Port PWMP 8-Bit Counter Data Register GATE PWMCNTx (clock edge sync) 8-Bit Compare = up/down reset PWMDTYx To Pin Driver 8-Bit Compare = PWMPERx PPOLx CAEx PWMEx Figure 12-35. PWM Timer Channel Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 375 When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 376 Counter Stops When PWMCNTx register When PWM channel is When PWM channel is written to any value enabled (PWMEx = 1). Counts disabled (PWMEx = 0) from last value in PWMCNTx. Effective period ends MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 377 Clock source = bus clock, where bus clock = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx frequency = 10 MHz/4 = 2.5 MHz PWMx period = 400 ns PWMx duty cycle = 3/4 *100% = 75% Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 378 PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx PWMPERx PWMPERx Period = PWMPERx*2 Figure 12-38. PWM Center Aligned Output Waveform MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 379 12-40. Similarly, when channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes of the double byte channel. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 380 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low-order CAEx bit. The high-order CAEx bit has no effect. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 381 PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA=1 or when PWMENA is being asserted while the level at PWM5 is active. A description of the registers involved and affected due to this interrupt is explained in Section 12.3.2.15, “PWM Shutdown Register (PWMSDN).” Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 382 Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 383: Chapter 13 Serial Communications Interface (S12Sciv2)
Separately enabled transmitter and receiver • Programmable transmitter output parity • Two receiver wake up methods: — Idle line wake-up — Address mark wake-up • Interrupt-driven operation with eight ﬂags: — Transmitter empty Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 384 SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 385 The SCI module has a total of two external pins: 13.2.1 TXD-SCI Transmit Pin This pin serves as transmit data output of SCI. 13.2.2 RXD-SCI Receive Pin This pin serves as receive data input of the SCI. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 386 ﬁgure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and ﬁeld function follow the register diagrams, in bit order. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 387 BR = 0. Writing to SCIBDH has no effect without writing to SCIBDL, since writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 388 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity 1 Odd parity MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 389 SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 390 TC is cleared in the event of a simultaneous set and clear of the TC ﬂag (transmission not complete). 0 Transmission in progress 1 No transmission in progress MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 391 (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 392 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 393 In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write ﬁrst to SCI data register high (SCIDRH), then SCIDRL. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 394 CONTROL IDLE SBR12–SBR0 RSRC RDRF BAUD RATE WAKE CLOCK GENERATOR DATA FORMAT CONTROL TO CPU TRANSMIT ÷16 LOOPS CONTROL TDRE RSRC TRANSMIT TCIE SHIFT REGISTER SCI DATA REGISTER Figure 13-9. SCI Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 395 A frame with nine data bits has a total of 11 bits. Table 13-9. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits 1. The address bit identiﬁes the frame as an address character. See Section 13.4.4.6, “Receiver Wakeup”. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 396 Target Baud Error SBR[12-0] Clock (Hz) Clock (Hz) Rate 609,756.1 38,109.8 38,400 308,642.0 19,290.1 19,200 153,374.2 9585.9 9600 76,687.1 4792.9 4800 38,402.5 2400.2 2400 1302 19,201.2 1200.1 1200 2604 9600.6 600.0 5208 4800.0 300.0 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 397 The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 398 When the transmit shift register is not transmitting a frame, the Tx output signal goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 399 If the TE bit is cleared during a transmission, the Tx output signal becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 400 The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 401 To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-11 summarizes the results of the start bit veriﬁcation samples. Table 13-11. Start Bit Veriﬁcation RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 402 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-13 summarizes the results of the stop bit samples. Table 13-13. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 403 RT8, RT9, and RT10 are within the bit time and data recovery is successful. PERCEIVED START BIT ACTUAL START BIT Rx Input Signal SAMPLES RT CLOCK RT CLOCK COUNT RESET RT CLOCK Figure 13-15. Start Bit Search Example 2 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 404 ﬂag. PERCEIVED AND ACTUAL START BIT Rx Input Signal SAMPLES RT CLOCK RT CLOCK COUNT RESET RT CLOCK Figure 13-17. Start Bit Search Example 4 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 405 ﬂag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. START BIT Rx Input Signal SAMPLES RT CLOCK RT CLOCK COUNT RESET RT CLOCK Figure 13-19. Start Bit Search Example 6 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 406 ((151 – 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 407 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 408 Address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames.{sci_wake} NOTE With the WAKE bit clear, setting the RWU bit after the Rx Input signal has been idle can cause the receiver to wake up immediately. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 409 The reset state of each individual bit is listed in Section 13.3, “Memory Map and Registers” which details the registers and their bit ﬁelds. All special functions or modes which are initialized during or just following reset are described within this section. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 410 There are ﬁve interrupt sources that can generate an SCI interrupt in to the CPU. They are listed in Table 13-14. Table 13-14. SCI Interrupt Source Interrupt Source Flag Local Enable Transmitter TDRE Transmitter TCIE Receiver RDRF Receiver IDLE ILIE MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 411 IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 13.5.3 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 412 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 413: Chapter 14 Serial Peripheral Interface (Spiv3)
This is a high level description only, detailed descriptions of operating modes are contained in Section 14.4, “Functional Description.” Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 414 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is conﬁgured as a master and receive data when it is conﬁgured as slave. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 415 Reserved — 0x0005 SPI Data Register (SPIDR) 0x0006 Reserved — 0x0007 Reserved — 1. Certain bits are non-writable. 2. Writes to this register are ignored. 3. Reading from this register returns all zeros. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 416 Figure 14-2. SPI Register Summary 14.3.2.1 SPI Control Register 1 (SPICR1) Module Base 0x0000 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE Reset Figure 14-3. SPI Control Register 1 (SPICR1) Read: anytime Write: anytime MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 417 SSOE Master Mode Slave Mode SS not used by SPI SS input SS not used by SPI SS input SS input with MODF feature SS input SS is slave select output SS input Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 418 Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 419 SPI system into idle state. The baud rate divisor equation is as follows: • BaudRateDivisor SPPR The baud rate can be calculated with the following equation: ⁄ Baud Rate BusClock BaudRateDivisor Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 420 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 1024 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 421 1792 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 1024 24.41 kHz 2048 12.21 kHz NOTE In slave mode of SPI S-clock speed DIV2 is not supported. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 422 1 Mode fault has occurred. 14.3.2.5 SPI Data Register (SPIDR) Module Base 0x0005 Bit 7 Bit 0 Reset = Unimplemented or Reserved Figure 14-7. SPI Data Register (SPIDR) Read: anytime; normally read only after SPIF is set MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 423 The SPI can be conﬁgured to operate as a master or as a slave. When the MSTR bit in SPI Control Register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 424 SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 425 SPI Data Register. To indicate transfer is complete, the SPIF ﬂag in the SPI Status Register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and has to be avoided. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 426 This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 427 SPI Data Register is not transmitted, instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions then the content of the SPI Data Register is transmitted. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 428 The SPI interrupt request ﬂag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 429 25-MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 430 Serial Out Serial In MOSI MOSI Normal Mode SPC0 = 0 Serial Out Serial In MISO MISO Serial In Serial Out MOMI Bidirectional Mode BIDIROE SPC0 = 1 BIDIROE Serial In Serial Out SISO MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 431 The mode fault ﬂag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault ﬂag is cleared, the SPI becomes a normal master or slave again. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 432 CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 433 SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is described in Section 14.3.2.4, “SPI Status Register (SPISR).” Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 434 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 435: Chapter 15 Timer Module (Tim16B8Cv1)
Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 15.1.1 Features The TIM16B8CV1 includes these distinctive features: • Eight input capture/output compare channels. • Clock prescaling. • 16-bit counter. • 16-bit pulse accumulator. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 436 Output compare Timer channel 7 Channel 6 interrupt Input capture IOC6 Output compare PA overflow Channel 7 interrupt 16-bit Input capture IOC7 Pulse accumulator Output compare PA input interrupt Figure 15-1. TIM16B8CV1 Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 437 Edge detector Interrupt PACNT M clock Divide by 64 Figure 15-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 15-3. Interrupt Flag Setting Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 438 This pin serves as input capture or output compare for channel 4. Pin 15.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin This pin serves as input capture or output compare for channel 3. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 439 15-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8CV1 module and the address offset for each register. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 440 1. Always read 0x0000. 2. Only writable in special modes (test_mode = 1). 3. Write to these registers have no meaning or effect during input capture. 4. Write has no effect; return 0 on read MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 441 TCTL1 0x0009 TCTL2 0x000A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4 0x000C = Unimplemented or Reserved Figure 15-5. TIM16B8CV1 Register Summary Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 442 Figure 15-5. TIM16B8CV1 Register Summary (continued) 15.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 Reset Figure 15-6. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 443 ﬂag won’t get set. 15.3.2.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 Reset Figure 15-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 444 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 Reset Figure 15-10. Timer Count Register High (TCNTH) Module Base + 0x0005 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 Reset Figure 15-11. Timer Count Register Low (TCNTL) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 445 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 446 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. 15.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 Reset Figure 15-14. Timer Control Register 1 (TCTL1) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 447 Table 15-11. The OC7 and OCx event priority OC7M7=0 OC7M7=1 OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0 TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx IOCx=OC7Dx IOCx=OC7Dx IOCx=OMx/OLx IOCx=OC7Dx IOCx=OC7Dx IOCx=OMx/OLx IOC7=OM7/O +OMx/OLx IOC7=OM7/OL7 IOC7=OC7D7 +OMx/OLx IOC7=OC7D7 IOC7=OM7/O IOC7=OC7D7 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 448 IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 449 Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector EDGnB circuits. EDGnA Table 15-13. Edge Detector Circuit Conﬁguration EDGnB EDGnA Conﬁguration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 450 ﬂag is enabled to cause a interrupt. 15.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D TCRE Reset = Unimplemented or Reserved Figure 15-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 451 The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 15.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E Reset Figure 15-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 452 Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while TEN bit of TSCR1 is set to one. (See also TCRE control bit explanation.) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 453 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 454 15-21. CLK[1:0] Pulse Accumulator Overﬂow Interrupt Enable PAOVI 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 455 When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the ﬂags in the PAFLG register. Timer module must stay enabled (TEN =1) while clearing thse bits. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 456 Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 register is set to one. Any access to the PACNT register will clear all the ﬂags in this register when TFFCA bit in register TSCR(0x0006) is set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 457 ﬁrst. 15.4 Functional Description This section provides a complete functional description of the timer TIM16B8CV1 block. Please refer to the detailed timer block diagram in Figure 15-28 as necessary. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 458 Figure 15-28. Detailed Timer Block Diagram 15.4.1 Prescaler The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 459 When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 460 PAOVI, enables the PAOVF ﬂag to generate interrupt requests. NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 461 15.6.1 Channel [7:0] Interrupt (C[7:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be serviced by the system controller. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 462 15.6.4 Timer Overﬂow Interrupt (TOF) This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced by the system controller. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 463: Chapter 16 Dual Output Voltage Regulator (Vreg3V3V2)
POR feature is available, LVD and LVR are disabled. This mode must be used to disable the chip internal regulator VREG3V3V2, i.e., to bypass the VREG3V3V2 to use external supplies. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 464 REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages. DDPLL REG2 SSPLL REG1 REGEN CTRL REG: Regulator Core LVD: Low Voltage Detect CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset Figure 16-1. VREG3V3 Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 465 Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between V and V can further improve the quality of this supply. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 466 This subsection provides a detailed description of all registers accessible in VREG3V3V2. 16.3.1 Module Memory Map Figure 16-2 provides an overview of all used registers. Table 16-2. VREG3V3V2 Memory Map Address Access Offset 0x0000 VREG3V3V2 Control Register (VREGCTRL) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 467 (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the interface to the digital core logic but also manages the operating modes of VREG3V3V2. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 468 16.4.7 CTRL — Regulator Control This part contains the register block of VREG3V3V2 and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 469 LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the Reduced Power Mode, the LVIF is not cleared by the VREG3V3V2. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 470 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 471: Chapter 17 16 Kbyte Flash Module (S12Fts16Kv1)
2-stage command pipeline for faster multi-word program times • Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 472 Buffer Empty sector 0 Interrupt sector 1 Registers Protection sector 31 Security Oscillator Clock Clock Divider FCLK Figure 17-1. FTS16K Block Diagram 17.2 External Signal Description FTS16K module contains no signals that connect off-chip. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 473 Flash Security/Options byte Refer to Section 17.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3F in the HCS12 Core PPAGE register, the 16 Kbyte page can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 474 Note: 0x3F corresponds to the PPAGE register content Figure 17-2. Flash Memory Map Table 17-2. Flash Array Memory Map Summary MCU Address Protectable PPAGE Range Address Range 0x8000–0xBFFF 0x3F 0xB800–0xBFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged 0xF800–0xFFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 475 0x0009 FABLO FADDRLO 0x000A FDHI FDATAHI 0x000B FDLO FDATALO 0x000C RESERVED3 0x000D RESERVED4 0x000E RESERVED5 0x000F RESERVED6 = Unimplemented or Reserved Figure 17-3. Flash Register Summary 1. Intended for factory test purposes only. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 476 All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash conﬁguration ﬁeld at 0xFF0F during the reset sequence, indicated by F in Figure 17-5. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 477 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 Reset = Unimplemented or Reserved Figure 17-6. RESERVED1 All bits read 0 and are not writable. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 478 The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPHS[1:0] can be written anytime until FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 17-8. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 479 Unprotected high range 1. For range sizes refer to Table 17-10. Table 17-10. Flash Protection Higher Address Range FPHS[1:0] Address Range Range Size 0xF800–0xFFFF 2 Kbytes 0xF000–0xFFFF 4 Kbytes 0xE000–0xFFFF 8 Kbytes 0xC000–0xFFFF 16 Kbytes Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 480 FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reﬂect the active protection scenario. Table 17-11. Flash Protection Scenario Transitions From To Protection Scenario Protection Scenario MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 481 Writing to the CCIF ﬂag has no effect. The CCIF ﬂag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 17-26). 0 Command in progress 1 All commands are completed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 482 Figure 17-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 483 All bits read 0 and are not writable. 17.3.2.9 Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 FABHI Reset = Unimplemented or Reserved Figure 17-13. Flash Address High Register (FADDRHI) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 484 FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 17.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 485 Module Base + 0x000E Reset = Unimplemented or Reserved Figure 17-19. RESERVED5 All bits read 0 and are not writable. 17.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 486 • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 487 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag in the FSTAT register will set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 488 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 FCLK > 0.15MHz FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE Figure 17-21. PRDIV8 and FDIV Bits Determination Procedure MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 489 Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 490 A mass erase of the full Flash array is only possible when FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 491 BLANK ﬂag in the FSTAT register will be set if all addresses in the Flash array are veriﬁed to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 492 Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check Erase Verify BLANK Status Set? Flash Array Flash Array EXIT EXIT Erased Not Erased Figure 17-22. Example Erase Verify Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 493 CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program operation. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 494 Read: FSTAT register Bit Polling for CBEIF Buffer Empty Set? Check Sequential Next Programming Decision Word? Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 17-23. Example Program Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 495 Once the sector erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 496 Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 17-24. Example Sector Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 497 Once the mass erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 498 Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 17-25. Example Mass Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 499 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL ﬂag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL ﬂag is cleared. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 500 Flash array, the MCU will be unsecured. The data must be written to the backdoor key MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 501 FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 502 CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 17-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 17.3.2.4, “Flash Conﬁguration Register (FCNFG)” Section 17.3.2.6, “Flash Status Register (FSTAT)”. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 503: Chapter 18 32 Kbyte Flash Module (S12Fts32Kv1)
2-stage command pipeline for faster multi-word program times • Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 504 Buffer Empty sector 0 Interrupt sector 1 Registers Protection sector 63 Security Oscillator Clock Clock Divider FCLK Figure 18-1. FTS32K Block Diagram 18.2 External Signal Description FTS32K module contains no signals that connect off-chip. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 505 Refer to Section 18.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top ﬁxed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 506 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x3E–0x3F correspond to the PPAGE register content Figure 18-2. Flash Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 507 0x18000–0x1BFFF (0x3E) 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 508 0x0009 FABLO FADDRLO 0x000A FDHI FDATAHI 0x000B FDLO FDATALO 0x000C RESERVED3 0x000D RESERVED4 0x000E RESERVED5 0x000F RESERVED6 = Unimplemented or Reserved Figure 18-3. Flash Register Summary 1. Intended for factory test purposes only. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 509 All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash conﬁguration ﬁeld at 0xFF0F during the reset sequence, indicated by F in Figure 18-5. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 510 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 Reset = Unimplemented or Reserved Figure 18-6. RESERVED1 All bits read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 511 The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 512 Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected FPLS[1:0] sector as shown in Table 18-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 513 Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 514 FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reﬂect the active protection scenario. Table 18-12. Flash Protection Scenario Transitions From To Protection Scenario Protection Scenario MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 515 Writing to the CCIF ﬂag has no effect. The CCIF ﬂag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 18-26). 0 Command in progress 1 All commands are completed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 516 Figure 18-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 517 All bits read 0 and are not writable. 18.3.2.9 Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 FABHI Reset = Unimplemented or Reserved Figure 18-13. Flash Address High Register (FADDRHI) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 518 FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 18.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 519 Module Base + 0x000E Reset = Unimplemented or Reserved Figure 18-19. RESERVED5 All bits read 0 and are not writable. 18.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 520 • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 521 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag in the FSTAT register will set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 522 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[ms]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ms])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ms])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[ms] > 5 FCLK > 0.15MHz FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE Figure 18-21. PRDIV8 and FDIV Bits Determination Procedure MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 523 Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 524 FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 525 BLANK ﬂag in the FSTAT register will be set if all addresses in the Flash array are veriﬁed to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 526 Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check Erase Verify BLANK Status Set? Flash Array Flash Array EXIT EXIT Erased Not Erased Figure 18-22. Example Erase Verify Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 527 CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program operation. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 528 Read: FSTAT register Bit Polling for CBEIF Buffer Empty Set? Check Sequential Next Programming Decision Word? Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 18-23. Example Program Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 529 Once the sector erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 530 Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 18-24. Example Sector Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 531 Once the mass erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 532 Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 18-25. Example Mass Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 533 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL ﬂag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL ﬂag is cleared. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 534 Flash array, the MCU will be unsecured. The data must be written to the backdoor key MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 535 FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 536 CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 18-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 18.3.2.4, “Flash Conﬁguration Register (FCNFG)” Section 18.3.2.6, “Flash Status Register (FSTAT)”. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 537: Chapter 19 64 Kbyte Flash Module (S12Fts64Kv4)
2-stage command pipeline for faster multi-word program times • Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 538 64K * 16 Bits addr2 addr1 Command data1 data2 Buffer Empty sector 0 Interrupt sector 1 Registers Protection sector 127 Security Oscillator Clock Clock Divider FCLK Figure 19-1. FTS128K1 Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 539 19-4. The HCS12 architecture places the Flash array addresses between 0x40000x4000 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 540 Refer to Section 19.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top ﬁxed 16 Kbyte pages can be seen twice in the MCU memory map. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 541 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x38–0x3F correspond to the PPAGE register content Figure 19-3. Flash Memory Map Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 542 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x3C–0x3F correspond to the PPAGE register content Figure 19-4. Flash Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 543 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 544 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 545 0x0009 FABLO FADDRLO 0x000A FDHI FDATAHI 0x000B FDLO FDATALO 0x000C RESERVED3 0x000D RESERVED4 0x000E RESERVED5 0x000F RESERVED6 = Unimplemented or Reserved Figure 19-5. Flash Register Summary 1. Intended for factory test purposes only. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 546 All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash conﬁguration ﬁeld at 0xFF0F during the reset sequence, indicated by F in Figure 19-7. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 547 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 Reset = Unimplemented or Reserved Figure 19-8. RESERVED1 All bits read 0 and are not writable. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 548 The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 549 Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected FPLS[1:0] sector as shown in Table 19-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 550 Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 551 FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reﬂect the active protection scenario. Table 19-13. Flash Protection Scenario Transitions From To Protection Scenario Protection Scenario Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 552 Writing to the CCIF ﬂag has no effect. The CCIF ﬂag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 19-29). 0 Command in progress 1 All commands are completed MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 553 Figure 19-13. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 554 All bits read 0 and are not writable. 19.3.2.9 Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 FABHI Reset Figure 19-15. Flash Address High Register (FADDRHI) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 555 In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 556 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E Reset = Unimplemented or Reserved Figure 19-22. RESERVED5 All bits read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 557 150-kHz to 200-kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we deﬁne: • FCLK as the clock of the Flash timing control block Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 558 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag in the FSTAT register will set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 559 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 FCLK > 0.15MHz FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE Figure 19-24. PRDIV8 and FDIV Bits Determination Procedure Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 560 Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 561 FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 562 BLANK ﬂag in the FSTAT register will be set if all addresses in the Flash array are veriﬁed to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 563 Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check Erase Verify BLANK Status Set? Flash Array Flash Array EXIT EXIT Erased Not Erased Figure 19-25. Example Erase Verify Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 564 CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program operation. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 565 Read: FSTAT register Bit Polling for CBEIF Buffer Empty Set? Check Sequential Next Programming Decision Word? Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 19-26. Example Program Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 566 Once the sector erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 567 Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 19-27. Example Sector Erase Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 568 Once the mass erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 569 Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 19-28. Example Mass Erase Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 570 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL ﬂag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL ﬂag is cleared. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 571 Flash array, the MCU will be unsecured. The data must be written to the backdoor key Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 572 FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 573 CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 19-29. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 19.3.2.4, “Flash Conﬁguration Register (FCNFG)” Section 19.3.2.6, “Flash Status Register (FSTAT)”. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 574 Chapter 19 64 Kbyte Flash Module (S12FTS64KV4) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 575: Chapter 20 96 Kbyte Flash Module (S12Fts96Kv1)
2-stage command pipeline for faster multi-word program times • Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 576 64K * 16 Bits addr2 addr1 Command data1 data2 Buffer Empty sector 0 Interrupt sector 1 Registers Protection sector 127 Security Oscillator Clock Clock Divider FCLK Figure 20-1. FTS128K1 Block Diagram MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 577 20-4. The HCS12 architecture places the Flash array addresses between 0x40000x4000 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 578 Refer to Section 20.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top ﬁxed 16 Kbyte pages can be seen twice in the MCU memory map. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 579 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x38–0x3F correspond to the PPAGE register content Figure 20-3. Flash Memory Map Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 580 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x3A–0x3F correspond to the PPAGE register content Figure 20-4. Flash Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 581 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 582 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 583 0x0009 FABLO FADDRLO 0x000A FDHI FDATAHI 0x000B FDLO FDATALO 0x000C RESERVED3 0x000D RESERVED4 0x000E RESERVED5 0x000F RESERVED6 = Unimplemented or Reserved Figure 20-5. Flash Register Summary 1. Intended for factory test purposes only. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 584 All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash conﬁguration ﬁeld at 0xFF0F during the reset sequence, indicated by F in Figure 20-7. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 585 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 Reset = Unimplemented or Reserved Figure 20-8. RESERVED1 All bits read 0 and are not writable. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 586 The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 587 Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected FPLS[1:0] sector as shown in Table 20-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 588 Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 589 FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reﬂect the active protection scenario. Table 20-13. Flash Protection Scenario Transitions From To Protection Scenario Protection Scenario Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 590 Writing to the CCIF ﬂag has no effect. The CCIF ﬂag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 20-28). 0 Command in progress 1 All commands are completed MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 591 Figure 20-13. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 592 All bits read 0 and are not writable. 20.3.2.9 Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 FABHI Reset Figure 20-15. Flash Address High Register (FADDRHI) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 593 FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 20.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 594 Module Base + 0x000E Reset = Unimplemented or Reserved Figure 20-21. RESERVED5 All bits read 0 and are not writable. 20.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 595 • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 596 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag in the FSTAT register will set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 597 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 FCLK > 0.15MHz FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE Figure 20-23. PRDIV8 and FDIV Bits Determination Procedure Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 598 Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 599 FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 600 BLANK ﬂag in the FSTAT register will be set if all addresses in the Flash array are veriﬁed to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 601 Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check Erase Verify BLANK Status Set? Flash Array Flash Array EXIT EXIT Erased Not Erased Figure 20-24. Example Erase Verify Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 602 CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program operation. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 603 Read: FSTAT register Bit Polling for CBEIF Buffer Empty Set? Check Sequential Next Programming Decision Word? Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 20-25. Example Program Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 604 Once the sector erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 605 Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 20-26. Example Sector Erase Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 606 Once the mass erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 607 Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 20-27. Example Mass Erase Command Flow Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 608 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL ﬂag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL ﬂag is cleared. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 609 Flash array, the MCU will be unsecured. The data must be written to the backdoor key Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family...
Page 610 FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 611 CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 20-28. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 20.3.2.4, “Flash Conﬁguration Register (FCNFG)” Section 20.3.2.6, “Flash Status Register (FSTAT)”. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 612 Chapter 20 96 Kbyte Flash Module (S12FTS96KV1) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 613: Chapter 21 128 Kbyte Flash Module (S12Fts128K1V1)
2-stage command pipeline for faster multi-word program times • Flexible protection scheme to prevent accidental program or erase • Single power supply for Flash program and erase operations • Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 614 Buffer Empty sector 0 Interrupt sector 1 Registers Protection sector 127 Security Oscillator Clock Clock Divider FCLK Figure 21-1. FTS128K1 Block Diagram 21.2 External Signal Description FTS128K1 module contains no signals that connect off-chip. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 615 Refer to Section 21.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top ﬁxed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 616 Flash Protected High Sectors 0xE000 0x3F 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Conﬁguration Field) Note: 0x38–0x3F correspond to the PPAGE register content Figure 21-2. Flash Memory Map MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 617 0x14000–0x17FFF 0x3E 0x8000–0x83FF N.A. 0x18000–0x1BFFF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0x1C000–0x1FFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged N.A. 0xF800–0xFFFF 0x1C000–0x1FFFF (0x3F) 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 618 0x0009 FABLO FADDRLO 0x000A FDHI FDATAHI 0x000B FDLO FDATALO 0x000C RESERVED3 0x000D RESERVED4 0x000E RESERVED5 0x000F RESERVED6 = Unimplemented or Reserved Figure 21-3. Flash Register Summary 1. Intended for factory test purposes only. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 619 All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash conﬁguration ﬁeld at 0xFF0F during the reset sequence, indicated by F in Figure 21-5. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 620 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 Reset = Unimplemented or Reserved Figure 21-6. RESERVED1 All bits read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 621 The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 622 Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected FPLS[1:0] sector as shown in Table 21-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 623 Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 624 FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reﬂect the active protection scenario. Table 21-12. Flash Protection Scenario Transitions From To Protection Scenario Protection Scenario MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 625 Writing to the CCIF ﬂag has no effect. The CCIF ﬂag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 21-26). 0 Command in progress 1 All commands are completed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 626 Figure 21-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 627 All bits read 0 and are not writable. 21.3.2.9 Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 FABHI Reset Figure 21-13. Flash Address High Register (FADDRHI) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 628 FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 21.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 629 Module Base + 0x000E Reset = Unimplemented or Reserved Figure 21-19. RESERVED5 All bits read 0 and are not writable. 21.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 630 • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 631 FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag in the FSTAT register will set. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 632 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 FCLK > 0.15MHz FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE Figure 21-21. PRDIV8 and FDIV Bits Determination Procedure MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 633 Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 634 FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 635 BLANK ﬂag in the FSTAT register will be set if all addresses in the Flash array are veriﬁed to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 636 Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check Erase Verify BLANK Status Set? Flash Array Flash Array EXIT EXIT Erased Not Erased Figure 21-22. Example Erase Verify Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 637 CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program operation. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 638 Read: FSTAT register Bit Polling for CBEIF Buffer Empty Set? Check Sequential Next Programming Decision Word? Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 21-23. Example Program Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 639 Once the sector erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 640 Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 21-24. Example Sector Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 641 Once the mass erase command has successfully launched, the CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 642 Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for CCIF Command Completion Set? Check EXIT Figure 21-25. Example Mass Erase Command Flow MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 643 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL ﬂag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL ﬂag is cleared. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 644 Flash array, the MCU will be unsecured. The data must be written to the backdoor key MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 645 FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 646 CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 21-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 21.3.2.4, “Flash Conﬁguration Register (FCNFG)” Section 21.3.2.6, “Flash Status Register (FSTAT)”. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 647: Appendix A Electrical Characteristics
I/O ports, A/D converter, oscillator and PLL as well as the internal logic. The V pair supplies the A/D converter. The V pair supplies the I/O pins The V pair supplies the internal voltage regulator. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 648 Current Injection Power supply must maintain regulation within operating V or V range during instantaneous and operating maximum current conditions. If positive injection current (V > V ) is greater than I , the MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 649 3. These pins are internally clamped to V and V SSPLL DDPLL 4. This pin is clamped low to V , but not clamped high. This pin must be tied low in applications. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 650 Human Body Model (HBM) 2000 — Machine Model (MM) — Charge Device Model (CDM) — Latch-up Current at 125°C Positive +100 — Negative –100 — Latch-up Current at 27°C Positive +200 — Negative –200 — MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 651 Using an external regulator, with the internal voltage regulator disabled, an external LVR must be provided. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 652 ﬂowing into the external loads with output high. ∑ ⋅ DSON IO i Which is the sum of all output currents on I/O ports associated with V and V MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 653 Junction to Package Top QFP80 — — 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7 Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 654 8 C to 12 C in the temper ature range from 50 C to 125 C . 2. Refer to Section A.1.4, “Current Injection”, for more details 3. Parameter only applies in STOP or Pseudo STOP mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 655 A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 656 100˚C although the Temperature speciﬁcation is 85˚C. Similarly for "v" and "M" options the temperature used in test lies 15˚C above the temperature option speciﬁcation. 2. PLL off 3. At those low power dissipation levels T can be assumed MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 657 100˚C although the Temperature speciﬁcation is 85˚C. Similarly for "v" and "M" options the temperature used in test lies 15˚C above the temperature option speciﬁcation. 2. PLL off 3. At those low power dissipation levels T can be assumed Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 658 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a ﬁnal sample period of 2 ATD clocks cycles while the maximum time assumes a ﬁnal sample period of 16 ATD clocks. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 659 For a maximum sampling error of the input voltage ≤ 1LSB, then the external ﬁlter capacitor, C ≥ 1024 * (C – C Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 660 8-Bit Differential Nonlinearity –0.5 — Counts ±0.5 8-Bit Integral Nonlinearity –1.0 Counts ±1 8-Bit Absolute Error -1.5 Counts 1. These values include quantization error which is inherently 1/2 count for any A/D converter. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 661 DNL i ( ) -------------------------- - 1 – 1LSB The Integral Non-Linearity (INL) is deﬁned as the sum of all DNLs: ∑ – INL n ( ) DNL i ( ) -------------------- - n – 1LSB Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 662 29.25 3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328 Figure A-1. ATD Accuracy Deﬁnitions NOTE Figure A-1 shows only deﬁnitions, for speciﬁcation values refer to Table A- MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 663 After releasing the LVR reset the oscillator and the clock quality check are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self CQOUT clock. The fastest startup time possible is given by n uposc Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 664 . The device also features a clock monitor. A Clock Monitor Failure is UPOSC asserted if the frequency of the incoming clock signal is below the Assert Frequency f CMFA. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 665 2. f = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce Oscillator/external clock selected (XCLKS = 0 during reset) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 666 – 60 50 – ---------------------- - --------------------- - ⋅ – ⋅ ⋅ = -90.48MHz/V – The phase detector relationship is given by: ⋅ – = 316.7Hz/Ω Φ is the current in tracking mode. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 667 The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 668 Figure A-4. Maximum Bus Clock Jitter Approximation This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 669 The minimum program and erase times shown in Table A-18 are calculated for maximum f NVMOP maximum f . The maximum times are calculated for minimum f and a f of 2MHz. NVMOP Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 670 The setup times can be ignored for this operation. A.5.1.4 Mass Erase Erasing a NVM block takes: ≈ ⋅ 20000 --------------------- mass NVMOP This is independent of sector size. The setup times can be ignored for this operation. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 671 8. Minimum time, if ﬁrst word in the array is not blank (1024 byte sector size) 9. Maximum time to complete check on an erased block (1024 byte sector size). Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 672 3. Spec table quotes typical endurance evaluated at 25°C for this product family, typical endurance at various temperature can be estimated using the graph below. For additional information on how Freescale deﬁnes Typical Endurance, please refer to Engineering Bulletin EB619. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 673 Load capacitance C on all outputs LOAD, Thresholds for delay measurement points (20% / 80%) V A.6.1 Master Mode Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 674 MASTER MSB OUT (OUTPUT) 1. If conﬁgured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-7. SPI Master Timing (CPHA=1) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 675 BIT 6 . . . 1 SLAVE LSB OUT SLAVE MSB (OUTPUT) note NOTE MOSI MSB IN BIT 6 . . . 1 LSB IN (INPUT) NOTE: Not defined! Figure A-8. SPI Slave Timing (CPHA=0) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 676 — 30 + t Data Hold Time (Outputs) — — Rise and Fall Time Inputs — — rﬁ Rise and Fall Time Outputs — — 1. t added due to internal synchronization delay MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 677 Chip Power-up and LVI/LVR Graphical Explanation Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-10. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 678 The capacitive loads are speciﬁed in Table A-24. Ceramic capacitors with X7R dielectricum are required. Table A-24. Voltage Regulator — Capacitive Loads Characteristic Symbol Typical Unit external capacitive load 12000 DDext external capacitive load 5000 DDPLL DDPLLext MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 679: Appendix B Emulation Information
ADDR1/DATA1/PB1 PA3/ADDR11/DATA11 ADDR2/DATA2/PB2 PA2/ADDR10/DATA10 ADDR3/DATA3/PB3 PA1/ADDR9/DATA9 ADDR4/DATA4/PB4 PA0/ADDR8/DATA8 Signals shown in Bold are available only in the 112 Pin Package. Pins marked "NC" are not connected Figure B-1. Pin Assignments in 112-Pin LQFP Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 680 The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal pullup resistors at PortK[2:0]. In this reset state the pull-up resistors provide a deﬁned state and prevent a ﬂoating input, thereby preventing unnecessary current consumption at the input stage. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 681: Appendix C Package Information
Appendix C Package Information Appendix C Package Information General This section provides the physical dimensions of the packages 48LQFP, 52LQFP, 80QFP. Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 682 EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT 0.13 ° DETAIL C BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 16.95 17.45 0.35 0.45 1.6 REF Figure C-1. 80-Pin QFP Mechanical Dimensions (Case no. 841B) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 683 0.236 BSC 0.20 REF 0.008 REF 1.00 REF 0.039 REF ° ° ° ° θ ° ° θ1 ° ° θ2 ° ° θ3 Figure C-2. 52-Pin LQFP Mechanical Dimensions (Case no. 848D-03) Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 684 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF M ° BASE METAL TOP & BOTTOM 0.080 SECTION AE-AE L ° DETAIL AD Figure C-3. 48-Pin LQFP Mechanical Dimensions (Case no. 932-03 issue F) MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 685: Appendix D Derivative Differences
Table D-1. List of MC9S12C and MC9S12GC Family members Flash Device PWM Timer MC9S12C128 128K MC9S12GC128 — MC9S12C96 MC9S12GC96 — MC9S12C64 MC9S12GC64 — MC9S12C32 MC9S12GC32 — MC9S12GC16 — 1. All family memebers are available in 80QFP, 52LQFP and 48LQFP package options Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 686 C128 die MC9S12C96MPB XL09S/0M66G -40˚C,125˚C 52LQFP 25MHz C128 die MC9S12C96MFU XL09S/0M66G -40˚C, 125˚C 80QFP 25MHz C128 die MC9S12C64CFA XL09S/0M66G -40˚C, 85˚C 48LQFP 25MHz C128 die MC9S12C64CPB XL09S/0M66G -40˚C, 85˚C 52LQFP 25MHz C128 die MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 687 -40˚C,105˚C 52LQFP 25MHz C32 die MC9S12GC32VFU xL45J / xM34C -40˚C, 105˚C 80QFP 25MHz C32 die MC9S12GC32MFA xL45J / xM34C -40˚C,125˚C 48LQFP 25MHz C32 die MC9S12GC32MPB xL45J / xM34C -40˚C,125˚C 52LQFP 25MHz C32 die Freescale Semiconductor MC9S12C-Family / MC9S12GC-Family Rev 01.24...
Page 688 2. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8 channel timer. The GC-Family members do not have the CAN module 3. I/O is the sum of ports capable to act as digital input or output. MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.24...
Page 690 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 691 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Freescale Semiconductor S9S12C64J2CFAE MC9S12GC16MFAE MC9S12GC96MFUE MC9S12GC64MPBE MC9S12GC64MFUE MC9S12GC64MFAE MC9S12GC96MFAE MC9S12GC32MFAE MC9S12GC128MFUE MC9S12C128CPBE MC9S12C128VFAE MC9S12C128VFUE MC9S12C32CFAE16 MC9S12C32CFUE25 MC9S12C32CPBE25 MC9S12C32MPBE16 MC9S12C32VFAE16 MC9S12C32VFAE25 MC9S12C32VFUE16 MC9S12C32VPBE16 MC9S12C64CFAER MC9S12C64CFUE MC9S12C64CPBE MC9S12C64VFAE MC9S12C64VFUE...

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Mc9s12gc family

Freescale Semiconductor MC9S12C Family Reference Manual

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)

Chapter 2 Port Integration Module (PIM9C32)

Chapter 3 Module Mapping Control (MMCV4)

Chapter 4 Multiplexed External Bus Interface (MEBIV3)

Chapter 5 Interrupt (INTV1)

Chapter 6 Background Debug Module (BDMV4)

Chapter 7 Debug Module (DBGV1)

Chapter 8 Analog-To-Digital Converter (ATD10B8C)

Chapter 9 Clocks and Reset Generator (CRGV4)

Chapter 10 Scalable Controller Area Network (S12MSCANV2)

Chapter 11 Oscillator (OSCV2)

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)

Chapter 13 Serial Communications Interface (S12SCIV2)

Chapter 14 Serial Peripheral Interface (SPIV3)

Chapter 15 Timer Module (TIM16B8CV1)

Chapter 16 Dual Output Voltage Regulator (VREG3V3V2)

Chapter 17 16 Kbyte Flash Module (S12FTS16KV1)

Chapter 18 32 Kbyte Flash Module (S12FTS32KV1)

Chapter 19 64 Kbyte Flash Module (S12FTS64KV4)

Chapter 20 96 Kbyte Flash Module (S12FTS96KV1)

Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1)

Appendix A Electrical Characteristics

Appendix B Emulation Information

Appendix C Package Information

Appendix D Derivative Differences

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