Freescale Semiconductor ColdFire MCF5213 Reference Manual

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MCF5213 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF5211

MCF5212

MCF5213

Document Number: MCF5213RM

Rev. 3

03/2007

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Page 1 ® MCF5213 ColdFire Integrated Microcontroller Reference Manual Devices Supported: MCF5211 MCF5212 MCF5213 Document Number: MCF5213RM Rev. 3 03/2007...
Page 2 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor Hong Kong Ltd.
Page 3 Overview Signal Descriptions ColdFire Core Multiply-Accumulate Unit (MAC) Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Module Edge Port Module (EPORT) DMA Controller Module ColdFire Flash Module (CFM) EzPort Programmable Interrupt Timers (PIT0–PIT1)
Page 4 Overview Signal Descriptions ColdFire Core Multiply-Accumulate Unit (MAC) Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Module Edge Port Module (EPORT) DMA Controller Module ColdFire Flash Module (CFM) EzPort Programmable Interrupt Timers (PIT0–PIT1)
Page 5: Table Of Contents
Software Watchdog Timer ..................1-12 1.4.16 Phase-Locked Loop (PLL) ..................1-12 1.4.17 Interrupt Controller (INTC) ..................1-13 1.4.18 DMA Controller ......................1-13 1.4.19 Reset .......................... 1-13 1.4.20 GPIO ......................... 1-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 6: Paragraph Number
Exception Stack Frame Definition ................3-10 Processor Exceptions ....................3-12 3.5.1 Access Error Exception .................... 3-12 3.5.2 Address Error Exception ................... 3-12 3.5.3 Illegal Instruction Exception ..................3-12 3.5.4 Divide-By-Zero ......................3-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 7 Mask Register (MASK) ....................4-7 4.4.3 Accumulator Register (ACC) ..................4-8 MAC Instruction Set Summary ..................4-8 4.5.1 MAC Instruction Execution Times ................4-9 4.5.2 Data Representation ....................4-9 4.5.3 MAC Opcodes ......................4-9 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 8 Clock Operation During Reset .................. 6-10 6.8.3 System Clock Generation ..................6-11 6.8.4 PLL Operation ......................6-11 6.8.4.1 Phase and Frequency Detector (PFD) ..............6-12 6.8.4.2 Charge Pump/Loop Filter ..................6-12 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 viii Freescale Semiconductor...
Page 9 UART Modules (UART0, UART1, and UART2) ..........7-12 7.4.2.7 I2C Module ......................7-13 7.4.2.8 Queued Serial Peripheral Interface (QSPI) ............7-13 7.4.2.9 DMA Timers (DTIM0–DTIM3) ................7-13 7.4.2.10 Interrupt Controllers (INTC0, INTC1) ..............7-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 10 Reset Controller Module Introduction ........................9-1 Features ........................... 9-1 Block Diagram ........................ 9-1 Signals ..........................9-2 9.4.1 RSTI ..........................9-2 9.4.2 RSTO .......................... 9-2 Memory Map and Registers .................... 9-2 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 11 10.6.3 Bus Master Park Register (MPARK) ..............10-10 10.7 System Access Control Unit (SACU) ................. 10-12 10.7.1 Overview ......................... 10-12 10.7.2 Features ........................10-12 10.7.3 Memory Map/Register Definition ................10-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 12 Memory Map ........................ 12-4 12.3 Register Descriptions ....................12-6 12.3.1 Interrupt Pending Registers (IPRHn, IPRLn) ............12-6 12.3.2 Interrupt Mask Register (IMRHn, IMRLn) .............. 12-7 12.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) ..........12-9 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 13 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) ......14-6 14.3.5 DMA Control Registers (DCRn) ................14-8 14.4 Functional Description ....................14-11 14.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) ........14-12 14.4.2 Dual-Address Data Transfer Mode ................. 14-12 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xiii...
Page 14 Command Write Sequence ................15-18 15.4.2.3.3 Bus Arbitration During Write Operations ............15-19 15.4.2.3.4 Flash Normal Mode Commands ..............15-19 15.4.2.3.4.1 Blank Check ....................15-19 15.4.2.3.4.2 Page Erase Verify ..................15-21 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 15 16.4.1.7 Page Program ......................16-6 16.4.1.8 Sector Erase ......................16-7 16.4.1.9 Bulk Erase ......................16-7 16.4.1.10 Reset Chip ......................16-7 16.5 Functional Description ....................16-7 16.6 Initialization/Application Information ................16-8 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 16 GPT Control Register 2 (GPTCTL2) ..............18-10 18.6.10 GPT Interrupt Enable Register (GPTIE) ..............18-10 18.6.11 GPT System Control Register 2 (GPTSCR2) ............18-11 18.6.12 GPT Flag Register 1 (GPTFLG1) ................18-12 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 17 19.3 Functional Description ....................19-8 19.3.1 Prescaler ........................19-8 19.3.2 Capture Mode ......................19-8 19.3.3 Reference Compare ....................19-8 19.3.4 Output Mode ......................19-8 19.4 Initialization/Application Information ................19-9 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xvii...
Page 18 Introduction ........................21-1 21.1.1 Overview ........................21-1 21.1.2 Features ........................21-2 21.2 External Signal Description ..................21-2 21.3 Memory Map/Register Definition ................21-3 21.3.1 UART Mode Registers 1 (UMR1n) ................21-5 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xviii Freescale Semiconductor...
Page 19 21.5.1.2 Setting up the UART to Request DMA Service ..........21-26 21.5.2 UART Module Initialization Sequence ..............21-27 Chapter 22 C Interface 22.1 Introduction ........................22-1 22.1.1 Overview ........................22-1 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 20 Channel List 1 and 2 Registers (ADLST1 and ADLST2) ........23-8 23.4.5 Sample Disable Register (ADSDIS) ............... 23-10 23.4.6 Status Register (ADSTAT) ..................23-11 23.4.7 Limit Status Register (ADLSTAT) ................. 23-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 21 PWM Center Align Enable Register (PWMCAE) ........... 24-6 24.2.6 PWM Control Register (PWMCTL) ................. 24-6 24.2.7 PWM Scale A Register (PWMSCLA) ..............24-7 24.2.8 PWM Scale B Register (PWMSCLB) ..............24-8 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 22 FlexCAN Control Register (CANCTRL) ..............25-8 25.3.3 FlexCAN Free Running Timer Register (TIMER) ..........25-10 25.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK) ......25-11 25.3.5 FlexCAN Error Counter Register (ERRCNT) ............25-12 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxii Freescale Semiconductor...
Page 23 Trigger Definition Register (TDR) ................. 26-12 26.4.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) ......26-15 26.4.7 Address Breakpoint Registers (ABLR, ABHR) ............. 26-17 26.4.8 Data Breakpoint and Mask Registers (DBR, DBMR) ..........26-18 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xxiii...
Page 24 IEEE 1149.1 Test Access Port (JTAG) 27.1 Introduction ........................27-1 27.1.1 Block Diagram ......................27-1 27.1.2 Features ........................27-2 27.1.3 Modes of Operation ....................27-2 27.2 External Signal Description ..................27-2 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxiv Freescale Semiconductor...
Page 25 CLAMP Instruction .................... 27-10 27.4.3.9 BYPASS Instruction ................... 27-10 27.5 Initialization/Application Information ................ 27-10 27.5.1 Restrictions ......................27-10 27.5.2 Nonscan Chain Operation ..................27-10 Appendix A Register Memory Map Quick Reference MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 26 Contents Paragraph Page Title Number Number MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxvi Freescale Semiconductor...
Page 27: About This Book
RAM (SRAM) implementation. It also provides information and examples of how to minimize power consumption when using the SRAM. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xxvii...
Page 28 (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Programming examples are included. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxviii Freescale Semiconductor...
Page 29: Conventions
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xxix...
Page 30: Register Figure Conventions
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 31: Acronyms And Abbreviations
Least recently used Least-significant byte Least-significant bit Multiply accumulate unit, also Media access controller MBAR Memory base address register Most-significant byte Most-significant bit Multiplex No operation Operand execution pipeline Program counter MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xxxi...
Page 32: Terminology Conventions
Any control register (example VBR is the vector base register) MAC registers (ACC, MAC, MASK) Any address or data register Destination register w (used for MAC instructions only) Ry,Rx Any source and destination registers, respectively MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxxii Freescale Semiconductor...
Page 33 Source operand is moved to destination operand ←→ Two operands are exchanged sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor xxxiii...
Page 34 Bit selection (example: Bit 3 of D0) Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 xxxiv Freescale Semiconductor...
Page 35: Overview
Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com/coldfire. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 36: Mcf5213 Family Configurations
FlexCAN is available on the MCF5211 only in the 64 QFN package. The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller packages. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 37: Block Diagram
Edge PLL OCO FlexCAN PIT0 PIT1 Port CLKGEN EXTAL XTAL CLKOUT CLKMOD0 CLKMOD1 To/From Interrupt Controller Figure 1-1. MCF5213 Block Diagram Part Numbers and Packaging Table 1-2. Part Number Summary MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 38: Features
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses • Power management — Fully static operation with processor sleep and whole chip stop modes MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 39 — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level • Queued serial peripheral interface (QSPI) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 40 — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 41 — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 42: V2 Core Overview
MCF5213 core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 43: Integrated Debug Module
• Bypass the MCF5213 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 44: On-Chip Memories
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 1-10 Freescale Semiconductor...
Page 45: Uarts
8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 1-11...
Page 46: General Purpose Timer (Gpt)
In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 1-12 Freescale Semiconductor...
Page 47: Interrupt Controller (Intc)
Nearly all pins on the MCF5213 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 1-13...
Page 48 Overview MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 1-14 Freescale Semiconductor...
Page 49: Signal Descriptions
Active-low signals, such as SRAS and TA, are indicated with an overbar. Overview Figure 2-1 shows the block diagram of the device with the signal interface. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 50 SRAM Flash (GPIO) RSTO (4K×16)×4 (32K×16)×4 STBY Edge PLL OCO FlexCAN PIT0 PIT1 Port CLKGEN EXTAL XTAL CLKOUT CLKMOD0 CLKMOD1 To/From Interrupt Controller Figure 2-1. Block Diagram with Signal Interfaces MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 51 Table 2-1. Pin Functions by Primary and Alternate Purpose Drive Primary Secondary Tertiary Quaternary Slew Rate / Pull-up / Pin on Pin on 81 Pin on 64 Strength / Notes Group Function Function Function Function Control Pull-down 100 LQFP MAPBGA LQFP/QFN Control —...
Page 52 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Slew Rate / Pull-up / Pin on Pin on 81 Pin on 64 Strength / Notes Group Function Function Function Function Control Pull-down 100 LQFP MAPBGA LQFP/QFN Control...
Page 53 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Slew Rate / Pull-up / Pin on Pin on 81 Pin on 64 Strength / Notes Group Function Function Function Function Control Pull-down 100 LQFP MAPBGA LQFP/QFN Control...
Page 54 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Drive Primary Secondary Tertiary Quaternary Slew Rate / Pull-up / Pin on Pin on 81 Pin on 64 Strength / Notes Group Function Function Function Function Control Pull-down 100 LQFP MAPBGA LQFP/QFN Control...
Page 55: Reset Signals
Test TEST Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 56: External Interrupt Signals
Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable. Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active Chip Selects high or low. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 57: I 2 C I/O Signals
Table 2-10. DMA Timer Signals Signal Name Abbreviation Function DMA Timer Input DTINn Event input to the DMA timer modules. DMA Timer Output DTOUTn Programmable output from the DMA timer modules. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 58: 2.11 Adc Signals
Test Clock TCLK Used to synchronize the JTAG logic. Test Mode Select Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 2-10 Freescale Semiconductor...
Page 59 The CLKOUT signal can be used by the development system to know when to sample PST[3:0]. All Processor Status ALLPST Logical AND of PST[3.0] Outputs MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 2-11...
Page 60: 2.15 Ezport Signal Descriptions
Positive Supply These pins supply positive power to the core logic. Ground This pin is the negative supply (ground) to the chip. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 2-12 Freescale Semiconductor...
Page 61: Coldfire Core
Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 62: Memory Map/Register Description
8-bit condition code register (CCR) • MAC registers (described fully in Chapter 4, “Multiply-Accumulate Unit (MAC)”): — One 32-bit accumulator(ACC) register — One 16-bit mask register (MASK) — 8-bit Status register (MACSR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 63 User/Supervisor A7 Stack Pointer Contents of 3.2.3/3-4 (OTHER_A7) location 0x0000_0000 0x801 Vector Base Register (VBR) 0x0000_0000 3.2.6/3-6 0x80E Status Register (SR) 0x27-- 3.2.7/3-7 0xC04 Flash Base Address Register 0x0000_0000 3.2.8/3-8 (FLASHBAR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 64: Data Registers (D0-D7)
(SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 65: Condition Code Register (Ccr)
The extend bit (X) is also used as an input operand during multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 66: Program Counter (Pc)
The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 67: Status Register (Sr)
1 Supervisor mode Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or move to SR instructions. Reserved, must be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 68: Memory Base Address Registers (Rambar, Flashbar)
Move from USP USP → Destination register Source register → USP Move to USP STLDSR Pushes the contents of the status register onto the stack and then reloads the status register with the immediate data value. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 69: Exception Processing Overview
3-5). The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are device-specific peripheral interrupt vectors. See,” for details on the device-specific interrupt sources. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 70: Exception Stack Frame Definition
Figure 3-9 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the 32-bit program counter address. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-10 Freescale Semiconductor...
Page 71 The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. See Table 3-5. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-11...
Page 72: Processor Exceptions
1 and extension word 2. The opword is further subdivided into three sections: the upper four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-12 Freescale Semiconductor...
Page 73: Divide-By-Zero
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction, including MOVEC. 3.5.4 Divide-By-Zero Attempting to divide by zero causes an exception (vector 5, offset equal 0x014). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-13...
Page 74: Privilege Violation
3.5.8 Unimplemented Line-F Opcode A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when attempting to execute an undefined line-f opcode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-14 Freescale Semiconductor...
Page 75: Debug Interrupt
Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-15...
Page 76 0010 V2 ColdFire core (This is the value used for this device.) 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V5 ColdFire core Else Reserved for future use. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-16 Freescale Semiconductor...
Page 77 Debug module revision number. This 4-bit field defines revision level of the debug module used in the ColdFire DEBUG processor core. 0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B+ (This is the value used for this device.) 1011 DEBUG_D+ Else Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-17...
Page 78 0000-0111 No flash 1000 64KB Flash 1001 128KB Flash 1010 256KB Flash (This is the value used for this device) 1011 512KB Flash Else Reserved for future use. 19–16 Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-18 Freescale Semiconductor...
Page 79: Instruction Execution Timing
(DSOC) of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-19...
Page 80: Move Instruction Execution Times
1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1) (Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-20 Freescale Semiconductor...
Page 81: Standard One Operand Instruction Execution Times
#xxx bitrev 1(0/0) — — — — — — — byterev 1(0/0) — — — — — — — clr.b <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-21...
Page 82: Standard Two Operand Instruction Execution Times
Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bchg #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — bclr Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-22 Freescale Semiconductor...
Page 83: Miscellaneous Instruction Execution Times
Opcode <EA> (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx cpushl (Ax) — 11(0/1) — — — — — — link.w Ay,#imm 2(0/1) — — — — — — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-23...
Page 84: Mac Instruction Execution Times
-(An) (d16,An) xxx.wl #xxx Xn*SF) mac.l Ry, Rx 3(0/0) — — — — — — — mac.l Ry, Rx, <ea>, Rw — 4(1/0) 4(1/0) 4(1/0) 4(1/0) — — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-24 Freescale Semiconductor...
Page 85: Branch Instruction Execution Times
3(0/0) 4(0/0) 3(0/0) — <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — — — 10(2/0) — — — — — — — 5(1/0) — — — — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 3-25...
Page 86 ColdFire Core Table 3-19. Bcc Instruction Execution Times Forward Forward Backward Backward Opcode Taken Not Taken Taken Not Taken 3(0/0) 1(0/0) 2(0/0) 3(0/0) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 3-26 Freescale Semiconductor...
Page 87: Multiply-Accumulate Unit (Mac)
For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 88: General Operation
For longword integer operations, only the least significant 32 bits of the product are calculated. For fractional operations, the entire 64-bit product is calculated and then truncated or rounded to a 32-bit result using the round-to-nearest (even) method. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 89: Memory Map/Register Definition
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-2. MAC Status Register (MACSR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 90 After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly loaded. MULS and MULU instructions do not change this value. Carry. This field is always zero. Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 91: Fractional Operation Mode
— If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down. This method minimizes rounding bias and creates as statistically correct an answer as possible. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 92: Saving And Restoring The Mac Programming Model
MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers. 4.4.1.1.4 Scale Factor in MAC or MSAC Instructions The scale factor is ignored while the MAC is in fractional mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 93: Mask Register (Mask)
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 4-3. Mask Register (MASK) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 94: Accumulator Register (Acc)
Writes the contents of the accumulator to a CPU register move.l ACC,Rx Load MACSR Writes a value to MACSR move.l {Ry,#imm},MACSR Store MACSR Write the contents of MACSR to a CPU register move.l MACSR,Rx MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 95: Mac Instruction Execution Times
This indicator is treated as a sticky flag, meaning after set, it remains set until the accumulator or the MACSR is directly loaded. See Section 4.4.1, “MAC Status Register (MACSR).” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 96 = 0x7fff_ffff else result[31:0] = 0x8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[31:0] = 0x8000_0000 else result[31:0] = 0x7fff_ffff MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 4-10 Freescale Semiconductor...
Page 97 /* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break; case 1: case 3: /* signed fractionals */ MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 4-11...
Page 98 (result[31:0] == 0x0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break; case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.V == 0) then { MACSR.V = 0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 4-12 Freescale Semiconductor...
Page 99 = {0, product[31:1]} break; /* combine with accumulator */ if (MACSR.V == 0) then {if (inst == MSAC) then result[31:0] = acc[31:0] - product[31:0] else result[31:0] = acc[31:0] + product[31:0] MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 4-13...
Page 100 = 0xffff_ffff /* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break;} MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 4-14 Freescale Semiconductor...
Page 101: Static Ram (Sram)
Byte, word, and longword address capabilities Memory Map/Register Description The SRAM programming model shown in Table 5-1 includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 102: Sram Base Address Register (Rambar)
MCF5211). By programming this field, the SRAM may be located on any 32-Kbyte boundary (16-Kbyte boundary for the MCF5211). Bit 14 is reserved on the MCF5212and MCF5213 devices and should be cleared. 13–12 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 103: Initialization/Application Information
If the SRAM requires initialization with instructions or data, perform the following steps: 1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 104: Sram Initialization Code
Table 5-3 shows examples of typical RAMBAR settings. Table 5-3. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Instruction Only 0x2B Data Only 0x35 Instructions and Data 0x21 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 105: Clock Module
PLL. The PLL reference can be a crystal oscillator or an external clock. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 106: 1:1 Pll Mode
RFD value plus one before entering stop mode. In external clock mode, there are no wakeup periods for oscillator startup or PLL lock. Block Diagram Figure 6-1 shows a block diagram of the entire clock module. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 107 PPRML[17] CLKOUT DMA Timers DISCLK PPRMH[9] PPRML[16:13] QSPI PPRMH[8] PPRML[10] PPRMH[7] PPRML[9] PITs UARTs PPRMH[4:3] PPRML[7:5 Edge Port PPRMH[1] PPRML[4] GPIO / Ports PPRMH[0] Figure 6-1. Clock Module Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 108: Signal Descriptions
PLL disabled, clock driven by external crystal PLL in normal mode, clock driven by external oscillator PLL in normal mode, clock driven by on-chip oscillator PLL in normal mode, clock driven by external crystal MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 109: Rsto
Access: Supervisor read/write Offset: 0x12_0000 (SYNCR) LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 Reset LOCEN DISCLK FWKUP — — CLKSRC PLLMODE PLLEN Reset Figure 6-2. Synthesizer Control Register (SYNCR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 110 To avoid surpassing the allowable system operating frequency, write to RFD[2:0] only when the LOCK bit is set. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 111: Synthesizer Status Register (Synsr)
See note 1 See note 2 See note 2 Note: 1. Reset state determined during reset configuration. 2. See the LOCKS and LOCK bit descriptions. Figure 6-3. Synthesizer Status Register (SYNSR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 112 PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 0 PLL not locked 1 PLL locked MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 113: Low-Power Divider Register (Lpdr)
Table 6-7. LPDR Field Descriptions Field Description 7–4 Reserved, should be cleared. 3–0 Low-Power Divider. This field is used to divide down the system clock by a factor of 2 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 114: Functional Description
In external clock mode, the system is static and does not recognize reset until a clock is generated from the reference clock source selected by the CLKMOD pins (see Section 6.6.4, “CLKMOD[1:0]). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-10 Freescale Semiconductor...
Page 115: System Clock Generation
Actual component values depend on crystal specifications. The following subsections describe each major block of the PLL. Refer to Figure 6-5 to see how these functional sub-blocks interact. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 6-11...
Page 116: Phase And Frequency Detector (Pfd)
The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge, respectively, from the loop filter. The filter is integrated on the chip. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-12 Freescale Semiconductor...
Page 117: Voltage Control Output (Vco)
Figure 6-6 shows the sequence for detecting locked and non-locked conditions. In external clock mode, the PLL is disabled and cannot lock. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 6-13...
Page 118: Pll Loss Of Lock Conditions
To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the LOLRE bit has no effect. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-14 Freescale Semiconductor...
Page 119: Loss Of Clock Detection
PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. The reference and the PLL must be functioning properly to exit reset. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 6-15...
Page 120: Loss Of Clock In Stop Mode
‘LK ‘LC Block LOCKS from being cleared Lose reference Stuck — — — clock or no lock regain Lose reference ‘LK ‘LC Block LOCKS clock, from being regain cleared MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-16 Freescale Semiconductor...
Page 121 Off Off 0 Lose lock, Regain ‘LK ‘LC REF not entered f.b. clock, during stop; reference SCM entered clock during stop only during oscillator startup No regain Stuck — — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 6-17...
Page 122 — — ‘LK ‘LC Lose lock or clock RESET — — — Reset immediately Off X Lose lock, RESET RESET — — — Reset f.b. clock, immediately reference clock MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-18 Freescale Semiconductor...
Page 123 Stuck — — — clock Off X Regain SCM Wakeup without disabled lock Off X Regain SCM disabled On On 0 — — Wakeup without lock Lose reference clock MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 6-19...
Page 124 1–>‘LC = current value is 1 until clock is regained which then is the previous value before entering stop 1–> = current value is 1 until clock is regained but CLK is never expected to regain MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 6-20 Freescale Semiconductor...
Page 125: Power Management
Addresses not assigned to a register and undefined register bits are reserved for expansion. The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when accessing the LPCR. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 126: Peripheral Power Management Registers (Ppmrh, Ppmrl)
PPMRH definition. IPSBAR Access: read/write Offset: 0x000C (PPMRH) Reset Reset CDCFM CDFCAN CDPWM CDGPT Reset CDADC CDPIT1 CDPIT0 CDEPORT CDPORTS Reset Figure 7-1. Peripheral Power Management Register High (PPMRH) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 127 0 EPORT module clock is enabled 1 EPORT module clock is disabled Disable clock to the Ports module. CDPORTS 0 Ports module clock is enabled 1 Ports module clock is disabled MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 128: Peripheral Power Management Register Low (Ppmrl)
TMR1 module clock is enabled TMR1 module clock is disabled Disable clock to the DTIM0 module. CDTMR0 TMR0 module clock is enabled TMR0 module clock is disabled 12–11 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 129: Low-Power Interrupt Control Register (Lpicr)
The following is the sequence of operations needed to enable this functionality: 1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropriate interrupt priority level. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 130 Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the XLPM_IPL low-power mode.Refer to Table 7-5. [2:0] 3–0 Reserved, should be cleared. — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 131: Peripheral Power Management Set Register (Ppmrs)
PPMRx. The data value on a register write causes the corresponding bit in the PPMRx register to be cleared. A data value of 64 to 127 provides a global clear function, forcing the entire contents of the MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 132: Low-Power Control Register (Lpcr)
STOP instruction is issued, and controls clock activity in this low-power mode. IPSBAR Access: read/write Offset: 0x11_0007 (LPCR) LPMD STPMD LVDSE Reset: Figure 7-6. Low-Power Control Register (LPCR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 133: Ips Bus Timeout Monitor
IPS module enable and continues to count until the bus cycle is terminated via the negation of ips_xfr_wait. If the programmed timeout value is reached before a termination, the bus monitor completes MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 134: Functional Description
CPU with no cycles active, powers down the system and stops all internal clocks appropriately. During stop mode, the system clock is stopped low. For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 7-10 Freescale Semiconductor...
Page 135: Run Mode
Most peripherals may be disabled by software to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 7-11...
Page 136: Peripheral Behavior In Low-Power Modes
Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions. • The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 7-12 Freescale Semiconductor...
Page 137: I2C Module
CPU processor during low-power stop mode when all system clocks are stopped. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 7-13...
Page 138: I/O Ports
LPCR[STPMD] bit settings.The external CLKOUT output pin may be disabled to lower power consumption via the SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 7-14 Freescale Semiconductor...
Page 139: Edge Port
CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks. Recommendations for, and features of, FlexCAN’s stop mode operation are as follows: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 7-15...
Page 140 FlexCAN resumes its clocks. It then continues to monitor the conditions and stops/resumes its clocks appropriately. The following are conditions for the automatic shut-off of FlexCAN clocks: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 7-16 Freescale Semiconductor...
Page 141: Bdm
Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 7-17...
Page 142 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode is re-entered and changes made in halt mode remains in effect. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 7-18 Freescale Semiconductor...
Page 143: Chip Configuration Module (Ccm)
Internal weak pull-down device TEST Test mode selection Internal weak pull-down device The use of external pull-up/down resistors is very strongly recommended. Refer to Chapter 6, “Clock Module,” for more information. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 144: Rcon
The reset configuration register (RCON) indicates the default chip configuration. • The chip identification register (CIR) contains a unique part number. Table 8-2. Write-Once Bits Read/Write Accessibility Configuration Read/Write Access All configurations Read-always Debug operation Write-always MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 145: Memory Map
Chip configuration mode. This read-only field reflects the configuration selected at reset. Mode 111 Reserved 110 Single Chip Mode 101 EzPort Mode 100 Reserved 0xx Reserved 7–0 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 146: Reset Configuration Register (Rcon)
Access: read-only Offset: Reset – – – – – – – – – – – – – – – – The reset value is device-dependent. Figure 8-3. Chip Identification Register (CIR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 147 5–0 Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order, beginning with zero. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 148 Chip Configuration Module (CCM) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 149: Reset Controller Module
• LVD control and status bits for setup and use of LVD reset or interrupt Block Diagram Figure 9-1 illustrates the reset controller and is explained in the following sections. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 150: Signals
Memory Map and Registers The reset controller programming model consists of these registers: • Reset control register (RCR)—selects reset controller functions • Reset status register (RSR)—reflects the state of the last reset source MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 151: Reset Control Register (Rcr)
Also, LVDF is not cleared at reset; however, it always initializes to a zero because the part does not come out of reset while in a low-power state (LVDE/LVDRE bits are enabled out of reset). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 152: Reset Status Register (Rsr)
Software reset flag. Indicates that the last reset was caused by software. SOFT 1 Last reset caused by software 0 Last reset not caused by software Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 153: Functional Description
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 154: Power-On Reset
9-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 155 LATCH RESET STATUS ASSERT RSTO AND LATCH RESET STATUS RSTI NEGATED? PLL MODE? PLL LOCKED? WAIT 512 CLKOUT CYCLES NEGATE RSTO RCON ASSERTED? LATCH CONFIGURATION Figure 9-4. Reset Control Flow MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 156: Synchronous Reset Requests
(5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 157: Reset Status Flags
For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared to 0, even if another type of reset condition is detected during the reset sequence for LVD. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 158 Reset Controller Module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 9-10 Freescale Semiconductor...
Page 159: System Control Module (Scm)
— Core reset status register (CRSR) indicates type of last reset — Core watchdog service register (CWSR) services watchdog timer — Core watchdog control register (CWCR) for watchdog timer control MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-1...
Page 160: Memory Map And Register Definition
Peripheral Access Control Register (PACR3) 0x00 10.7.3.2/10-14 0x0028 Peripheral Access Control Register (PACR4) 0x00 10.7.3.2/10-14 0x0029 Peripheral Access Control Register (PACR5) 0x00 10.7.3.2/10-14 0x002A Peripheral Access Control Register (PACR6) 0x00 10.7.3.2/10-14 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-2 Freescale Semiconductor...
Page 161: Register Descriptions
At reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-3...
Page 162: Memory Base Address Register (Rambar)
For example, a DMA channel in a typical double-buffer application (also MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-4 Freescale Semiconductor...
Page 163 • RAMBAR specifies the base address of the SRAM. • All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-5...
Page 164: Core Reset Status Register (Crsr)
1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the processor core to initiate reset exception processing. All registers are forced to their initial state. 6–0 Reserved, should read as 0. Do not write to these locations. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-6 Freescale Semiconductor...
Page 165: Core Watchdog Control Register (Cwcr)
The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled. IPSBAR Access: read/write Offset: 0x0011 (CWCR) CWRI CWT[2:0] CWTA CWTAVAL CWTIF Reset: Figure 10-4. Core Watchdog Control Register (CWCR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-7...
Page 166: Core Watchdog Service Register (Cwsr)
CWT interrupt. Figure 10-5 illustrates the CWSR. At system reset, the contents of CWSR are uninitialized. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-8 Freescale Semiconductor...
Page 167: Internal Bus Arbitration
All remaining requesting ports are evaluated by the arbitration algorithm to determine the next-state arbitration pointer. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-9...
Page 168: Arbitration Algorithms
MPARK[PRK_LAST] is set or parks on the master that last requested the bus if cleared. 10.6.3 Bus Master Park Register (MPARK) The MPARK controls the operation of the system bus arbitration module. The platform bus master connections are defined as the following: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-10 Freescale Semiconductor...
Page 169 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-11...
Page 170: System Access Control Unit (Sacu)
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes the following: • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write • User instruction fetch • User operand read MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-12 Freescale Semiconductor...
Page 171: Memory Map/Register Definition
[15:12] [11:8] [7:4] [3:0] Offset 0x020 PPMRS PPMRC IPSBMT 0x024 PACR0 PACR1 PACR2 PACR3 0x028 PACR4 PACR5 PACR6 PACR7 0x02C PACR8 — — — 0x030 GPACR0 GPACR1 — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-13...
Page 172: Master Privilege Register (Mpr)
PACR defines the access level for each of the two modules. These modules only support operand reads and writes. Each PACR follows the format illustrated in Figure 10-9. For a list of PACRs and the modules that they control, refer to Table 10-12. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-14 Freescale Semiconductor...
Page 173 Read/Write No Access No Access Table 10-12. Peripheral Access Control Registers (PACRs) Modules Controlled IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 0x024 PACR0 — 0x025 PACR1 — 0x026 PACR2 UART0 UART1 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-15...
Page 174: Grouped Peripheral Access Control Registers (Gpacr0 & Gpacr1)
GPACR0, even though the modules are mapped in its 64-Mbyte address space. IPSBAR 0x0030 (GPACR0) Access: read/write Offsets: 0x0031 (GPACR1) LOCK ACCESS_CTRL Reset: Figure 10-10. GPACR Register MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-16 Freescale Semiconductor...
Page 175 Read / Write / Execute Read / Write / Execute 1101 Read / Write / Execute Read / Execute 1110 Read / Write Read 1111 Read / Write / Execute Execute MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 10-17...
Page 176 EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) GPACR1 0x0400_0000– CFM (Flash module’s backdoor access for 0x07FF_FFFF programming or access by a bus master other than the core) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 10-18 Freescale Semiconductor...
Page 177: General Purpose I/O Module
DTIN2 / PTC[2] / DTOUT2 / PWM4 PORT TC DTIN1 / PTC[1] / DTOUT1 / PWM2 DTIN0 / PTC[0] / DTOUT0 / PWM0 Figure 11-1. General Purpose I/O Module Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-1...
Page 178: Overview
Descriptions,” for more detailed information on the different signals and pins. 11.5 Memory Map/Register Definition 11.5.1 Ports Memory Map Table 11-1 summarizes all the registers in the MCF5213 ports address space. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-2 Freescale Semiconductor...
Page 179 The register address is the sum of the IPSBAR address and the value in this column. S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-3...
Page 180: Register Descriptions
0x10_0010 (PORTTD) 0x10_0011 (PORTUA) 0x10_0012 (PORTUB) 0x10_0013 (PORTUC) PORTn3 PORTn2 PORTn1 PORTn0 Reset: Figure 11-3. Port Output Data Registers with Bits 3:0 Implemented (PORTTA, PORTTC, PORTDD, PORTUA, PORTUB, PORTUC) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-4 Freescale Semiconductor...
Page 181: Port Data Direction Registers (Ddrn)
11-11. The fields are described in Table 11-3, which applies to all DDRn registers. The DDRn registers are read/write. At reset, all bits in the DDRn registers are cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-5...
Page 182 Figure 11-9. Port QS Data Direction Register (DDRQS) IPSBAR Access: User read/write Offset: 0x10_001C (DDRNQ) DDRn7 DDRn6 DDRn5 DDRn4 DDRn3 DDRn2 DDRn1 Reset: Figure 11-10. Port NQ Data Direction Register (DDRNQ) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-6 Freescale Semiconductor...
Page 183: Port Pin Data/Set Data Registers (Portnp/Setn)
0x10_0031 (PORTDDP/SETDD) Access: User read/write Offsets: 0x10_0032 (PORTANP/SETAN) PORTnP7 PORTnP6 PORTnP5 PORTnP4 PORTnP3 PORTnP2 PORTnP1 PORTnP0 Reset: Figure 11-12. Port Pin Data/Set Data Registers with Bits 7:0 Implemented (PORTDD/SETDD, PORTAN/SETAN) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-7...
Page 184 Reset: Figure 11-15. Port NQ Pin Data/Set Data Register (PORTNQ/SETNQ) IPSBAR Access: User read/write Offset: 0x10_0033 (PORTASP/SETAS) PORTnP1 PORTnP0 Reset: Figure 11-16. Port AS Pin Data/Set Data Register (PORTAS/SETAS) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-8 Freescale Semiconductor...
Page 185: Port Clear Output Data Registers (Clrn)
0x10_004C (CLRTD) 0x10_004D (CLRUA) 0x10_004E (CLRUB) 0x10_004F (CLRUC) CLRn3 CLRn2 CLRn1 CLRn0 Reset: Figure 11-18. Port Clear Output Data Registers with Bits 3:0 Implemented (CLRTA, CLRTC, CLRTD, CLRUA, CLRUB, CLRUC) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-9...
Page 186: Pin Assignment Registers
2-1). However, a signal should not be assigned to more than one pin at the same time. If a signal is assigned to two or more pins simultaneously, the result is undefined. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-10 Freescale Semiconductor...
Page 187: Dual-Function Pin Assignment Registers
The quad function pin assignment registers allow each pin controlled by each register bit to be configured for the primary, alternate 1 (secondary), alternate 2 (tertiary), and GPIO (quaternary) functions. The fields are described in Table 11-7, which applies to all quad-function registers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-11...
Page 188 Description PnPARx PnPARx pin assignment register bits. Pin assumes the GPIO function Pin assumes the primary function Pin assumes the alternate 1 function Pin assumes the alternate 2 function MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-12 Freescale Semiconductor...
Page 189: Port Nq Pin Assignment Register (Pnqpar)
PSSR0 Reset See note 1 1) Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode. Figure 11-28. Pin Slew Rate Register (PSRR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-13...
Page 190 PSSRx PSSRx slew rate register control bits. 1 Pin is configured for slow slew rate (delay is approximately 10 times slower) 0 Pin is configured for fast slew rate MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-14 Freescale Semiconductor...
Page 191: Pin Drive Strength Register (Pdsr)
1 Pin is configured for high drive strength (10mA) 0 Pin is configured for low drive strength (2mA) 11.7 Ports Interrupts The ports module does not generate interrupt requests. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 11-15...
Page 192 General Purpose I/O Module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 11-16 Freescale Semiconductor...
Page 193: Interrupt Controller Module
8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-1...
Page 194: Interrupt Controller Theory Of Operation
(from highest to lowest priority) as shown in Table 12-1. Table 12-1. Interrupt Priority Within a Level Interrupt ICR[2:0] Priority Sources 7 (Highest) 8–63 8–63 8–63 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-2 Freescale Semiconductor...
Page 195: Interrupt Recognition
Vector number = 64 + Interrupt source number Recall that vector numbers 0–63 are reserved for the ColdFire processor and its internal exceptions. Thus, the mapping of bit positions to vector numbers is as follows: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-3...
Page 196: Memory Map
Interrupt Force Register Low (INTFRCLn), [31:1] IPSBAR + 0x0C18 IRLRn[7:1] IACKLPRn[7:0] Reserved IPSBAR + 0x0C1C– Reserved IPSBAR + 0x0C3C IPSBAR + 0x0C40 Reserved ICRn01 ICRn02 ICRn03 IPSBAR + 0x0C44 ICRn04 ICRn05 ICRn06 ICRn07 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-4 Freescale Semiconductor...
Page 197 IPSBAR + 0x0FE0 GSWIACK Reserved IPSBAR + 0x0FE4 GL1IACK Reserved IPSBAR + 0x0FE8 GL2IACK Reserved IPSBAR + 0x0FEC GL3IACK Reserved IPSBAR + 0x0FF0 GL4IACK Reserved IPSBAR + 0x0FF4 GL5IACK Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-5...
Page 198: Register Descriptions
The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-6 Freescale Semiconductor...
Page 199: Interrupt Mask Register (Imrhn, Imrln)
63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability. IPSBAR Access: Read/write Offset: 0x0C08 (IMRHn) INT_MASK[63:48] Reset INT_MASK[47:32] Reset Figure 12-3. Interrupt Mask Register High (IMRHn) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-7...
Page 200 This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-8 Freescale Semiconductor...
Page 201: Interrupt Force Registers (Intfrchn, Intfrcln)
Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. INTFRCH 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-9...
Page 202: Interrupt Request Level Register (Irlrn)
Interrupt requests. Represents the prioritized active interrupts for each level. 0 There are no active interrupts at this level 1 There is an active interrupt at this level Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-10 Freescale Semiconductor...
Page 203: Interrupt Acknowledge Level And Priority Register (Iacklprn)
Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-11...
Page 204 111b represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field always reads as 000b. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-12 Freescale Semiconductor...
Page 205: Interrupt Sources
Write 1 to appropriate DTER0 bit DTIM1 DTIM1 interrupt Write 1 to appropriate DTER1 bit DTIM2 DTIM2 interrupt Write 1 to appropriate DTER2 bit DTIM3 DTIM3 interrupt Write 1 to appropriate DTER3 bit MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-13...
Page 206 ADCA ADCA conversion complete Write 1 to EOSI0 ADCB ADCB conversion complete Write 1 to EOSI1 ADCINT ADC Interrupt Write 1 to ZCI, LLMTI and HLMTI Not used (Reserved) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-14 Freescale Semiconductor...
Page 207: Software And Level M Iack Registers (Swiackn, Lmiackn)
IACK is performed. If there are no active sources, the interrupt controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-15...
Page 208: Global Software And Level M Iack Registers (Gswiack, Glmiack)
As implemented on the MCF5213, these registers contain the same information as SWIACK and LnIACK. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-16 Freescale Semiconductor...
Page 209: Low-Power Wakeup Operation
LPICR[6:4], then the interrupt controller asserts the wake-up output signal, which is routed to the SCM and PLL module to re-enable the device’s clock trees and resume processing. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 12-17...
Page 210 Interrupt Controller Module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 12-18 Freescale Semiconductor...
Page 211: Edge Port Module (Eport)
This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 7, “Power Management.” Table 13-1 shows EPORT module operation in low-power modes and describes how this module may exit from each mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 13-1...
Page 212: Interrupt/General-Purpose I/O Pin Descriptions
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 13-2 Freescale Semiconductor...
Page 213: Memory Map And Registers
EPORT data register (EPDR)—holds the data to be driven to the pins. • EPORT pin data register (EPPDR)—reflects the current state of the pins. • EPORT flag register (EPFR)—individually latches EPORT edge events. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 13-3...
Page 214: Eport Pin Assignment Register (Eppar)
Reserved, should be cleared. 13.4.2.2 EPORT Data Direction Register (EPDDR) IPSBAR Access: Supervisor read/write Offset: 0x13_0002 (EPDDR) EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 Reset: Figure 13-3. EPORT Data Direction Register (EPDDR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 13-4 Freescale Semiconductor...
Page 215: Edge Port Interrupt Enable Register (Epier)
Reserved, should be cleared. 13.4.2.4 Edge Port Data Register (EPDR) IPSBAR Access: User read/write Offset: 0x13_0004 (EPDR) EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 Reset: Figure 13-5. EPORT Port Data Register (EPDR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 13-5...
Page 216: Edge Port Pin Data Register (Eppdr)
Reserved, should be cleared. 13.4.2.6 Edge Port Flag Register (EPFR) IPSBAR Access: User read/write Offset: 0x13_0006 (EPFR) EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 Reset: Figure 13-7. EPORT Port Flag Register (EPFR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 13-6 Freescale Semiconductor...
Page 217 1 Selected edge for IRQx pin has been detected. 0 Selected edge for IRQx pin has not been detected. Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 13-7...
Page 218 Edge Port Module (EPORT) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 13-8 Freescale Semiconductor...
Page 219: Dma Controller Module
(SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART and GPIOs. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-1...
Page 220: Features
Continuous-mode or cycle-steal transfers • Independent transfer widths for source and destination • Independent source and destination address registers • Modulo addressing on source and destination addresses • Automatic channel linking MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-2 Freescale Semiconductor...
Page 221: Dma Transfer Overview
This section describes each internal register and its bit assignment. Modifying DMA control registers during a DMA transfer can result in undefined operation. Table 14-1 shows the mapping of DMA controller registers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-3...
Page 222: Dma Request Control (Dmareqc)
Writing to this register determines the exact routing of the DMA request to the four channels of the DMA modules. IPSBAR Access: read/write Offset: 0x00_0014 (DMAREQC) Reset DMAC3 DMAC2 DMAC1 DMAC0 Reset Figure 14-3. DMA Request Control Register (DMAREQC) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-4 Freescale Semiconductor...
Page 223: Source Address Registers (Sarn)
Section 5.2.1, “SRAM Base Address Register (RAMBAR),” for more details. 14.3.3 Destination Address Registers (DARn) DARn, shown in Figure 14-5, holds the address to which the DMA controller sends data. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-5...
Page 224: Byte Count Registers (Bcrn) And Dma Status Registers (Dsrn)
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-6 Freescale Semiconductor...
Page 225 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-7...
Page 226: Dma Control Registers (Dcrn)
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-8 Freescale Semiconductor...
Page 227 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-9...
Page 228 Disable request. DMA hardware automatically clears the corresponding DCRn[EEXT] bit when the byte count D_REQ register reaches zero. 0 EEXT bit is not affected. 1 EEXT bit is cleared when the BCR is exhausted. Reserved; should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-10 Freescale Semiconductor...
Page 229: Functional Description
A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE]. See 14.3.5, “DMA Control Registers (DCRn).” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-11...
Page 230: Transfer Requests (Cycle-Steal And Continuous Modes)
If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-12 Freescale Semiconductor...
Page 231: Channel Initialization And Startup
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-13...
Page 232: Data Transfer
If auto-alignment is enabled, DCRn[AA] equals 1, the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-14 Freescale Semiconductor...
Page 233: Termination
DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. 14.5 Document Revision History MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 14-15...
Page 234 DMA Controller Module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 14-16 Freescale Semiconductor...
Page 235: Coldfire Flash Module (Cfm)
It is not possible to read from any flash logical block while the same logical block is being erased, programmed, or verified. Flash logical blocks are divided into multiple logical pages that can be erased separately. An erased bit reads 1 and a programmed bit reads 0. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-1...
Page 236: Features
Single power supply for program and erase operations • Software programmable interrupts on command completion, access violations, or protection violations • Fast page erase operation • Fast word program operation MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-2 Freescale Semiconductor...
Page 237: External Signal Description
CFM protection and access restriction scheme out of reset. A description of each byte found in the flash configuration field is given in Table 15-1. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-3...
Page 238: Flash Base Address Register (Flashbar)
FLASHBAR located in the processor’s CPU space is invalid and it must be initialized with the valid bit set before the CPU (or modules) can access the on-chip flash. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-4 Freescale Semiconductor...
Page 239 Base address field. Defines the 0-modulo-512K base address of the flash module. By programming this field, the flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space. 18–9 — Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-5...
Page 240 15 - 8 7 - 0 0x1D_0000 CFMMCR CFMCLKD RESERVED 0x1D_0004 RESERVED 0x1D_0008 CFMSEC 0x1D_000C RESERVED 0x1D_0010 CFMPROT 0x1D_0014 CFMSACC 0x1D_0018 CFMDACC 0x1D_001C RESERVED 0x1D_0020 CFMUSTAT RESERVED 0x1D_0024 CFMCMD RESERVED MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-6 Freescale Semiconductor...
Page 241: Register Descriptions
The PVIE bit is always readable and writable. The PVIE bit enables an interrupt in case the protection violation flag, PVIOL in the CFMUSTAT register, is set. 1 = An interrupt is requested when the PVIOL flag is set. 0 = PVIOL interrupt disabled. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-7...
Page 242: Cfmclkd - Cfm Clock Divider Register
The CFMCLKD register is used to control the period of the clock used for timed events in program and erase algorithms. IPSBAR Access: User read/write Offset: 0x1D_0002 (CFMCLKD) DIVLD PRDIV8 Reset: Figure 15-5. CFM Clock Divider Register (CFMCLKD) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-8 Freescale Semiconductor...
Page 243: Cfmsec - Cfm Security Register
1 = Backdoor key access to flash module is enabled. 0 = Backdoor key access to flash module is disabled. Flash memory security status SECSTAT 1 = Flash security is enabled. 0 = Flash security is disabled. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-9...
Page 244: Cfmprot - Cfm Protection Register
Reset PROTECT Reset Reset state loaded from flash configuration field during reset. Figure 15-7. CFM Protection Register (CFMPROT) All CFMPROT register bits are readable and only writable when LOCK=0. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-10 Freescale Semiconductor...
Page 245 SECTOR 16 8kBytes (PROGRAM_ARRAY_BASE + 0x0002_0000) SECTOR 15 8kBytes (PROGRAM_ARRAY_BASE + 0x0001_E000) • • • (PROGRAM_ARRAY_BASE + 0x0000_2000) PROTECT[0] SECTOR 0 8kBytes (PROGRAM_ARRAY_BASE + 0x0000_0000) Figure 15-8. CFMPROT Protection Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-11...
Page 246: Cfmsacc - Cfm Supervisor Access Register
Flash address space assignment for supervisor/user access SUPV SUPV[M] = 1: Flash logical sector M is placed in supervisor address space. SUPV[M] = 0: Flash logical sector M is placed in unrestricted address space. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-12 Freescale Semiconductor...
Page 247: Cfmdacc - Cfm Data Access Register
The CFMUSTAT register defines the flash command controller status and flash memory access, protection and verify status. IPSBAR Access: User read/write Offset: 0x1D_0020 (CFMUSTAT) CCIF CBEIF PVIOL ACCERR BLANK Reset: Figure 15-11. CFM User Status Register (CFMUSTAT) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-13...
Page 248 Section 15.4.2.3.5, “Flash Normal Mode Illegal Operations” for details on what action sets the ACCERR flag. 1 = Access error has occurred. 0 = No access error has been detected. Reserved, should read 0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-14 Freescale Semiconductor...
Page 249: Cfmcmd - Cfm Command Register
ACCERR flag in the CFMUSTAT register to set. Table 15-13. CFM Flash Memory Commands CMD[6:0] Description 0x05 Blank Check 0x06 Page Erase Verify 0x20 Word Program 0x40 Page Erase 0x41 Mass Erase MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-15...
Page 250: Cfmclksel - Cfm Clock Select Register
Program, erase, and verify operations (Section 15.4.2.3, “Program, Erase, and Verify Operations”) d) Stop mode (Section 15.4.2.4, “Stop Mode”) 2. Flash security operation (Section 15.4.3, “Flash Security Operation”) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-16 Freescale Semiconductor...
Page 251: Flash Normal Mode
If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1, MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-17...
Page 252: Command Write Sequence
The CBEIF flag is set again indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-18 Freescale Semiconductor...
Page 253: Bus Arbitration During Write Operations
15 internal flash bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set in the CFMUSTAT register. Upon completion of the blank MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-19...
Page 254 Blank Check BLANK Verify Status Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 Flash Memory Flash Memory EXIT EXIT Erased Not Erased Figure 15-14. Example Blank Check Command Flow MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-20 Freescale Semiconductor...
Page 255: Page Erase Verify
If any address in the selected flash logical page is not erased, the page erase verify operation terminates and the BLANK flag remains clear. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-21...
Page 256 Verify Status Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 Flash Logical Page Flash Logical Page EXIT EXIT Erased Not Erased Figure 15-15. Example Page Erase Verify Command Flow MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-22 Freescale Semiconductor...
Page 257: Program
CFMUSTAT register sets and the program command does not launch. After the program command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the program operation has completed unless a new command write sequence has been buffered. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-23...
Page 258: Page Erase
Set? Completion Check EXIT Figure 15-16. Example Program Command Flow Page Erase The page erase operation erases all memory addresses in a flash logical page using an embedded algorithm. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-24 Freescale Semiconductor...
Page 259 CFMUSTAT register sets and the page erase command does not launch. After the page erase command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the page erase operation has completed, unless a new command write sequence has been buffered. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-25...
Page 260: Mass Erase
Bit Polling for CCIF Command Set? Completion Check EXIT Figure 15-17. Example Page Erase Command Flow Mass Erase The mass erase operation erases all flash memory addresses using an embedded algorithm. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-26 Freescale Semiconductor...
Page 261 After the mass erase command has successfully launched, the CCIF flag in the CFMUSTAT register sets after the mass erase operation has completed, unless a new command write sequence has been buffered. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-27...
Page 262 Address, Data, Next Write? CBEIF Command Set? Buffer Empty Check • Read: Register CFMUSTAT Bit Polling for CCIF Command Set? Completion Check EXIT Figure 15-18. Example Mass Erase Command Flow MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-28 Freescale Semiconductor...
Page 263: Flash Normal Mode Illegal Operations
As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not execute the stop instruction during program and erase operations. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-29...
Page 264: Flash Security Operation
The contents of the flash security word at address offset 0x0414 must be changed by programming that address when the device is unsecured and the sector containing the flash configuration field is unprotected. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-30 Freescale Semiconductor...
Page 265: Blank Check
A secured CFM can be unsecured by mass erasing the flash memory via a sequence of JTAG commands, as specified in the system level security documentation followed by a reset of the MCU. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 15-31...
Page 266 ColdFire Flash Module (CFM) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 15-32 Freescale Semiconductor...
Page 267: Features
The rest of the micro-controller is disabled when the EzPort is enabled to avoid conflicts. • Disabled—When the EzPort is disabled, the rest of the micro-controller can access flash memory as normal. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 16-1...
Page 268: External Signal Description
EzPort clock (EZPCK) is the serial clock for data transfers. Serial data in (EZPD) and chip select (EZPCS) are registered on the rising edge of EZPCK while serial data out (EZPQ) is driven on the falling edge of MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 16-2 Freescale Semiconductor...
Page 269: Ezpcs - Ezport Chip Select
FAST_READ Page Program 0x02 4 to 256 Sector Erase 0xD8 Bulk Erase 0xC7 RESET Reset Chip 0xB9 Lists the compatible commands on the ST Microelectronics Serial Flash Memory parts. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 16-3...
Page 270: Command Descriptions
Bulk Erase command. The flag clears after a Read Status Register (RDSR) command. 0 No error on previous erase/program command. 1 Error on previous erase/program command. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 16-4 Freescale Semiconductor...
Page 271: Write Configuration Register
This command should not be used if the write error flag is set, a write is in progress, or the configuration register has already been loaded (as it is a write-once register). IPSBAR Access: read/write Offset: PRDIV8 DIV[5:0] Reset: Figure 16-3. EzPort Configuration Register MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 16-5...
Page 272: Read Data
The write error flag sets if there is an attempt to program a protected area of the flash memory. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 16-6 Freescale Semiconductor...
Page 273: Sector Erase
The serial data out from the EzPort is tri-stated unless data is being driven, allowing the signal to be shared among several different EzPort (or compatible) devices in parallel, provided they have different chip selects. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 16-7...
Page 274: Initialization/Application Information
For proper program and erase operations, it is critical to set Fclk between 150 kHz and 200 kHz. Array damage due to overstress can occur when Fclk is less than 150 kHz. Incomplete programming and erasure can occur when Fclk is greater than 200 kHz. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 16-8 Freescale Semiconductor...
Page 275: Programmable Interrupt Timers (Pit0-Pit1)
Low-power modes are described in the power management module, Chapter 7, “Power Management.” Table 17-1 shows the PIT module operation in low-power modes and how it can exit from each mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 17-1...
Page 276: Memory Map/Register Definition
0x15_0000 PIT Control and Status Register (PCSRn) 0x0000 17.2.1/17-3 0x16_0000 0x15_0002 PIT Modulus Register (PMRn) 0xFFFF 17.2.2/17-4 0x16_0002 User/Supervisor Access Registers 0x15_0004 PIT Count Register (PCNTRn) 0xFFFF 17.2.3/17-5 0x16_0004 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 17-2 Freescale Semiconductor...
Page 277: Pit Control And Status Register (Pcsrn)
0 PIT function not affected in doze mode 1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 17-3...
Page 278: Pit Modulus Register (Pmrn)
PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF. IPSBAR 0x15_0002 (PMR0) Access: Supervisor Offset: 0x16_0002 (PMR1) read/write Reset Figure 17-3. PIT Modulus Register (PMRn) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 17-4 Freescale Semiconductor...
Page 279: Pit Count Register (Pcntrn)
PIF flag issues an interrupt request to the CPU. When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 17-5...
Page 280: Free-Running Timer Operation
Eqn. 17-1 sys 2 ⁄ 17.3.4 Interrupt Operation Table 17-6 shows the interrupt request generated by the PIT. Table 17-6. PIT Interrupt Requests Interrupt Request Flag Enable Bit Timeout MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 17-6 Freescale Semiconductor...
Page 281 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 17-7...
Page 282 Programmable Interrupt Timers (PIT0–PIT1) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 17-8 Freescale Semiconductor...
Page 283: General Purpose Timer Module (Gpt)
• Programmable prescaler • Pulse-widths variable from microseconds to seconds • Single 16-bit pulse accumulator • Toggle-on-overflow feature for pulse-width modulator (PWM) generation • External timer clock input (SYNCA/SYNCB) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-1...
Page 284: Block Diagram
EDGE DETECT PAOVF GPTPACNTH:GPTPACNTL PAIF PACLK/65536 16-Bit Counter Divide System PACLK/256 Divide-by-64 PACLK by 2 Clock Interrupt Interrupt PAMOD Request Logic PAOVI PAOVF PAIF Figure 18-1. GPT Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-2 Freescale Semiconductor...
Page 285: Low-Power Mode Operation
The GPT3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. This pin is available for general-purpose I/O when not configured for timer functions. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-3...
Page 286: Syncn
GPT Channel 1 Register Low (GPTC1L) 18.6.14/18-13 0x1A_0014 GPT Channel 2 Register High (GPTC2H) 18.6.14/18-13 0x1A_0015 GPT Channel 2 Register Low (GPTC2L) 18.6.14/18-13 0x1A_0016 GPT Channel 3 Register High (GPTC3H) 18.6.14/18-13 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-4 Freescale Semiconductor...
Page 287: Gpt Input Capture/Output Compare Select Register (Gptios)
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels. These bits are read anytime (always read 0x00), write anytime. 1 Output compare enabled 0 Input capture enabled MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-5...
Page 288: Gpt Compare Force Register (Gpcforc)
OC3D bit. 18.6.3 GPT Output Compare 3 Mask Register (GPTOC3M) IPSBAR Access: Supervisor read/write Offset: 0x1A_0002 (GPTOC3M) OC3M Reset: Figure 18-4. GPT Output Compare 3 Mask Register (GPTOC3M) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-6 Freescale Semiconductor...
Page 289: Gpt Output Compare 3 Data Register (Gptoc3D)
For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 18.6.5 GPT Counter Register (GPTCNT) IPSBAR Access: Supervisor read-only Offset: 0x1A_0004 (GPTCNT) CNTR Reset Figure 18-6. GPT Counter Register (GPTCNT) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-7...
Page 290: Gpt System Control Register 1 (Gptscr1)
• Any access of the PA counter registers (GPTPACNT) clears the PAOVF and PAIF flags in GPTPAFLG. Writing logic 1s to the flags clears them only when TFFCA is clear. 1 Fast flag clearing 0 Normal flag clearing 3–0 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-8 Freescale Semiconductor...
Page 291: Gpt Toggle-On-Overflow Register (Gpttov)
0 Toggle output compare pin on overflow feature disabled 18.6.8 GPT Control Register 1 (GPTCTL1) IPSBAR Access: Supervisor read/write Offset: 0x1A_0009 (GPTCTL1) Reset: Figure 18-10. GPT Control Register 1 (GPTCTL1) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-9...
Page 292: Gpt Control Register 2 (Gptctl2)
11 Input capture on any edge (rising or falling) 18.6.10 GPT Interrupt Enable Register (GPTIE) IPSBAR Access: Supervisor read/write Offset: 0x1A_000C (GPTIE) Reset: Figure 18-12. GPT Interrupt Enable Register (GPTIE) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-10 Freescale Semiconductor...
Page 293: Gpt System Control Register 2 (Gptscr2)
0x0000 all the time. When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-11...
Page 294: Gpt Flag Register 1 (Gptflg1)
When a channel flag is set, it does not inhibit subsequent output compares or input captures. 18.6.13 GPT Flag Register 2 (GPTFLG2) IPSBAR Access: Supervisor read/write Offset: 0x1A_000F (GPTFLG2) Reset: Figure 18-15. GPT Flag Register 2 (GPTFLG2) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-12 Freescale Semiconductor...
Page 295: Gpt Channel Registers (Gptcn)
18.6.15 Pulse Accumulator Control Register (GPTPACTL) IPSBAR Access: Supervisor read/write Offset: 0x1A_0018 (GPTPACTL) PAMOD PEDGE PAOVI Reset: Figure 18-17. Pulse Accumulator Control Register (GPTPACTL) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-13...
Page 296: Pulse Accumulator Flag Register (Gptpaflg)
1 PAIF interrupt requests enabled 0 PAIF interrupt requests disabled 18.6.16 Pulse Accumulator Flag Register (GPTPAFLG) IPSBAR Access: Supervisor read/write Offset: 0x1A_0019 (GPTPAFLG) PAOVF PAIF Reset: Figure 18-18. Pulse Accumulator Flag Register (GPTPAFLG) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-14 Freescale Semiconductor...
Page 297: Pulse Accumulator Counter Register (Gptpacnt)
To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-15...
Page 298: Gpt Port Data Register (Gptport)
0 Corresponding pin configured as input 18.7 Functional Description The general purpose timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-16 Freescale Semiconductor...
Page 299: Prescaler
Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-17...
Page 300: Pulse Accumulator
3 output mode (OM3) and output level (OL3) bits. Also clear the channel 3 output compare mask bit (OC3M3). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-18 Freescale Semiconductor...
Page 301: General-Purpose I/O Ports
3. Clear the pin’s DDR bit in PORTTnDDR. 4. Write to the OMn/OLn bits in GPTCTL1 to select the output action. Table 18-23 shows how various timer settings affect pin functionality. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-19...
Page 302 An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Enabling output compare disables data register drive of the pin. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-20 Freescale Semiconductor...
Page 303: Reset
GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag. NOTE When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 18-21...
Page 304: Pulse Accumulator Input (Paif)
When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 18-22 Freescale Semiconductor...
Page 305: Dma Timers (Dtim0-Dtim3)
The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 11, “General Purpose I/O Module”) prior to configuring the DMA Timers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 19-1...
Page 306: Features
• Programmable interrupt or DMA request on input capture or reference-compare 19.2 Memory Map/Register Definition The timer module registers, shown in Table 19-1, can be modified at any time. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 19-2 Freescale Semiconductor...
Page 307: Dma Timer Mode Registers (Dtmrn)
Figure 19-2, program the prescaler and various timer modes. IPSBAR 0x0400 (DTMR0) Access: User read/write Offset: 0x0440 (DTMR1) 0x0480 (DTMR2) 0x04C0 (DTMR3) ORRI FRR Reset Figure 19-2. DTMRn Registers MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 19-3...
Page 308: Dma Timer Extended Mode Registers (Dtxmrn)
The DTXMRn register programs DMA request and increment modes for the timers. IPSBAR 0x0402 (DTXMR0) Access: User read/write Offset: 0x0442 (DTXMR1) 0x0482 (DTXMR2) 0x04C2 (DTXMR3) Reset: Figure 19-3. DTXMRn Registers MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 19-4 Freescale Semiconductor...
Page 309: Dma Timer Event Registers (Dtern)
REF and CAP flags via the internal DMA ACK signal. IPSBAR 0x0403 (DTER0) Access: User read/write Offset: 0x0443 (DTER1) 0x0483 (DTER2) 0x04C3 (DTER3) Reset: Figure 19-4. DTERn Registers MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 19-5...
Page 310: Dma Timer Reference Registers (Dtrrn)
(DTCNn) as part of the output-compare function. The reference value is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 19-6 Freescale Semiconductor...
Page 311: Dma Timer Capture Registers (Dtcrn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to DTCNn clears it. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTnIN). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 19-7...
Page 312: Functional Description
When a timer reaches the reference value selected by DTRR, it can send an output signal on DTnOUT. DTnOUT can be an active-low pulse or a toggle of the current output, as selected by the DTMRn[OM] bit. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 19-8 Freescale Semiconductor...
Page 313: Initialization/Application Information
*[ORRI] = 0, disable ref. match output *[FRR] = 1, restart mode enabled *[CLK] = 10, internal bus clock/16 *[RST] = 0, timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 19-9...
Page 314: Calculating Time-Out Values
For example, if a 66-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0xFBC5 (64453 decimal), the time-out period is: × × × ------------------- - Timeout period 64453 2.00 s Eqn. 19-2 × MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 19-10 Freescale Semiconductor...
Page 315: Queued Serial Peripheral Interface (Qspi)
Rx/Tx Data Reg. Logic Array Control QSPI_DOUT Regs Command QSPI_CS[3:0] Delay Counter Internal Bus Baud Rate Internal Bus Divide by 2 QSPI_CLK Generator Clock (f Figure 20-1. QSPI Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-1...
Page 316: Overview
Although QSPI_CSn functions as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-2 Freescale Semiconductor...
Page 317: Memory Map/Register Definition
(QMR[MSTR]) must be set for the QSPI module to operate correctly. IPSBAR 0x00_0340 (QMR) Access: User read/write Offset: MSTR DOHIE BITS CPOL CPHA BAUD Reset Figure 20-2. QSPI Mode Register (QMR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-3...
Page 318 A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: / (2 × [desired QSPI_CLK baud rate]) QMR[BAUD] = f sys/ MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-4 Freescale Semiconductor...
Page 319: Qspi Delay Register (Qdlyr)
7–0 Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-5...
Page 320: Qspi Wrap Register (Qwr)
The QIR contains QSPI interrupt enables and status flags. IPSBAR 0x00_034C (QIR) Access: User read/write Offset: WCEF ABRT SPIF WCEFB ABRTB ABRTL WCEFE ABRTE SPIFE Reset Figure 20-6. QSPI Interrupt Register (QIR) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-6 Freescale Semiconductor...
Page 321: Qspi Address Register (Qar)
A read or write to the QSPI RAM causes QAR to increment. However, the QAR does not wrap after the last queue entry within each section of the RAM. The application software must handle address range errors. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-7...
Page 322: Qspi Data Register (Qdr)
RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-8 Freescale Semiconductor...
Page 323: Functional Description
The RAM is divided into three segments: • 16 command control bytes (command RAM) • 32 transmit data bytes (transmit data RAM) • 32 receive data bytes (receive data RAM) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-9...
Page 324 The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-10 Freescale Semiconductor...
Page 325: Qspi Ram
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data words with less than 16 bits are MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-11...
Page 326: Transmit Ram
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the internal bus clock divided by two. A baud rate value of zero turns off the QSPI_CLK. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-12 Freescale Semiconductor...
Page 327: Transfer Delays
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1: × QDLYR[DTL] ----------------------------------------------- - Delay after transfer (DT = 1) Eqn. 20-3 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-13...
Page 328: Transfer Length
QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-14 Freescale Semiconductor...
Page 329: Initialization/Application Information
11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 20-15...
Page 330 Queued Serial Peripheral Interface (QSPI) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 20-16 Freescale Semiconductor...
Page 331: Uart Modules
(To DMA Controller) Figure 21-1. UART Block Diagram NOTE The DTnIN pin can clock UARTn. However, if the timers are used, then input capture mode is not available for that timer. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-1...
Page 332: Features
Line-break detection and generation • Detection of breaks originating in the middle of a character • Start/end break interrupt/status 21.2 External Signal Description Figure 21-1 shows the external and internal signal groups. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-2 Freescale Semiconductor...
Page 333: Memory Map/Register Definition
Writing control bytes into the appropriate registers controls the operation of the UART module Table 21-2 is a memory map for UART module registers. NOTE UART registers are accessible only as bytes. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-3...
Page 334 21.3.13/21-16 0x00_027C 0x00_02BC UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-4 Freescale Semiconductor...
Page 335: Uart Mode Registers 1 (Umr1N)
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-5...
Page 336: Uart Mode Register 2 (Umr2N)
Access: User read/write Offset: 0x00_0240 (UMR21) 0x00_0280 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 21-4. UART Mode Registers 2 (UMR2n) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-6 Freescale Semiconductor...
Page 337: Uart Status Registers (Usrn)
1.938 0111 1.500 1.000 1111 2.000 21.3.3 UART Status Registers (USRn) The USRn registers, shown in Figure 21-5, show the status of the transmitter, the receiver, and the FIFO. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-7...
Page 338 1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-8 Freescale Semiconductor...
Page 339: Uart Clock Select Registers (Ucsrn)
21-7, supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, RESET TRANSMITTER ENABLE cannot be specified in one command. TRANSMITTER MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-9...
Page 340 Transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS. Causes UnTXD to go high (mark) within two bit times. Any characters in the STOP BREAK transmit buffer are sent. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-10 Freescale Semiconductor...
Page 341: Uart Receive Buffers (Urbn)
FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 21-18). RB contains the character in the receiver. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-11...
Page 342: Uart Transmit Buffers (Utbn)
21-10, hold the current state and the change-of-state for UnCTS. IPSBAR 0x00_0210 (UIPCR0) Access: User read-only Offset: 0x00_0250 (UIPCR1) 0x00_0290 (UIPCR2) Reset: UnCTS Figure 21-10. UART Input Port Changed Registers (UIPCRn) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-12 Freescale Semiconductor...
Page 343: Uart Auxiliary Control Register (Uacrn)
If a UIMRn bit is cleared, state of the corresponding UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-13...
Page 344 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY equaling to 0 are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-14 Freescale Semiconductor...
Page 345: Uart Baud Rate Generator Registers (Ubg1N/Ubg2N)
Figure 21-15, show the current state of the UnCTS input. IPSBAR 0x00_0234 (UIP0) Access: User read-only Offset: 0x00_0274 (UIP1) 0x00_02B4 (UIP2) Reset: Figure 21-15. UART Input Port Registers (UIPn) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-15...
Page 346: Uart Output Port Command Registers (Uop1N/Uop0N)
16-bit divider dedicated to each UART. The clock generator might not produce standard baud rates if the internal bus clock is used, so the user must enable the 16-bit divider. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-16 Freescale Semiconductor...
Page 347: Programmable Divider
For detailed descriptions, refer Section 21.3, “Memory Map/Register Definition.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-17...
Page 348: Transmitter
UnCTS is reasserted. If transmitter is forced to send a continuous low condition by issuing a command, transmitter ignores the state of UnCTS. SEND BREAK MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-18 Freescale Semiconductor...
Page 349 Data on the UnRXD input is sampled on the rising edge of the MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-19...
Page 350: Receiver
USRn[OE] Manually asserted first time, Automatically asserted UnRTS automatically negated if overrun occurs when ready to receive UOP0[RTS] = 1 UMR2n[TXRTS] = 1 Figure 21-20. Receiver Timing Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-20 Freescale Semiconductor...
Page 351: Fifo
If the receiver is reset, the FIFO, UnRTS control, all receiver status bits, and interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-21...
Page 352: Looping Modes
UnRXD input data is ignored. • UnTXD is held marking. • The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-22 Freescale Semiconductor...
Page 353: Remote Loop-Back Mode
Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in Figure 21-24. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-23...
Page 354 If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-24 Freescale Semiconductor...
Page 355: Bus Operation
UART modules. 1. Initialize the appropriate ICRx register in the interrupt controller. 2. Unmask appropriate bits in IMR in the interrupt controller. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-25...
Page 356: Setting Up The Uart To Request Dma Service
The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-26 Freescale Semiconductor...
Page 357: Uart Module Initialization Sequence
Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit). Select character or block error mode (ERR bit). Select parity mode and type (PM and PT bits). Select number of bits per character (B/Cx bits). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-27...
Page 358 Errors? SINIT Initiate: Channel Enable Receiver Interrupts CHK1 Assert Request To Send Call CHCHK SINITR Return Save Channel Status Figure 21-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-28 Freescale Semiconductor...
Page 359 Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 21-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-29...
Page 360 Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 21-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-30 Freescale Semiconductor...
Page 361 Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR Figure 21-25. UART Mode Programming Flowchart (Sheet 4 of 5) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 21-31...
Page 362 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 21-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 21-32 Freescale Semiconductor...
Page 363: Introduction
(refer to Chapter 11, “General Purpose I/O Module”) prior to configuring the I C module. Figure 22-1 is a block diagram of the I C module. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-1...
Page 364: Features
Compatibility with I C bus standard version 2.1 • Support for 3.3-V tolerant devices • Multiple-master operation • Software-programmable for one of 50 different serial clock frequencies • Software-selectable acknowledge bit MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-2 Freescale Semiconductor...
Page 365: Memory Map/Register Definition
Slave address. Contains the specific slave address to be used by the I C module. Slave mode is the default I C mode for an address match on the bus. Reserved, must be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-3...
Page 366: I 2 C Frequency Divider Register (I2Fdr)
0x1B 1920 0x2B 0x3B 1024 0x0C 0x1C 2304 0x2C 0x3C 1280 0x0D 0x1D 2560 0x2D 0x3D 1536 0x0E 0x1E 3072 0x2E 0x3E 1792 0x0F 0x1F 3840 0x2F 0x3F 2048 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-4 Freescale Semiconductor...
Page 367: I 2 C Control Register (I2Cr)
0 No repeat start 1 Generates a repeated START condition. 1–0 Reserved, must be cleared. 22.2.4 C Status Register (I2SR) The I2SR contains bits that indicate transaction direction and status. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-5...
Page 368 Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle. RXAK 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-6 Freescale Semiconductor...
Page 369: I 2 C Data I/O Register (I2Dr)
I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-7...
Page 370: Slave Address Transmission
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Slave Address Data Byte STOP START ACK from Signal Signal Receiver Figure 22-8. Data Transfer MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-8 Freescale Semiconductor...
Page 371: Acknowledge
A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-9...
Page 372 Note: No acknowledge on the last byte Example 3: 7-bit Slave 0 Rept 7-bit Slave DATA A/A DATA DATA Address Address Master Writes to Slave Master Reads from Slave Figure 22-11. Data Transfer, Combined Format MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-10 Freescale Semiconductor...
Page 373: Clock Synchronization And Arbitration
STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. I2C_SCL I2C_SDA by Master1 I2C_SDA by Master 2 Loses Arbitration, Master2 and becomes slave-receiver I2C_SDA Figure 22-13. Arbitration Procedure MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-11...
Page 374: Handshaking And Clock Stretching
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, it may MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-12 Freescale Semiconductor...
Page 375: Post-Transfer Software Response
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-13...
Page 376: Generation Of Repeated Start
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-14 Freescale Semiconductor...
Page 377 Read Data Generate Dummy Read Dummy Read Dummy Read from I2DR from I2DR STOP Signal from I2DR from I2DR And Store Figure 22-14. Flow-Chart of Typical I C Interrupt Routine MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 22-15...
Page 378 C Interface MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 22-16 Freescale Semiconductor...
Page 379: Analog-To-Digital Converter (Adc)
1. In loop mode, the time between each conversion is 6 ADC clock cycles (1.2 μs at 5.0 MHz). Using simultaneous conversion, two samples are captured in 1.2 μs, providing an overall sample rate of 1.66 million samples per second. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-1...
Page 380: Block Diagram
Limit Status Register (ADLSTAT) 0x0000 23.4.7/23-13 0x19_0010 Zero Crossing Status Register (ADZCSTAT) 0x0000 23.4.8/23-14 0x19_0012–20 Result Registers 0-7 (ADRSLT0-7) 0x0000 23.4.9/23-14 0x19_0022–30 Low Limit Registers 0-7 (ADLLMT0-7) 0x0000 23.4.10/23-15 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-2 Freescale Semiconductor...
Page 381: Control 1 Register (Ctrl1)
START0 bit again is ignored until the end of the current scan. The ADC must be in a stable power configuration prior to writing to START0 (see Section 23.5.8, “Power Management”). 0 No action 1 Start command is issued MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-3...
Page 382 HLMTIE greater than the high limit register value. The raw result value is compared to ADHLMT[HLMT] before the offset register value is subtracted. 0 Interrupt disabled 1 Interrupt enabled MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-4 Freescale Semiconductor...
Page 383: Control 2 Register (Ctrl2)
Section 23.4.1, “Control 1 Register (CTRL1)”). 23.4.2.1 CTRL2 Under Sequential Scan Modes IPSBAR Access: read/write Offset: 0x19_0002 (CTRL2) Reset Figure 23-3. Control 2 Register (CTRL2) Under Sequential Scan Modes MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-5...
Page 384: Ctrl2 Under Parallel Scan Modes
The ADC must be in a stable power configuration prior to writing to START1 (see Section 23.5.8, “Power Management”). 0 No action 1 Start command is issued MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-6 Freescale Semiconductor...
Page 385 100 kHz 500 kHz 5.33 MHz CLK/12 00011 100 kHz 250 kHz 4.00 MHz CLK/16 00100 100 kHz 125 kHz 3.20 MHz CLK/20 — — — — — — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-7...
Page 386: Zero Crossing Control Register (Adzcc)
AN0 through AN3, sample slots SAMPLE0-3 should only contain binary values between 000 and 011. Likewise, because converter B only has access to analog inputs AN4 through AN7, sample slots MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-8 Freescale Semiconductor...
Page 387 Sample input channel select 0. The settings for this field are given in Table 23-9. SAMPLE0 IPSBAR Access: read/write Offset: 0x19_0008 (ADLST2) SAMPLE7 SAMPLE6 SAMPLE5 SAMPLE4 Reset Figure 23-7. Channel List 2 Register (ADLST2) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-9...
Page 388: Sample Disable Register (Adsdis)
DS5 is set to 1, SAMPLE0 through SAMPLE4 are sampled. However, if in parallel mode and bits DS5 or DS1 are set to 1, only SAMPLE0 and SAMPLE4 are sampled. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-10 Freescale Semiconductor...
Page 389: Status Register (Adstat)
They are not cleared automatically on the next scan sequence. IPSBAR Access: read/write Offset: 0x19_000C (ADSTAT) R CIP0 CIP1 LLMTI HLMTI RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 EOSI1 EOSI0 Reset Figure 23-9. Status Register (ADSTAT) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-11...
Page 390 It is cleared by writing 1 to all active ADLSTAT[LLS] bits. 0 No low limit interrupt request 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-12 Freescale Semiconductor...
Page 391: Limit Status Register (Adlstat)
0 Sample n is greater than or equal to the associated low-limit value 1 Sample n is less than the associated low-limit value Note: These bits are sticky, and can only be cleared by writing a 1 to them. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-13...
Page 392: Zero Crossing Status Register (Adzcstat)
Right shift with sign extend (ASR) three places to fit it into the range [0,4095] • Accept the number as presented in the register, knowing there are missing codes, because the lower three LSBs are always zero MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-14 Freescale Semiconductor...
Page 393: Low And High Limit Registers (Adllmtn And Adhlmtn)
Limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high limit and 0x0000 for the low limit. At reset, limit checking is disabled. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-15...
Page 394 0x19_0040 (ADHLMT7) HLMT Reset Figure 23-14. High Limit Registers (ADHLMTn) Table 23-16. ADHLMTn Field Descriptions Field Description Reserved, should be cleared. 14–3 High limit. HLMT 2–0 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-16 Freescale Semiconductor...
Page 395: Offset Registers (Adofsn)
The ADC module is idle when neither of the two converters has a scan in process. 4. Active state The ADC module is active when at least one of the two converters has a scan in process. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-17...
Page 396 ADC is ready for operation. During auto power-down mode, this bit indicates the current powered state of converter B. 0 ADC converter B is currently enabled 1 ADC converter B is currently disabled MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-18 Freescale Semiconductor...
Page 397 (powering-down) converter A and converter B automatically powers-down the voltage reference. 0 Manually power-up voltage reference circuit 1 Power-down voltage reference circuit is controlled by PD0 and PD1 (default) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-19...
Page 398: Voltage Reference Register (Cal)
1 AN2 Select V Source bit. This bit selects the source of the V reference for conversions. REFL REFL SEL_VREFL 0 Internal VR 1 AN6 13–0 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-20 Freescale Semiconductor...
Page 399: Functional Description
AN6-7. When configured as a differential pair, a reference to either member of the differential pair by a sample slot results in a differential measurement using that differential pair. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-21...
Page 400 SYNC inputs are ignored until the SYNC input is re-armed. This arming can occur anytime after the SYNC pulse occurs, even while the scan it initiated remains in process. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-22 Freescale Semiconductor...
Page 401: Input Mux Function
1-of-2 select function, such that either channel for the V- input of the A/D. of the two differential channels can be routed to the A/D input. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-23...
Page 402 Converter B Converter B Interface Interface Function Function V– V– REFL REFL Single-Ended Differential Channel Select Channel Select Single-Ended vs Single-Ended vs Differential Differential Figure 23-20. Input Select Mux MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-24 Freescale Semiconductor...
Page 403: Adc Sample Conversion
A mix and match combination of differential and single-ended configurations may exist. Examples: • AN0 and AN1 differential, AN2 and AN3 single-ended • AN4 and AN5 differential, AN6 and AN7 single-ended MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-25...
Page 404: Single-Ended Samples
, return 0 when the plus (+) input is at V and the minus (−) input is at REFL REFL , and scale linearly between based on the voltage difference between the two signals. REFL MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-26 Freescale Semiconductor...
Page 405: Adc Data Processing
3 bits (as shown in the ADRSLT register definition) and does not include the sign bit. The sign bit (SEXT) is calculated during subtraction of the corresponding ADOFSn offset value. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-27...
Page 406: Sequential Vs. Parallel Sampling
SAMPLE slot may refer to any of the 8 analog inputs (AN0-7), thus the same input may be referenced by more than one SAMPLE slot. Scanning is initiated when the START0 bit is written as 1 or, if the SYNC0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-28 Freescale Semiconductor...
Page 407: Scan Sequencing
Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-29...
Page 408: Scan Configuration And Control
During non-simultaneous scans, the A and B converters operate asynchronously with each converter using its own independent set of controls (CTRL1 for A and CTRL2 for B). Refer to Section 23.4.2.2, “CTRL2 Under Parallel Scan Modes,” for more information. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-30 Freescale Semiconductor...
Page 409 ADSDIS register or completes all 4 samples. If external sync is enabled (SYNC0=1), new scans are started for each sync pulse as long as the ADC has completed the previous scan (STAT[CIPn]=0). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-31...
Page 410: Interrupt Sources
This hybrid mode converts at an ADC clock rate of 100 kHz using standby current mode when active, and gates off the ADC clock and powers down the converters when idle. A startup delay of MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-32 Freescale Semiconductor...
Page 411: Power Management Details
PUDELAY values: a large value for full power-up and a smaller value for going from standby current levels to full power-up. The following paragraphs provide an explanation of how to use PUDELAY when starting the ADC up or changing modes. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-33...
Page 412: Adc Stop Mode Of Operation
23.5.9 ADC Clock 23.5.9.1 General The ADC has two external clock inputs used to drive two clock domains within the ADC module. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-34 Freescale Semiconductor...
Page 413: Description Of Clock Operation
The oscillator clock feeds an 80:1 divider, generating the auto standby clock. The auto standby clock is selected as the ADC clock during the auto standby power mode when both converters are idle. The auto MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-35...
Page 414: Adc Clock Resynchronization At Start Of Scan
ADC Conversion Clock Resynchronized Asserted ADC Scans Start System Clock Old ADC Clock ADC Clock After Resynchronization ADCA Scan ADCB Scan Figure 23-26. ADC Clock Resynchronization for Sequential and Simultaneous Parallel Modes MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-36 Freescale Semiconductor...
Page 415 REFH DDA, the amplitude of V . It is imperative that special precautions be taken to assure the voltage applied to MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 23-37...
Page 416 Dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy. The power provided to these pins is suggested to come from a low noise filtered source. Uncoupling capacitors ought to be connected between V and V MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 23-38 Freescale Semiconductor...
Page 417: Introduction
Alignment Period and Duty Counter Channel 2 Period and Duty Counter Channel 1 PWMOUT1 Period and Duty Counter Channel 0 Period and Duty Counter Figure 24-1. PWM Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-1...
Page 418: Memory Map/Register Definition
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. A 32-bit access to any of these registers results in a bus transfer error. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-2 Freescale Semiconductor...
Page 419: Pwm Enable Register (Pwme)
The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOLn] bit. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-3...
Page 420: Pwm Clock Select Register (Pwmclk)
IPSBAR 0x1B_0002 (PWMCLK) Access: User Read/Write Offset: PCLK7 PCLK5 PCLK3 PCLK1 Reset: Figure 24-4. PWM Clock Select Register (PWMCLK) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-4 Freescale Semiconductor...
Page 421: Pwm Prescale Clock Select Register (Pwmprclk)
Clock B prescaler select. These three bits control the rate of Clock B which can be used for PWM channels 3 and 7. PCKB PCKB Clock B Rate Internal bus clock ÷ 2 Internal bus clock ÷ 2 Internal bus clock ÷ 2 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-5...
Page 422: Pwm Center Align Enable Register (Pwmcae)
The PWMCTL register provides various control of the PWM module. Change the CONn(n+1) bits only when both corresponding channels are disabled. See Section 24.3.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation function. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-6 Freescale Semiconductor...
Page 423: Pwm Scale A Register (Pwmscla)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated with the following equation: Clock A ---------------------------------------- - Eqn. 24-1 Clock SA × PWMSCLA MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-7...
Page 424: Pwm Scale B Register (Pwmsclb)
Any value written to this register causes the scale counter to load the new scale value (PWMSCLB). IPSBAR 0x1B_0009 (PWMSCLB) Access: User Read/Write Offset: SCALEB Reset: Figure 24-9. PWM Scale B Register (PWMSCLB) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-8 Freescale Semiconductor...
Page 425: Pwm Channel Counter Registers (Pwmcntn)
IPSBAR 0x1B_000C (PWMCNT0) Access: User Read/Write Offset: 0x1B_000D (PWMCNT1) 0x1B_000E (PWMCNT2) 0x1B_000F (PWMCNT3) 0x1B_0010 (PWMCNT4) 0x1B_0011 (PWMCNT5) 0x1B_0012 (PWMCNT6) 0x1B_0013 (PWMCNT7) COUNT Reset: Figure 24-10. PWM Counter Registers (PWMCNTn) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-9...
Page 426: Pwm Channel Period Registers (Pwmpern)
(high time as a percentage of period) for a particular channel: ⎛ ⎞ PWMDTYn × ----------------------------- - Eqn. 24-4 Duty Cycle 1 PWMPOL PPOLn – – 100% ⎝ ⎠ PWMPERn MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-10 Freescale Semiconductor...
Page 427: Pwm Shutdown Register (Pwmsdn)
The PWM shutdown register provides emergency shutdown functionality of the PWM module. The PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared. IPSBAR 0x1B_0024 (PWMSDN) Access: Read/Write Offset: PWM7IN PWM7IL SDNEN RESTART Reset: Figure 24-13. PWM Shutdown Register (PWMSDN) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-11...
Page 428: Functional Description
PWM channel has the capability of selecting one of two clocks, the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 24-14 shows the four different clocks and how the scaled clocks are created. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-12 Freescale Semiconductor...
Page 429: Prescaled Clock (A Or B)
Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-13...
Page 430: Scaled Clock (Sa Or Sb)
The starting polarity of the output is also selectable on a per channel basis. Figure 24-15 shows a block diagram for a PWM timer. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-14 Freescale Semiconductor...
Page 431: Pwm Enable
A change in duty or period can be forced into effect immediately by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-15...
Page 432: Pwm Timer Counters
When PWMCNTn register written to any When PWM channel is enabled When PWM channel is disabled value (PWMEn = 1). Counts from last value (PWMEn = 0) in PWMCNTn. Effective period ends MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-16 Freescale Semiconductor...
Page 433: Left-Aligned Outputs
PWMn frequency = 40 MHz ÷ 4 = 10 MHz PWMn period = 100 ns ⎛ ⎞ × -- - PWMn Duty Cycle – 100% ⎝ ⎠ The output waveform generated is below: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-17...
Page 434: Center-Aligned Outputs
The PWMn duty cycle (high time as a percentage of period) is expressed as: ⎛ ⎞ PWMDTYn × ------------------------------- Duty Cycle 1 PWMPOL PPOLn – – 100% Eqn. 24-10 ⎝ ⎠ PWMPERn MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-18 Freescale Semiconductor...
Page 435: Center-Aligned Output Example
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-19...
Page 436: Pwm Boundary Cases
PWMOUT1 24.3.2.8 PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (left- or center-aligned) and 8-bit (normal) or 16-bit (concatenation): MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-20 Freescale Semiconductor...
Page 437 (indicates no duty) 0x00 Always High (indicates no period) 0x00 Always Low (indicates no period) ≥ PWMPERn Always High ≥ PWMPERn Always Low Counter = 0x00 and does not count. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 24-21...
Page 438 Pulse-Width Modulation (PWM) Module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 24-22 Freescale Semiconductor...
Page 439: Introduction
[0:15] • • • • • • • • Bus Interface Unit Clocks, Address and Data Buses, Interrupt and Test Signals Internal Bus Interface Figure 25-1. FlexCAN Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-1...
Page 440: The Can System
FlexCAN caused by a defective CAN bus or defective stations. CAN Station 1 CAN Station 2 CAN Station n ColdFire Processor FlexCAN CANTX CANRX Transceiver CAN Bus Figure 25-3. Typical CAN System MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-2 Freescale Semiconductor...
Page 441: Features
After entry into freeze mode is requested, the FlexCAN waits until an intermission or idle condition exists on the CAN bus, or until the FlexCAN enters the error passive or bus off state. After one of these MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-3...
Page 442: Module Disabled Mode
In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Transmit and receive interrupts are generated. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-4 Freescale Semiconductor...
Page 443: Listen-Only Mode
Error and Status Register 0x0000_0000 25.3.6/25-13 (ERRSTAT) 0x1C_0028 Interrupt Mask Register (IMASK) 0x0000_0000 25.3.7/25-15 0x1C_0030 Interrupt Flag Register (IFLAG) 0x0000_0000 25.3.8/25-16 0x1C_0080 Message Buffers 0–15 (MB0–15) 2048 — 25.3.9/25-16 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-5...
Page 444: Flexcan Configuration Register (Canmcr)
Clearing this bit causes the FlexCAN to exit freeze mode. Refer to Section 25.1.3.2, “Freeze Mode,” more information. 0 FlexCAN ignores the BKPT signal and the CANMCR[HALT] bit. 1 FlexCAN module enabled to enter debug mode. Reserved, must be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-6 Freescale Semiconductor...
Page 445 The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode. Maximum MBs in Use = MAXMB + 1 Note: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-7...
Page 446: Flexcan Control Register (Canctrl)
1–7. Eqn. 25-4 Phase buffer segment 2 (PSEG2 + 1) time quanta Bus off interrupt mask. BOFFMSK 0 Bus off interrupt disabled 1 Bus off interrupt enabled MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-8 Freescale Semiconductor...
Page 447 Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission. LBUF 0 Message buffer with lowest ID is transmitted first 1 Lowest numbered buffer is transmitted first MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-9...
Page 448: Flexcan Free Running Timer Register (Timer)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-6. FlexCAN Timer Register (TIMER) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-10 Freescale Semiconductor...
Page 449: Rx Mask Registers (Rxgmask, Rx14Mask, Rx15Mask)
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB14 Match for Extended Format (MB3). Match for Normal Format. (MB2). Mismatch for MB3 because of ID0. Mismatch for MB2 because of ID28. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-11...
Page 450: Flexcan Error Counter Register (Errcnt)
If the value of TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset to zero. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-12 Freescale Semiconductor...
Page 451: Flexcan Error And Status Register (Errstat)
Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to Section 25.4.1, “Interrupts.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-13...
Page 452 TXWRN 1 TXErrCounter ≥ 96 Receiver error status flag. Reflects the status of the FlexCAN receive error counter. 0 Receive error counter < 96 RXWRN 1 RxErrCounter ≥ 96 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-14 Freescale Semiconductor...
Page 453: Interrupt Mask Register (Imask)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-10. FlexCAN Interrupt Mask Register (IMASK) MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-15...
Page 454: Interrupt Flag Register (Iflag)
(0x1C_0000). The 256-byte message buffer space is fully used by the16 message buffer structures. Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-16 Freescale Semiconductor...
Page 455 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 25-13. Message Buffer Structure for Extended and Standard Frames MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-17...
Page 456 Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from 23–16, the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame. 15–8, 7–0 DATA MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-18 Freescale Semiconductor...
Page 457 MB automatically returns to the INACTIVE state. 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-19...
Page 458: Rx Individual Masking Registers (Rximr0-15)
The CPU prepares or changes an MB for transmission by writing the following: 1. Control/status word to hold Tx MB inactive (CODE = 1000) 2. ID word 3. Data bytes MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-20 Freescale Semiconductor...
Page 459: 25.3.13 Arbitration Process
CAN protocol rules. FlexCAN transmits up to 8 data bytes, even if the data length code (DLC) value is bigger. Refer to Section 25.3.16.1, “Serial Message Buffers (SMBs),” for more information on serial message buffers. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-21...
Page 460: 25.3.14 Receive Process
The received identifier field is always stored in the matching MB, thus the contents of the ID field in an MB may change if the match was due to masking. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-22 Freescale Semiconductor...
Page 461: 25.3.14.1 Self-Received Frames
If the CPU wants to change the function of an active MB, the recommended procedure is to put the module into freeze mode and then change the CODE field of that MB. This is a safe procedure because the MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-23...
Page 462: 25.3.16.3 Locking And Releasing Message Buffers
Suppose, for example, that FlexCAN has already received and stored a message into one of the MBs. Suppose now that the CPU decides to read that MB at the same time another message with the same ID MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-24 Freescale Semiconductor...
Page 463: 25.3.17 Can Protocol Related Frames
Overload frame transmissions are not initiated by the FlexCAN unless certain conditions are detected on the CAN bus. These conditions include detection of a dominant bit in the following: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-25...
Page 464: 25.3.18 Time Stamp
1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-26 Freescale Semiconductor...
Page 465 It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-27...
Page 466: Initialization/Application Information
Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW. b) Select the S-clock rate by programming the PRESDIV field. c) Select the internal arbitration mode via the LBUF bit. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-28 Freescale Semiconductor...
Page 467: Interrupts
MB caused the interrupt. The other two interrupt sources (bus off and error) act in the same way, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located in the CANCTRL register. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 25-29...
Page 468 FlexCAN MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 25-30 Freescale Semiconductor...
Page 469: Debug Module
External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See Section 26.6, “Real-Time Debug Support.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-1...
Page 470: Signal Descriptions
Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-2 Freescale Semiconductor...
Page 471: Real-Time Trace Support
PST[3:0] and DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on the DDATA port, one nibble at a time starting with the least significant bit (lsb). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-3...
Page 472 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until the processor is restarted or reset. See Section 26.5.1, “CPU Halt.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-4 Freescale Semiconductor...
Page 473: Begin Execution Of Taken Branch (Pst = 0X5)
DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST equals 0x0) until space is available in the FIFO. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-5...
Page 474: Memory Map/Register Definition
PC breakpoint register 2 (PBR2) See Section 26.4.6/26-15 0x1B PC breakpoint register 3 (PBR3) See Section 26.4.6/26-15 Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care). MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-6 Freescale Semiconductor...
Page 475: Shared Debug Resources
BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the RDMREG WDMREG commands. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-7...
Page 476 1 Disables the generation of the PSTDDATA output signals, and forces these signals to remain quiescent Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. Only commands from the external development system can modify IPW. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-8 Freescale Semiconductor...
Page 477 On receipt of the command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. 3–0 Reserved, should be cleared. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-9...
Page 478: Bdm Address Attribute Register (Baar)
(TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the command. WDMREG MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-10 Freescale Semiconductor...
Page 479 Read/write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-11...
Page 480: Trigger Definition Register (Tdr)
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-12 Freescale Semiconductor...
Page 481 Level 2 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-13...
Page 482 Note: Debug Rev A only had the ‘AND’ condition available for the triggers. Enable level 1 breakpoint. Global enable for the breakpoint trigger. L1EBL 0 Disables all level 1 breakpoints 1 Enables all level 1 breakpoint triggers MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-14 Freescale Semiconductor...
Page 483: Program Counter Breakpoint/Mask Registers (Pbr0-3, Pbmr)
(PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-15...
Page 484 1 PBR is enabled. Figure 26-9 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the command. PBMR only masks PBR0. WDMREG MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-16 Freescale Semiconductor...
Page 485: Address Breakpoint Registers (Ablr, Abhr)
ABLR. Table 26-14. ABHR Field Description Field Description 31–0 High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-17...
Page 486: Data Breakpoint And Mask Registers (Dbr, Dbmr)
The DBR supports aligned and misaligned references. Table 26-17 shows relationships between processor address, access size, and location within the 32-bit data bus. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-18 Freescale Semiconductor...
Page 487: Background Debug Mode (Bdm)
When a pending condition is asserted, the processor halts execution at the next sample point. See Section 26.6.1, “Theory of Operation.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-19...
Page 488: Bdm Serial Interface
17-bit packets composed of a status/control bit and a 16-bit data word. As shown Figure 26-13, all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is high; DSI is sampled and DSO is driven. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-20 Freescale Semiconductor...
Page 489: Receive Packet Format
Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 26.5.2.1 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit Data Figure 26-14. Receive BDM Packet MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-21...
Page 490: Transmit Packet Format
BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. See Table 26-22 for register address encodings. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-22 Freescale Semiconductor...
Page 491 - Parallel: Command is executed in parallel with CPU activity. 0x4 is a three-bit field. Freescale reserves unassigned command opcodes. All unused command formats within any revision level perform a and return the illegal command response. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-23...
Page 492: Coldfire Bdm Command Format
Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-24 Freescale Semiconductor...
Page 493: Command Sequence Diagrams
• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-25...
Page 494: Command Set Descriptions
BERR ’NOT READY’ Figure 26-19. Command Sequence RAREG RDREG Operand Data: None Result Data: The contents of the selected register are returned as a longword value, most-significant word first. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-26 Freescale Semiconductor...
Page 495: Write A/D Register (Wareg/Wdreg)
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-27...
Page 496 Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001 (S equals 1) is returned if a bus error occurs. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-28 Freescale Semiconductor...
Page 497: Write Memory Location (Write)
Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 26-24. Command Format WRITE MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-29...
Page 498: Dump Memory Block (Dump)
The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the current DUMP operand size, and store the updated address in the temporary register. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-30 Freescale Semiconductor...
Page 499 ’NOT READY’ LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD ’ILLEGAL’ ’NOT READY’ BERR ’NOT READY’ Figure 26-27. Command Sequence DUMP Operand Data: None MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-31...
Page 500: Fill Memory Block (Fill)
The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 26-28. Command Format FILL MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-32 Freescale Semiconductor...
Page 501: Resume Execution (Go)
BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Figure 26-30. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’ Figure 26-31. Command Sequence MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-33...
Page 502: No Operation (Nop)
PC for performance monitoring. The SYNC execution of this command is considerably less obtrusive to the real-time operation of an application than command sequence. HALT READ RESUME Command Formats: MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-34 Freescale Semiconductor...
Page 503: Read Control Register (Rcreg)
32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same the processor’s MOVEC instruction uses. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 26-36. Command/Result Formats RCREG MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-35...
Page 504: Bdm Accesses Of The Stack Pointer Registers (A7: Ssp And Usp)
SR[S] = 1 then A7 = Supervisor Stack Pointer OTHER_A7 = User Stack Pointer MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-36 Freescale Semiconductor...
Page 505: Write Control Register (Wcreg)
Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-37...
Page 506: Read Debug Module Register (Rdmreg)
The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-38 Freescale Semiconductor...
Page 507: Real-Time Debug Support
Table 26-24, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-39...
Page 508 The debug interrupt handler can use supervisor instructions to save the necessary context, such as the state of all program-visible registers into a reserved memory area. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-40 Freescale Semiconductor...
Page 509: Emulator Mode
After the debug module bus cycle, the processor reclaims the bus. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-41...
Page 510: Processor Status, Debug Data Definition
In this definition, the ‘y’ suffix generally denotes the source, and ‘x’ denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-42 Freescale Semiconductor...
Page 511 PST = 0x1, {PST = 0xB, DD = source operand} divs.w <ea>y,Dx PST = 0x1, {PST = 0x9, DD = source operand} divu.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand} MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-43...
Page 512 PST = 0x1, {PST = 0x9, DD = source operand} neg.l PST = 0x1 negx.l PST = 0x1 PST = 0x1 not.l PST = 0x1 or.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand} MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-44 Freescale Semiconductor...
Page 513 PST = 0x4, {PST = 0x8, DD = source operand wddata.l <ea>y PST = 0x4, {PST = 0xB, DD = source operand wddata.w <ea>y PST = 0x4, {PST = 0x9, DD = source operand MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-45...
Page 514 PST = 0x1 move.l MASK,Rx PST = 0x1 msac.l Ry,Rx PST = 0x1 msac.l Ry,Rx,<ea>y,Rw PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-46 Freescale Semiconductor...
Page 515: Supervisor Instruction Set
ColdFire processor is in the given mode. 26.8 Freescale-Recommended BDM Pinout The ColdFire BDM connector is a 26-pin Berg connector arranged 2 x 13 as shown below. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 26-47...
Page 516 EVDD PST3 PST2 PST1 PST0 DDATA3 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK IVDD Pins reserved for BDM developer use. Supplied by target Figure 26-44. Recommended BDM Connector MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 26-48 Freescale Semiconductor...
Page 517: Ieee 1149.1 Test Access Port (Jtag)
4-bit TAP Instruction Decoder 4-bit TAP Instruction Register JTAG_EN TCLK Disable DSCLK TMS/BKPT Force BKPT = 1 TRST/DSCLK JTAG Module to Debug Module BKPT DSCLK Figure 27-1. JTAG Block Diagram MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 27-1...
Page 518: Features
The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is selected; if it is high, the JTAG is selected. Table 27-2 summarizes the pin function selected depending on JTAG_EN logic state. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 27-2 Freescale Semiconductor...
Page 519: Test Clock Input (Tclk)
(lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 27-3...
Page 520: Test Reset/Development Serial Clock (Trst/Dsclk)
Reset Figure 27-2. 4-Bit Instruction Register (IR) 27.3.2 IDCODE Register The IDCODE is a read-only register; its value is chip dependent. For more information, see Section 27.4.3.1, “IDCODE Instruction.” MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 27-4 Freescale Semiconductor...
Page 521: Bypass Register
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 27-5...
Page 522: Boundary Scan Register
TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 27-6 Freescale Semiconductor...
Page 523: Jtag Instructions
Selects boundary scan register while applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 27-7...
Page 524: Idcode Instruction
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in initialization data. The update-DR state and the falling edge of TCLK can then transfer this data to MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 27-8 Freescale Semiconductor...
Page 525: Extest Instruction
After the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller and the MCU to return to normal operation. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor 27-9...
Page 526: Clamp Instruction
However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 27-10 Freescale Semiconductor...
Page 527 MAC Accumulator 0 ACC0 CPU @ 0x80E Status Register CPU @ 0x80F Program Counter CPU @ 0xC04 Flash Base Address Register FLASHBAR CPU @ 0xC05 RAM Base Address Register RAMBAR MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 528 Edge Port IPSBAR + 0x14_0000 Reserved IPSBAR + 0x15_0000 Programmable Interval Timer 0 IPSBAR + 0x16_0000 Programmable Interval Timer 1 IPSBAR + 0x17_0000 Reserved IPSBAR + 0x18_0000 Reserved IPSBAR + 0x19_0000 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 529 IPSBAR + 0x002C Peripheral Access Control Register 8 PACR8 IPSBAR + 0x0030 Grouped Peripheral Access Control Register 0 GPACR0 IPSBAR + 0x0031 Grouped Peripheral Access Control Register 1 GPACR1 DMA Registers MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 530 (Write) UART Interrupt Mask Register 0 UIMR0 IPSBAR + 0x0218 (Read) Reserved UART Baud Rate Generator Register 10 UBG10 IPSBAR + 0x021C (Read) Reserved UART Baud Rate Generator Register 20 UBG20 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 531 UART Mode Register 2 UMR12, UMR22 IPSBAR + 0x0284 (Read) UART Status Register 2 USR2 (Write) UART Clock Select Register 2 UCSR2 IPSBAR + 0x0288 (Read) Reserved (Write) UART Command Register 2 UCR2 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 532 QSPI Address Register IPSBAR + 0x0354 QSPI Data Register DMA Timer Registers IPSBAR + 0x0400 DMA Timer Mode Register 0 DTMR0 IPSBAR + 0x0402 DMA Timer Extended Mode Register 0 DTXMR0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 533 Interrupt Force Register Low 0 INTFRCL0 IPSBAR + 0x0C18 Interrupt Request Level Register 0 IRLR0 IPSBAR + 0x0C19 Interrupt Acknowledge Level and Priority Register 0 IACKLPR0 IPSBAR + 0x0C41 Interrupt Control Register 0-01 ICR001 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 534 IPSBAR + 0x0C5F Interrupt Control Register 0-31 ICR031 IPSBAR + 0x0C60 Interrupt Control Register 0-32 ICR032 IPSBAR + 0x0C61 Interrupt Control Register 0-33 ICR033 IPSBAR + 0x0C62 Interrupt Control Register 0-34 ICR034 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 535 IPSBAR + 0x0CE4 Level 1 Interrupt Acknowledge Register 0 L1IACK0 IPSBAR + 0x0CE8 Level 2 Interrupt Acknowledge Register 0 L2IACK0 IPSBAR + 0x0CEC Level 3 Interrupt Acknowledge Register 0 L3IACK0 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor...
Page 536 Port TC Output Data Register PORTTC IPSBAR + 0x10_0010 Port TD Output Data Register PORTTD IPSBAR + 0x10_0011 Port UA Output Data Register PORTUA IPSBAR + 0x10_0012 Port UB Output Data Register PORTUB MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 A-10 Freescale Semiconductor...
Page 537 Reserved — IPSBAR + 0x10_002F Reserved — IPSBAR + 0x10_0030 Port NQ Pin Data/Set Data Register PORTNQP/ SETNQ IPSBAR + 0x10_0031 Port DD Pin Data/Set Data Register PORTDDP/ SETDD MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor A-11...
Page 538 IPSBAR + 0x10_004A Port TA Clear Output Data Register CLRTA IPSBAR + 0x10_004B Port TC Clear Output Data Register CLRTC IPSBAR + 0x10_004C Port TD Clear Output Data Register CLRTD MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 A-12 Freescale Semiconductor...
Page 539 IPSBAR + 0x10_0069 Reserved — IPSBAR + 0x10_006A Reserved — IPSBAR + 0x10_006B Reserved — IPSBAR + 0x10_006C Reserved — IPSBAR + 0x10_006D Reserved — IPSBAR + 0x10_006E Reserved — MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor A-13...
Page 540 EPORT Pin Data Register EPPDR IPSBAR + 0x13_0006 EPORT Flag Register EPFR Backup Watchdog Timer Registers IPSBAR + 0x14_0000 Backup Watchdog Timer Control Register IPSBAR + 0x14_0002 Backup Watchdog Timer Modulus Register MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 A-14 Freescale Semiconductor...
Page 541 GPT Compare Force Register GPTCFORC IPSBAR + 0x1A_0002 GPT Output Compare 3 Mask Register GPTOC3M IPSBAR + 0x1A_0003 GPT Output Compare 3 Data Register GPTOC3D IPSBAR + 0x1A_0004 GPT Counter Register GPTCNT MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor A-15...
Page 542 PWM Channel Counter Register 2 PWMCNT2 IPSBAR + 0x1B_000F PWM Channel Counter Register 3 PWMCNT3 IPSBAR + 0x1B_0010 PWM Channel Counter Register 4 PWMCNT4 IPSBAR + 0x1B_0011 PWM Channel Counter Register 5 PWMCNT5 MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 A-16 Freescale Semiconductor...
Page 543 IPSBAR + 0x1C_001C Error Counter Register ERRCNT IPSBAR + 0x1C_0020 Error and Status ERRSTAT IPSBAR + 0x1C_0024 Reserved IPSBAR + 0x1C_0028 Interrupt Mask Register IMASK IPSBAR + 0x1C_002C Reserved MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 Freescale Semiconductor A-17...
Page 544 UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3 A-18 Freescale Semiconductor...

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About this Book

Chapter 1 Overview

Chapter 2 Signal Descriptions

Chapter 3 Coldfire Core

Chapter 4 Multiply-Accumulate Unit (MAC)

Chapter 5 Static RAM (SRAM)

Chapter 6 Clock Module

Chapter 7 Power Management

Chapter 8 Chip Configuration Module (CCM)

Chapter 9 Reset Controller Module

Chapter 10 System Control Module (SCM)

Chapter 11 General Purpose I/O Module

Chapter 12 Interrupt Controller Module

Chapter 13 Edge Port Module (EPORT)

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