Freescale Semiconductor MCF52100 Manuals

Freescale Semiconductor MCF52100 Manuals

Manuals and User Guides for Freescale Semiconductor MCF52100. We have 1 Freescale Semiconductor MCF52100 manual available for free PDF download: Reference Manual

Freescale Semiconductor MCF52100 Reference Manual

Freescale Semiconductor MCF52100 Reference Manual (530 pages)

ColdFire Integrated Microcontroller

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 6 MB

Table of Contents

Signal Descriptions

3
- Table of Contents
  3
- MCF52110 Coldfire® Integrated Microcontroller Reference Manual
  17
- MCF52110 Family Configurations
  18
- Part Numbers and Packaging
  19
  - Features
    20
- Chapter 1
  
  24
  - V2 Core Overview
    24
  - Jtag
    25
  - Power Management
    26
- Chapter 21 DMA Timers (DTIM0–DTIM3)
  
  27
  - Software Watchdog Timer
    28
  - Gpio
    29
  - Introduction
    31
- Chapter 2
  
  32
  - Pin Functions
    32
  - Reset Signals
    37
  - External Interrupt Signals
    38
  - UART Module Signals
    39
  - ADC Signals
    40
  - Ezport Signal Descriptions
    42
    
    Introduction
    43
  - Memory Map/Register Description
    44
- Chapter 3
  
  46
  - Data Registers (D0–D7)
    46
  - Condition Code Register (CCR)
    47
  - Program Counter (PC)
    48
  - Status Register (SR)
    49
  - Memory Base Address Registers (RAMBAR, FLASHBAR)
    50
  - Instruction Set Architecture (ISA_A+)
    56
  - Exception Processing Overview
    57
  - Processor Exceptions
    60
  - Instruction Execution Timing
    67
    
    Introduction
    75
    
    Memory Map/Register Definition
    76
- Chapter 4
  
  78
  - Mask Register (MASK)
    78
  - Accumulator Register (ACC)
    79
  - Functional Description
    80
  - Fractional Operation Mode
    81
  - MAC Instruction Set Summary
    82
  - MAC Instruction Execution Times
    83
Table of Contents

86
- If (MACSR.OMC == 0 || MACSR.V == 0) then
  87
- If (Sz == Word)
  87
- Macsr.V = 0
  87
- Perform the Multiply */ Product[63:0] = Operandy[31:0] * Operandx[31:0]
  87
- Check for Accumulation Overflow
  88
- If (Accumulationoverflow == 1)
  88
  - Saturationmode Enabled
    88
  - Then {MACSR.V = 1
    88
- If (Result[31:0] == 0X0000_0000)
  88
  - Else MACSR.Z = 0
    88
  - Then MACSR.Z = 1
    88
  - Introduction
    89
  - SRAM Base Address Register (RAMBAR)
    90
  - Initialization/Application Information
    91
  - SRAM Initialization Code
    92
  - Introduction
    93
  - Memory Map and Registers
    98
  - Functional Description
    109
  - System Clock Generation
    110
  - Memory Map and Register Definition
    122
  - Introduction
    127
- Chapter 6
  
  94
  - MACSR.N = Result
    88
  - Transfer the Result to the Accumulator */ Acc[31:0] = Result[31:0]
    88
  - RTC Mode
    94
    
    Block Diagram
    95
    
    Signal Descriptions
    96
  - Extal
    97
- Chapter 8
  
  128
- Chapter 9 RCON
  
  144
  - Memory Map
    145
  - Introduction
    149
- Chapter 10 Signals
  
  150
  - Reset Control Register (RCR)
    151
  - Reset Status Register (RSR)
    152
  - Functional Description
    153
  - Reset Control Flow
    155
  - Concurrent Resets
    157
  - Introduction
    159
  - Modes of Operation
    160
  - Functional Description
    171
  - Alarm
    172
- Chapter 11
  
  172
  - Code Example for Initializing the Real-Time Clock
    173
    
    Introduction
    175
    
    Memory Map and Register Definition
    176
    
    Register Descriptions
    177
- Chapter 12
  
  178
  - Memory Base Address Register (RAMBAR)
    178
  - Core Reset Status Register (CRSR)
    180
  - Core Watchdog Control Register (CWCR)
    181
  - Core Watchdog Service Register (CWSR)
    182
  - Internal Bus Arbitration
    183
    
    Arbitration Algorithms
    184
  - System Access Control Unit (SACU)
    186
    
    Memory Map/Register Definition
    187
    
    Introduction
    193
- Chapter 22
  
  194
  - Overview
    194
  - Register Descriptions
    196
  - Port Data Direction Registers (Ddrn)
    197
  - Port Pin Data/Set Data Registers (Portnp/Setn)
    199
  - Port Clear Output Data Registers (Clrn)
    201
  - Pin Assignment Registers
    202
  - Pad Control Registers
    205
  - Ports Interrupts
    207
  - K/Coldfire Interrupt Architecture Overview
    209
- Chapter 14 Interrupt Controller Theory of Operation
  
  210
- Chapter 17
  
  212
  - Memory Map
    212
  - Register Descriptions
    214
  - Interrupt Mask Register (Imrhn, Imrln)
    215
  - Interrupt Force Registers (Intfrchn, Intfrcln)
    216
  - Interrupt Request Level Register (Irlrn)
    218
  - Interrupt Control Registers (Icrnx)
    219
  - Software and Level M IACK Registers (Swiackn, Lmiackn)
    223
  - Global Level M IACK Registers (Glmiack)
    224
  - Introduction
    227
  - Low-Power Mode Operation
    228
- Chapter 15
  
  229
  - EPORT Pin Assignment Register (EPPAR)
    229
  - EPORT Data Direction Register (EPDDR)
    230
  - Edge Port Data Register (EPDR)
    231
  - Edge Port Flag Register (EPFR)
    232
    
    Introduction
    233
    
    Features
    234
  - DMA Transfer Overview
    235
    
    DMA Request Control (DMAREQC)
    236
    
    Source Address Registers (Sarn)
    237
    
    Byte Count Registers (Bcrn) and DMA Status Registers (Dsrn)
    238
    
    DMA Control Registers (Dcrn)
    240
    
    Functional Description
    243
    
    Transfer Requests (Cycle-Steal and Continuous Modes)
    244
    
    Channel Initialization and Startup
    245
    
    Data Transfer
    246
    
    Termination
    247
    
    Introduction
    249
    
    Features
    250
    
    External Signal Description
    251
    
    Flash Base Address Register (FLASHBAR)
    252
  - Register Descriptions
    255
    
    Functional Description
    264
    
    Flash Normal Mode
    265
    
    Flash Security Operation
    278
    
    Features
    281
  - External Signal Description
    282
  - Command Definition
    283
- Chapter 18 Command Descriptions
  
  284
  - Functional Description
    287
    
    Initialization/Application Information
    288
    
    Introduction
    289
  - Memory Map/Register Definition
    290
    
    PIT Control and Status Register (Pcsrn)
    291
    
    PIT Modulus Register (Pmrn)
    292
    
    PIT Count Register (Pcntrn)
    293
    
    Free-Running Timer Operation
    294
- Chapter 13
  
  297
  - Introduction
    297
- Chapter 27
  
  298
  - Block Diagram
    298
- Chapter 19
  
  299
  - Low-Power Mode Operation
    299
- Chapter 20 Syncn
  
  300
  - GPT Input Capture/Output Compare Select Register (GPTIOS)
    301
  - GPT Compare Force Register (GPCFORC)
    302
  - GPT Output Compare 3 Data Register (GPTOC3D)
    303
  - GPT System Control Register 1 (GPTSCR1)
    304
  - GPT Toggle-On-Overflow Register (GPTTOV)
    305
  - GPT Control Register 2 (GPTCTL2)
    306
  - GPT System Control Register 2 (GPTSCR2)
    307
  - GPT Flag Register 1 (GPTFLG1)
    308
  - GPT Channel Registers (Gptcn)
    309
  - Pulse Accumulator Flag Register (GPTPAFLG)
    310
  - Pulse Accumulator Counter Register (GPTPACNT)
    311
  - GPT Port Data Register (GPTPORT)
    312
  - Prescaler
    313
  - Pulse Accumulator
    314
  - General-Purpose I/O Ports
    315
  - Reset
    317
    
    Pulse Accumulator Input (PAIF)
    318
    
    Introduction
    319
  - Features
    320
    
    DMA Timer Mode Registers (Dtmrn)
    321
    
    DMA Timer Extended Mode Registers (Dtxmrn)
    322
    
    DMA Timer Event Registers (Dtern)
    323
    
    DMA Timer Reference Registers (Dtrrn)
    324
    
    DMA Timer Capture Registers (Dtcrn)
    325
  - Functional Description
    326
  - Initialization/Application Information
    327
    
    Calculating Time-Out Values
    328
  - Introduction
    329
    
    Overview
    330
  - Memory Map/Register Definition
    331
    
    QSPI Delay Register (QDLYR)
    333
    
    QSPI Wrap Register (QWR)
    334
    
    QSPI Address Register (QAR)
    335
    
    QSPI Data Register (QDR)
    336
  - Functional Description
    337
    
    Qspi Ram
    339
    
    Baud Rate Selection
    340
    
    Transfer Delays
    341
    
    Transfer Length
    342
  - Initialization/Application Information
    343
  - Introduction
    345
    
    Features
    346
  - External Signal Description
    347
- Chapter 23
  
  349
  - UART Mode Registers 1 (Umr1N)
    349
  - UART Mode Register 2 (Umr2N)
    350
  - UART Status Registers (Usrn)
    351
  - UART Clock Select Registers (Ucsrn)
    353
  - UART Receive Buffers (Urbn)
    355
  - UART Transmit Buffers (Utbn)
    356
  - UART Auxiliary Control Register (Uacrn)
    357
  - UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
    359
  - UART Output Port Command Registers (Uop1N/Uop0N)
    360
  - Transmitter and Receiver Operating Modes
    362
  - Looping Modes
    366
  - Multidrop Mode
    368
  - Bus Operation
    370
  - UART Module Initialization Sequence
    372
    
    Introduction
    379
    
    Block Diagram
    380
  - Features
    381
  - Functional Description
    386
- Chapter 24
  
  387
  - Slave Address Transmission
    387
  - Acknowledge
    388
  - Clock Synchronization and Arbitration
    390
  - Handshaking and Clock Stretching
    391
  - Post-Transfer Software Response
    392
  - Generation of Repeated START
    393
  - Introduction
    395
- Chapter 28
  
  396
  - Block Diagram
    396
- Chapter 25
  
  397
  - Control 1 Register (CTRL1)
    397
  - Control 2 Register (CTRL2)
    399
  - Zero Crossing Control Register (ADZCC)
    402
  - Sample Disable Register (ADSDIS)
    404
  - Status Register (ADSTAT)
    405
  - Limit Status Register (ADLSTAT)
    407
  - Zero Crossing Status Register (ADZCSTAT)
    408
  - Low and High Limit Registers (Adllmtn and Adhlmtn)
    409
  - Offset Registers (Adofsn)
    411
  - Voltage Reference Register (CAL)
    414
  - Functional Description
    415
  - Input MUX Function
    417
  - ADC Sample Conversion
    419
  - ADC Data Processing
    421
  - Sequential Vs. Parallel Sampling
    422
  - Scan Sequencing
    423
  - Scan Configuration and Control
    424
  - Interrupt Sources
    426
  - ADC Clock
    428
    
    Introduction
    433
    
    Memory Map/Register Definition
    434
- Chapter 26
  
  435
  - PWM Enable Register (PWME)
    435
  - PWM Polarity Register (PWMPOL)
    436
  - PWM Prescale Clock Select Register (PWMPRCLK)
    437
  - PWM Center Align Enable Register (PWMCAE)
    438
  - PWM Control Register (PWMCTL)
    439
  - PWM Scale a Register (PWMSCLA)
    440
  - PWM Scale B Register (PWMSCLB)
    441
  - PWM Channel Period Registers (Pwmpern)
    442
  - PWM Channel Duty Registers (Pwmdtyn)
    443
  - PWM Shutdown Register (PWMSDN)
    444
  - Functional Description
    445
  - PWM Channel Timers
    447
  - Introduction
    455
  - Signal Descriptions
    456
  - Real-Time Trace Support
    457
    
    Begin Execution of Taken Branch (PST = 0X5)
    459
    
    Memory Map/Register Definition
    460
    
    Shared Debug Resources
    461
    
    BDM Address Attribute Register (BAAR)
    464
    
    Trigger Definition Register (TDR)
    466
    
    Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
    469
    
    Address Breakpoint Registers (ABLR, ABHR)
    471
    
    Data Breakpoint and Mask Registers (DBR, DBMR)
    472
  - Background Debug Mode (BDM)
    473
    
    BDM Serial Interface
    474
    
    BDM Command Set
    476
  - Real-Time Debug Support
    493
    
    Concurrent BDM and Processor Operation
    495
  - Processor Status, Debug Data Definition
    496
    
    Supervisor Instruction Set
    501
    
    Introduction
    503
  - Features
    504
    
    Test Clock Input (TCLK)
    505
    
    Test Reset/Development Serial Clock (TRST/DSCLK)
    506
    
    Bypass Register
    507
    
    Functional Description
    508
    
    JTAG Instructions
    509
    
    Initialization/Application Information
    512

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