2 MFD sys max sys max Where f is the maximum system frequency for the particular MCF5282 device sys(max) (66MHz or 80MHz) Section 10.3.6/Page 10-11 Include the following text in the section description and as a note in Figure 10-9.
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Figure 17-26/Page 17-41 Change EMRBR register address from “IPSBAR + 0x11B8” to “IPSBAR + 0x1188”. Section 20.5.13/Page 20-12 Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2 register. MCF5282 User’s Manual Errata, Rev. 15 Freescale Semiconductor...
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= +2.0mA” to “I = +5.0mA” Table 33-8/Page 33-7 In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device were listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol , as shown below:...
--------------------------------------------- - f 2 MFD sys max sys max Where f is the maximum system frequency for the particular MCF5282 device sys(max) (66MHz or 80MHz) 10.3.2/10-8 Add the following note: ‘If an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the...
Table 33-8/33-7 In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device were listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol , as shown below:...
Add the following note to the SPV bit description: “The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM. For more information, see Section 8.4.2, ‘Memory Base Address Register (RAMBAR).’” MCF5282 User’s Manual Errata, Rev. 15 Freescale Semiconductor...
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0–6.” Figure 12-4/12-8 Change CSCRn to reflect that AA is set to ‘1’ at reset. 13.5/13-15 Remove final paragraph. The paragraph incorrectly states that the MCF5282 does not have a bus monitor. MCF5282 User’s Manual Errata, Rev. 15 Freescale Semiconductor...
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+85 ° ° MCF5281CVF80 MCF5281 RISC Microprocessor, 256 MAPBGA 80 MHz to +85 ° ° MCF5282CVF66 MCF5282 RISC Microprocessor, 256 MAPBGA 66.67 MHz -40 to +85 ° ° MCF5282CVF80 MCF5282 RISC Microprocessor, 256 MAPBGA 80 MHz to +85 Chapter 33 Delete references to ‘TA = TL to TH’.
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ACTV READ DACR[CASL] = 2 Figure 33-5. SDRAM Read Cycle Table 14-3/14-11 Change ‘Internal Pull-Up’ column to pull-up indications in the table below. Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function Pin Functions Internal Primary MAPBGA Pin Description...
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Errata for Revision 1.0 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions Internal Primary MAPBGA Pin Description Pull-up Primary Secondary Tertiary XTAL — — Crystal drive — CLKOUT — — Clock out — Chip Configuration/Mode Selection CLKMOD0 —...
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Errata for Revision 1.0 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions Internal Primary MAPBGA Pin Description Pull-up Primary Secondary Tertiary SIZ0 SYNCB Transfer size SYNCA Transfer start SYNCB Transfer in progress Chip Selects L16:L15:L14:L13...
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Errata for Revision 1.0 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions Internal Primary MAPBGA Pin Description Pull-up Primary Secondary Tertiary FlexCAN CANRX PAS3 URXD2 FlexCAN Receive data — CANTX PAS2 UTXD2 FlexCAN Transmit data —...
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Errata for Revision 1.0 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions Internal Primary MAPBGA Pin Description Pull-up Primary Secondary Tertiary DTOUT1 PTD2 URTS1/ U1/U0 Request to Send — URTS0 DTIN0 PTD1 UCTS1/ U1/U0 Clear to Send —...
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Errata for Revision 1.0 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions Internal Primary MAPBGA Pin Description Pull-up Primary Secondary Tertiary AN52 PQA0 Analog channel 52 — AN53 PQA1 Analog channel 53 — AN55 PQA3...
11/2003 • Added errata for PIT timer timeout equation. • Added I2CR write errata. • Added errata for ‘Internal Pull-Up’ column in ‘MCF5282 Signals and Pin Numbers Sorted by Function’ table. • Added errata for “SDRAM Read Cycle’ figure. • Added errata for Chapter 19. PIT1–PIT4 should be PIT0–PIT3.
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• Added DACRn[CBM] field description note. • Added FEC MIB counter memory map errata. • Added “Duplicate Frame Transmission” section to FEC chapter. • Added DMA SAA bit errata. • Added global IACK register space errata. MCF5282 User’s Manual Errata, Rev. 15 Freescale Semiconductor...
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P.O. Box 5405 application in which the failure of the Freescale Semiconductor product could Denver, Colorado 80217 create a situation where personal injury or death may occur. Should Buyer...
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