Freescale Semiconductor MC9S12XHY Series Reference Manual

Quick Links

Download this manual

MC9S12XHY256

Reference Manual

Covers MC9S12XHY Family

Data Sheet: Advance Information

This document contains information on a new product. Speciﬁcations and information here in are subject to change without notice.

S12

Microcontrollers

MC9S12XHY256RMV1

Rev. 1.01

03/2011

freescale.com

Downloaded from

Elcodis.com

electronic components distributor

Table of Contents

Need help?

Do you have a question about the MC9S12XHY Series and is the answer not in the manual?

Questions and answers

Summary of Contents for Freescale Semiconductor MC9S12XHY Series

Page 1 MC9S12XHY256 Reference Manual Covers MC9S12XHY Family Data Sheet: Advance Information This document contains information on a new product. Speciﬁcations and information here in are subject to change without notice. Microcontrollers MC9S12XHY256RMV1 Rev. 1.01 03/2011 freescale.com Downloaded from Elcodis.com electronic components distributor...
Page 2 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices.
Page 3 “Typicals” must be validated for each customer application by customer’s technical experts. Asia/Paciﬁc: Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor H.K. Ltd. Freescale Semiconductor products are not designed, intended, or authorized for use as components...
Page 4 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 5: Table Of Contents
Timer Module (TIM16B8CV2) ........519 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 6: Table Of Contents
Ordering Information..........799 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 7: Table Of Contents
Initialization/Application Information ..........195 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 8: Table Of Contents
10.3 Memory Map and Register Deﬁnition ..........319 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 9: Table Of Contents
15.3 Memory Map and Register Deﬁnition ..........496 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 10: Table Of Contents
20.5 Reset ............... 693 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 11: Table Of Contents
A.9.2 Slave Mode ............756 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 12: Table Of Contents
Ordering Information ............799 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 13: Device Overview Mc9S12Xhy-Family
I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. Features This section describes the key features of the MC9S12XHY family. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 14 Stepper Motor Controller Stepper Stall Detecter LCD Driver 38x4 40x4 38x4 40x4 (FPxBP) Key Wakeup Pins Frequency Modu- lated PLL External osc (4–16 MHz Pierce with loop control) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 15: Module Features
Four Stepper Stall Detector modules (one for each motor) • Up to 25 key wakup inputs Module Features The following sections provide more details of the modules implemented on the MC9S12XHY family. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 16 — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 17 16-bit free-running counter with 8-bit precision prescaler • 1 x 16-bit pulse accumulator 1.3.9 Timer (TIM1) • 8x 16-bit channels for input capture • 8x 16-bit channels for output compare MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 18 — Programmable bit rate up to 1 Mbps • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization • Flexible identiﬁer acceptance ﬁlter programmable as: MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 19 — Wakeup from low power modes on analog comparison > or <= match — Continuous conversion mode — Multiple channel scans • Pins can also be used as digital I/O MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 20 — SCI receive pins — Depending on the package option up to 25 pins on ports R, S, T and AD, conﬁgurable as rising or falling edge sensitive • MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 21 Device Overview MC9S12XHY-Family MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 22: Block Diagram
Motor Driver3 SSD 3 CAN1 RXCAN msCAN 2.0B TXCAN VLCD 5V IO Supply VDDX/VSSX VDDM1/VSSM1 VDDM2/VSSM2 VDDA/VSSA SCI1 Asynchronous Serial IF Figure 1-1. MC9S12XHY-Family 112 LQFP Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 23: Device Memory Map
MC(motor controller) 0x0200–0x021F 0x0220–0x0227 Stepper Stall Detector 0 (SSD0) 0x0228–0x022F Stepper Stall Detector 1 (SSD1) 0x0230–0x0237 Stepper Stall Detector 2 (SSD2) 0x0238–0x023F Stepper Stall Detector 3 (SSD3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 24 A CPU access to any unimplemented space causes an illegal address reset. The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block sizes are listed in Table 1-3. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 25 8K / 8 1. Number of 16K pages addressable via PPAGE register 2. Number of 4K pages addressing the RAM. 3. Number of 1K pages addressing the DFLASH MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 26 8K RAM Resources 0x4000 0x13_FFFF Unpaged 16K FLASH Unimplemented Space 0x8000 16K FLASH window PPAGE 0x3F_FFFF Unimplemented 0xC000 FLASH Unpaged 16K FLASH FLASH_LOW Vectors 0xFFFF FLASH 0x7F_FFFF MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 27: Part Id Assignments
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device. 1.7.1 Device Pinout MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 28 M3COSP /M3C0P /PV5 PT6 /IOC0_6 /KWT6 /FP15 M3SINM /M3C1M /IOC0_7 /IOC1_3 /PV6 PT5 /IOC0_5 /KWT5 /FP14 M3SINP /M3C1P /PV7 PT4 /IOC0_4 /KWT4 /FP13 Figure 1-3. MC9S12XHY-Family 112 LQFP pinout MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 29 M3SINM /M3C1M /IOC0_7 /IOC1_3 /PV6 PT6 /IOC0_6 /KWT6 /FP15 M3SINP /M3C1P /PV7 PT5 /IOC0_5 /KWT5 /FP14 FP0 /PWM0 /PP0 PT4 /IOC0_4 /KWT4 /FP13 Figure 1-4. MC9S12XHY-Family 100LQFP pinout MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 30 VDD/VSS2 VDDF/VSSF I/O Power Pair VDDPLL/VSSPLL VLCD power Sum of power pins OSC pairs XTAL/EXTAL other pins RESET/TEST/BKGD 1/1/1 1/1/1 1. VRH/VRL are sharing with VDDA/VSSA pins MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 31 1. “O” denotes a possible rerouting under software control, “X” denotes as default routing option Table 1-7 provides a pin out summary listing the availability and functionality of individual pins for each package option. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 32 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Dis- Port AD I/O, analog input of PAD05 AN05 VDDA PERAD abled ATD, key wakeup Dis- Port AD I/O, analog input of PAD06 AN06 VDDA...
Page 33 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State VDDM1 VSSM1 IOC0 PERU/P Dis- Port U I/O, Motor1 coil VDDM abled nodes of MC,TIM0 channel PERU/P Dis- Port U I/O, Motor1 coil VDDM abled...
Page 34 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Port V I/O, Motor3 coil IOC1 IOC0 PERV/P Dis- VDDM nodes of MC,TIM0/1 chan- abled PERV/P Dis- Port V I/O, Motor3 coil VDDM abled nodes of MC...
Page 35 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State IOC1_ PERR/P Port R I/O, timer1 Channel, VDDX Down Key wakeup IOC1_ PERR/P Port R I/O, timer1 Channel, VDDX Down Key wakeup...
Page 36 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Port S I/O, SCK of SPI, PERS/P PWM2 VDDX PWM channel2 , key wakeup PERS/P Port S I/O, SS of SPI, SDA PWM3 VDDX of IIC, PWM channel 3...
Page 37 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Port T I/O, LCD Frontplane IOC0_ PERT/P FP15 VDDX Down driver, timer0 channel,key wakeup Port T I/O, LCD Frontplane IOC0_ PERT/P FP16...
Page 38 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Port M I/O, PWM channel5 , IOC0 PERM/P PWM5 VDDX timer0 Channe 3, TXD of SCI1 IOC1 PERM/P Port M I/O, PWM channel6 , PWM6 VDDX...
Page 39 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State PERH/P Port H I/O, LCD Frontplane FP25 VDDX Down driver PERH/P Port H I/O, LCD Frontplane FP26 VDDX Down driver PERR/P...
Page 40 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Port BI/O, LCD Frontplane FP37 VDDX PUCR Down driver Port B I/O, LCD Frontplane FP38 VDDX PUCR Down driver Port B I/O, LCD Frontplane FP39...
Page 41 Table 1-7. Pin-Out Summary Package Internal Pull Function Resistor Power Description Supply Reset Func Func Func Func Func Func CTRL Func. State Dis- Port AD I/O, analog input of PAD01 AN01 VDDA PERAD abled ATD, key wakeup Dis- Port AD I/O, analog input of PAD02 AN02 VDDA...
Page 42 Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Section 1.16, “Oscillator Conﬁguration ). An internal pull-down is enabled during reset. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 43 (during slave mode) MISO for the serial peripheral interface (SPI).It can be conﬁgured as the serial clock pin SCL as IIC module.It can be conﬁgured as PWM channel0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 44 PR[3:2] / IOC1[7:6] / KWR[3:2] — Port R I/O Pins [3:2] PR[3:2] are a general-purpose input or output pins. They can be conﬁgured as timer (TIM1) channel 7-6. They can be conﬁgured as keypad wakeup inputs. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 45 FP[19]. It can be conﬁgured as the master input (during master mode) or slave output pin (during slave mode) MISO for the serial peripheral interface (SPI).It can be conﬁgured as the receive pin RXD of serial communication interface(SCI1). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 46 EMF to calibrate the pointer reset position. The pin interfaces to the coils of motor 1. It can aslo be configured as timer (TIM0) channel 3 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 47 PV[6] is a general-purpose input or output pin. It can be configured as high current PWM output pin which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. The pin MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 48 2. It can be conﬁgured as timer (TIM1) channel 0 or timer (TIM0) channel 4. It can be conﬁgured as the master input (during master mode) or slave output pin (during slave mode) MISO for the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 49 1.8V is derived from the internal voltage regulator. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This voltage is generated by the internal voltage regulator. No static external loading of these pins is permitted MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 50 VDDM[2:1] 5.0 V External power and ground, supply to Port U/V motor drivers VSSM[2:1] VLCD 5.0 V External voltage reference for the LCD driver MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 51: System Clock Description
Figure 1-5. Clock Connections The system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: • The on-chip phase locked loop (PLL) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 52: Modes Of Operation
MODC signal during reset (see Table 1-9). The MODC bit in the MODE register shows the current operating mode and provides limited mode MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 53 BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM ﬁrmware waits for additional serial commands through the BKGD pin. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 54 RESET, XIRQ, IRQ or any other interrupt that is not masked ends system wait mode. 1.9.2.5 Run Mode Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 55: Security
None $FFFE External pin RESET None None $FFFE Illegal Address Reset None None $FFFC Clock monitor reset None PLLCTL(CME,SCME) $FFFA COP watchdog reset None COP rate select MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 56 I bit Vector base + $C6 CRG PLL lock I bit CRGINT(LOCKIE) Vector base + $C4 CRG self-clock mode I bit CRGINT(SCMIE) Reserved Vector base + $C2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 57 Vector base + $82 Reserved Vector base + $80 Low-voltage interrupt (LVI) I bit VREGCTRL (LVIE) Vector base + $7E Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 58 Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module section. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 59: Cop Conﬁguration
NV[2:0] in CR[2:0] in FOPT Register COPCTL Register Table 1-13. Initial WCOP Conﬁguration NV[3] in WCOP in FOPT Register COPCTL Register 1.13 ATD External Trigger Input Connection MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 60: Atd Channel[17] Connection
ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17]. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 61: Oscillator Conﬁguration
Unlike XS family, XCLKS signal is applied in MC9S12XHY family instead of XCLKS in XS family EXTAL Crystal or Ceramic Resonator XTAL SSPLL Figure 1-6. Loop Controlled Pierce Oscillator Connections (XCLKS = 0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 62: Documentation Note
S12XHY will support only 10-bit ATD resolution, although in ATD12B block it still has the 12-bit descriptions. SSD block says one SSD can be conﬁged to control two motors, while in chip level, this feature is not supported. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 63 Conﬁguration, FOPT address is 0x7_FF0E Rev0.12 Nov-16-2010 Daniel Fix typo of Table 1-2./1-23, size of Moudle INT is 16, 0x130~ is 16 update Table 1-1./1-14,all parts has 2x MSCAN and SCI MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 64 Device Overview MC9S12XHY-Family MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 65: Port Integration Module (S12Xhypimv1)
Table 2-62,Figure 2-75 update WOMM[1:0] at Figure 2-34,Figure 2-2, Figure 2-80 update Figure 2-80,reduced drive,Routing,Wire-Or ﬁx Table 2-38, un-hidePMM5:4] routing ﬁx Table 2-95, port name for glitch MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 66: Introduction
This document assumes the availability of all features (112-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary section. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 67: External Signal Description
Table 2-1. Pin Functions and Priorities Pin Function Pin Function Port Pin Name Description & Priority after Reset BKGD MODC MODC input during RESET BKGD BKGD I/O BDM communication pin MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 68 GPIO I/O General purpose PB[7:4] BP[3:0] LCD backplane segment driver output GPIO GPIO I/O General purpose PB[3:0] FP[39:37,28] LCD frontplane segment driver output GPIO I/O General purpose MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 69 I/O Pulse Width Modulator channel 4 GPIO I/O General purpose PP[7:0] FP[7:0] LCD frontplane segment driver output PWM[7:0] I/O Pulse Width Modulator channel 7 - 0 GPIO GPIO I/O General purpose MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 70 I/O TIM0 channel, mappable through software GPIO I/O General purpose PR[0] KWR[0] Key Wakeup RXCAN1 RX of CAN1 IOC0[6] I/O TIM0 channel, mappable through software GPIO I/O General purpose MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 71 IOC0[7:4] I/O Timer0 Channels 7-4 GPIO I/O General purpose PT[3:0] FP[11:8] LCD segment driver output KWT[3:0] Key Wakeup IOC1[7:4] I/O Timer1 Channels 7-4 GPIO I/O General purpose MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 72 Motor control output for motor 0 GPIO I/O General purpose PU[0] M0COSM I/O SSD0 Cosine- Node M0C0M Motor control output for motor 0 IOC0_0 I/O TIM0 channel 0 GPIO I/O General purpose MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 73 IOC1_0 I/O TIM1 channel 0 I/O SCL of IIC, mappable through software PWM4 PWM channel 4, mappable through software MISO I/O MISO of SPI, mappable through software MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 74: Memory Map And Register Deﬁnition
0x001C ECLKCTL—ECLK Control Register 0x80 2.3.10/2-91 0x001D PIM Reserved 0x00 2.3.11/2-91 0x001E IRQCR—IRQ Control Register 0x00 2.3.12/2-92 0x001F PIM Reserved 0x00 2.3.13/2-92 0x0020 Non-PIM address range 0x023F MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 75 2.3.43/2-113 0x025D PPSP—Port P Polarity Select Register 0xFF 2.3.44/2-114 0x025E PTPRRH— Port P Routing Register High 0x00 2.3.45/2-114 0x025F PTPRRL— Port P Routing Register Low 0x00 2.3.46/2-115 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 76 PERR—Port R Pull Device Enable Register 0xFF 2.3.69/2-131 0x0285 PPSR—Port R Polarity Select Register 0xFF 2.3.70/2-132 0x0286 WOMR—Port R Wired-Or Mode Register 0x00 2.3.71/2-132 0x0287 PIM Reserved 0x00 2.3.72/2-133 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 77 Write access not applicable for one or more register bits. Refer to register description Read always returns logic level on pins. Register Bit 7 Bit 0 Name 0x0000 PORTA = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 78 Non-PIM Address Range Address Range 0x001C NECLK DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 ECLKCTL 0x001D Reserved 0x001E IRQE IRQEN XIRQEN IRQCR 0x001F Reserved = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 79 PTIS 0x024A DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 DDRS 0x024B Reserved 0x024C PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PERS = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 80 PTP0 0x0259 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 PTIP 0x025A DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 DDRP 0x025B Reserved = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 81 WOMH 0x0267 PTHRR0 PTHRR 0x0268- 0x026F Reserved 0x0270 PT0AD3 PT0AD2 PT0AD1 PT0AD8 PT0AD 0x0271 PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 PT1AD = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 82 PERR 0x0285 PPSR7 PPSR6 PPSR5 PPSR4 PPSR3 PPSR2 PPSR1 PPSR0 PPSR 0x0286 WOMR7 WOMR6 WOMR5 WOMR4 WOMR3 WOMR2 WOMR1 WOMR0 WOMR 0x0287 Reserved = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 83 PERU1 PERU0 PERU 0x0295 PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 PPSU 0x0296 SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0 SRRU = Unimplemented or Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 84 The conﬁguration bit PS is used for two purposes: 1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 85 NOTE Figures of module routing registers also display the module instance or module channel associated with the related routing bit. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 86 • The LCD segment driver output takes precedence over the IRQ and general purpose I/O function if the related LCD segment is enabled. • The IRQ takes precedence over the general purpose I/O function if the IRQ function is enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 87 Address 0x0002 (PRR) Access: User read/write DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Reset Figure 2-3. Port A Data Direction Register (DDRA) Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 88 Address 0x0003 (PRR) Access: User read/write DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Reset Figure 2-4. Port B Data Direction Register (DDRB) Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 89 = Unimplemented or Reserved Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR) Read:Anytime in single-chip modes. Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 90 0 pull-down device disabled 2.3.9 PIM Reserved Register Address 0x000D (PRR) Access: User read/write Reset = Unimplemented or Reserved Figure 2-7. PIM Reserved Register Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 91 EDIV=00000 DIV16-0,and bus clock>=32MHz, ECLK output maybe cannot work 2.3.11 PIM Reserved Register Address 0x001D (PRR) Access: User read Reset = Unimplemented or Reserved Figure 2-9. PIM Reserved Register MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 92 0 XIRQ pin is disconnected from interrupt logic 2.3.13 PIM Reserved Register This register is reserved for factory testing of the PIM module and is not available in normal operation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 93 FP14 FP13 FP11 FP10 Function Reset Figure 2-12. Port T Data Register (PTT) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 94 PTIT A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 95 PTT or PTIT registers, when changing the DDRT register. 2.3.17 PIM Reserved Register Address 0x0243 Access: User read/write Reset Figure 2-15. PIM Reserved Register MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 96 This bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 A pull-down device is selected 0 A pull-up device is selected MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 97 11 IOC0_7 routed to PT7(reserved) Port T data direction— PTTRR This register controls the routing of IOC0_5. 0 IOC0_5 routed to PT5 1 IOC0_5 routed to PV2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 98 MOSI MISO TXCAN RXCAN Function Reset Figure 2-20. Port S Data Register (PTS) Read: Anytime The data source is depending on the data direction value. Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 99 If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. • The CAN takes precedence over the general purpose I/O function if enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 100 This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 101 Else if PWM0 is routing to PS and PWM0 is enabled it will force as output. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 102 PTS or PTIS registers, when changing the DDRS register. 2.3.25 PIM Reserved Registers Address 0x024B Access: User read/write Reset Figure 2-23. PIM Reserved Register) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 103 0 A falling edge on the associated Port S pin sets the associated ﬂag bit in the PIFS register. A pull-up device is connected to the associated pin, if enabled and if the pin is used as input. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 104 Figure 2-27. Port S Routing Register (PTSRR) Read: Anytime. Write: Anytime. This register configures the re-routing of IIC and SPI on alternative ports. Table 2-23. Module Routing Summary PTSRR Module Related Pins MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 105 Port Integration Module (S12XHYPIMV1) Table 2-23. Module Routing Summary PTSRR Module Related Pins MISO MOSI Reserved 2.3.30 PIM Reserved Register MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 106 • The TIM1 output function takes precedence over the PWM6 and general purpose I/O function if the related channel is enabled. • The PWM6 takes precedence over the general purpose I/O function if enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 107 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-29. Port M Input Register (PTIM) Read: Anytime Write:Never, writes to this register have no effect. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 108 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRT register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 109 This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 110 “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no inﬂuence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 111 • The LCD segment takes precedence over the PWM function and the general purpose I/O function is LCD segment output is enabled • The PWM function takes precedence over the general purpose I/O function if the PWM channel is enabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 112 Port P Data Direction Register (DDRP) Address 0x025A Access: User read/write DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 Reset Figure 2-38. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 113 Port P Pull Device Enable Register (PERP) Address 0x025C Access: User read/write PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Reset Figure 2-40. Port P Pull Device Enable Register (PERP) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 114 Read: Anytime. Address 0x025E Access: User read/write PTPRRH7 PTPRRH6 PTPRRH5 PTPRRH4 PTPRRH3 PTPRRH2 PTPRRH1 PTPRRH0 Reset Figure 2-42. Port P Routing Register High (PTPRRH) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 115 The register decide the PWM[3:0] channel routing on the Port S/P/V The PTPRRH/PTPRRL register configures the re-routing of PWM on alternative ports. Table 2-38. Module Routing Summary PTPRRL Module PTPRRH Related Pins PWM7 PWM6 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 116 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 Function Reset Figure 2-44. Port H Data Register (PTH) Read: Anytime. Write: Anytime. Special priority for SPI & IIC MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 117 • The RXD of SCI1 takes precedence over the SPI and the general purpose I/O function • The MISO of SPI takes precedence over the general purpose I/O function MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 118 Port H Data Direction Register (DDRH) Address 0x0262 Access: User read/write DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 Reset Figure 2-46. Port H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 119 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 120 Port H Polarity Select Register (PPSH) Address 0x0265 Access: User read/write PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 Reset Figure 2-49. Port H Polarity Select Register (PPSH) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 121 “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no inﬂuence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 122 1 SCI1 routed to PM[1:0] 2.3.55 PIM Reserved Register Address 0x0268-0x26F Access: User read Reset = Unimplemented or Reserved Figure 2-52. PIM Reserved Register Read: Always reads 0x00 Write: Unimplemented MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 123 KWAD2 KWAD1 KWAD0 Altern. Function Reset Figure 2-54. Port AD Data Register (PT1AD) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 124 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT1AD registers, when changing the DDR1AD register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 125 DDR1AD register. 2.3.60 PIM Reserved Register Address 0x0274 Access: User read Reset = Unimplemented or Reserved Figure 2-57. PIM Reserved Register Read: Always reads 0x00 Write: Unimplemented MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 126 Port AD Pull Up Enable Register (PER1AD) Address 0x0277 Access: User read/write PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 Reset Figure 2-60. Port AD Pull Up Enable Register (PER1AD) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 127 IOC1_7 IOC1_6 IOC0_7 IOC0_6 Function Reset Figure 2-62. Port R Data Register (PTR) Read: Anytime The data source is depending on the data direction value. Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 128 If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. • The TIM1 output compare function takes precedence over the general purpose I/O function MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 129 This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 130 If TIM1/ are routing to the PR and TIM1 output compare functions are enabled, it will force as output. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 131 Port R Pull Device Enable Register (PERR) Address 0x0284 Access: User read/write PERR7 PERR6 PERR5 PERR4 PERR3 PERR2 PERR1 PERR0 Reset Figure 2-66. Port R Pull Device Enable Register (PERR) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 132 Port R Wired-Or Mode Register (WOMR) Address 0x0286 Access: User read/write WOMR7 WOMR6 WOMR5 WOMR4 WOMR3 WOMR2 WOMR1 WOMR0 Reset Figure 2-68. Port R Wired-Or Mode Register (WOMR) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 133 This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt ﬂag masked). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 134 This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port S. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt ﬂag masked). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 135 This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port AD. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt ﬂag masked). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 136 This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt ﬂag masked). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 137 M1C0P M1C0M M0C1P M0C1M M0C0P M0C0M Function M1SINP M1SINM M1COSP M1COSM M0SINP M0SINM M0COSP M0COSM Reset Figure 2-78. Port U Data Register (PTU) Read: Anytime. Write: Anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 138 This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 139 PIM Reserved Registers Address 0x0293 Access: User read Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-81. PIM Reserved Registers Read: Always reads 0x00 Write: Unimplemented MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 140 0 A pull-up device is connected to the associated Port U pin, if enabled by the associated bit in register PERU and if the port is used as input. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 141 Access: User read PTURR0 PTURR0 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-85. Port U Routing Register (PTURR) Read: Always reads 0x00 Write: Unimplemented MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 142 1 IOC0_2 routed to PM0 Port U Routing Register— PTURR This register controls the routing of IOC0_3 0 IOC0_3 routed to PU6 1 IOC0_3 routed to PM1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 143 • The TIM0 output compare function takes precedence over the TIM1 and the general purpose I/O function. • The TIM1 output compare function takes precedence over the general purpose I/O function if the related channels is enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 144 • The SCK of SPI takes precedence over the PWM channel 6 and the general purpose I/O function • The PWM channel 6 takes precedence over the general purpose I/O function MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 145 Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-87. Port V Input Register (PTIV) Read: Anytime. Write:Never, writes to this register have no effect. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 146 If enabled the Motor driver PWM output or enable the TIM1 channel 2 output compare function, it will force the I/O state to be output. 1 Associated pin is conﬁgured as output. 0 Associated pin is conﬁgured as input. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 147 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTV or PTIV registers, when changing the DDRV register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 148 Port V Polarity Select Register (PPSV) Address 0x029D Access: User read/write PPSV7 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0 Reset Figure 2-91. Port V Polarity Select Register (PPSV) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 149 After wakeup from STOP, it will also need to wait about 300 nanoseconds before slew rate control to be function as setting. When MC function is disabled and IIC/SPI/PWM async shutdown are routing to PV and enabled, the corresponding digital input buffer will be always enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 150: Functional Description
For example selecting a pull-up device: This device does not become active while the port is used as a push-pull output. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 151 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 152 2.4.2.8 Interrupt ﬂag register (PIFx) If the pin is used as an interrupt input this register holds the interrupt ﬂag after a valid pin event. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 153 Port P This port is associated with the PWM. 2.4.3.7 Port R This port is associated with LCD/IIC. 2.4.3.8 Port S This port is associated with SPI/SCI/IIC/PWM/CAN. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 154 Table 2-81). Glitch, ﬁltered out, no interrupt ﬂag set Valid pulse, interrupt ﬂag set uncertain pign pval Figure 2-95. Interrupt Glitch Filter on Port T,S,R, and AD(PPS=0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 155: Initialization Information
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 156 Port Integration Module (S12XHYPIMV1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 157: Memory Mapping Control (S12Xmmcv4)
The MMC module controls the multi-master priority accesses, the selection of internal resources . Internal buses, including internal memories and peripherals, are controlled in this module. The local address space for each master is translated to a global memory space. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 158 Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes Resources are also called targets. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 159 Single chip modes In normal and special single chip mode the internal memory is used. 3.1.5 Block Diagram Figure 3-1 shows a block diagram of the MMC. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 160 It also provides a brief description of their operation. Table 3-2. External Input Signals Associated with the MMC Signal Description Availability MODC Mode input Latched after RESET (active low) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 161: Memory Map And Registers
Reserved 0x0015 PPAGE PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0x0016 RPAGE 0x0017 EPAGE = Unimplemented or Reserved Figure 3-2. MMC Register Summary 3.3.2 Register Descriptions MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 162 Transition done by external pins (MODC) State RESET Transition done by write access to the MODE register State State Figure 3-5. Mode Transition Diagram when MCU is Unsecured MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 163 ;Set GPAGE offset to the value of 0x5000 MOVB #0x14, GPAGE ;Initialize GPAGE register with the value of 0x14 GLDAA ;Load Accu A from the global address 0x14_5000 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 164 ;Load the Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are “direct page aware” and can ;automatically select direct mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 165 1 Visible in the global memory map. 3.3.2.5 Program Page Index Register (PPAGE) Address: 0x0015 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Reset Figure 3-11. Program Page Index Register (PPAGE) Read: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 166 The ﬁxed 16K page from 0xC000-0xFFFF is the page number 0xFF. 3.3.2.6 RAM Page Index Register (RPAGE) Address: 0x0016 Reset Figure 3-13. RAM Page Index Register (RPAGE) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 167 The page 0xFD (reset value) contains unimplemented area in the range not occupied by RAM if RAMSIZE is less than 12KB (Refer to Section 3.4.2.3, “Implemented Memory Map). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 168 The two ﬁxed 4KB pages (0xFE, 0xFF) contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB (Refer to Section 3.4.2.3, “Implemented Memory Map). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 169 Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH EP[7:0] array pages is to be accessed in the Data FLASH Page Window. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 170 Please note that after the MCU enters active BDM mode the BDM ﬁrmware lookup tables and the BDM registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0xFF. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 171 Reset Vectors 0xFFFF 0x7F_4000 16KB FLASH (PPAGE 0xFD) 0x7F_8000 16KB FLASH (PPAGE 0xFE) 0x7F_C000 16KB FLASH (PPAGE 0xFF) 0x7F_FFFF Figure 3-17. Expansion of the Local Address Map MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 172 EPAGE allows accessing up to 256KB of Data Flash in the system by using the eight EPAGE index bits to page 1KB blocks into the Data FLASH page window located in the local CPU memory space from address 0x0800 to address 0x0BFF. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 173 [22:16] in the case of a hardware command or concatenation of the CPU local address and the BDMGPR register [22:16] in the case of a ﬁrmware command (see Figure 3-18). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 174 RAMSIZE is the hexadecimal value of RAM SIZE in Bytes DFLASHSIZE is the hexadecimal value of DFLASH SIZE in Bytes FLASHSIZE is the hexadecimal value of FLASH SIZE in Bytes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 175 Misaligned word access to the last location of any global page (64KB) by any global instruction, is performed by accessing the last byte of the page and the ﬁrst byte of the same page, considering the above mentioned misaligned access cases. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 176 Space 16K FLASH window PPAGE 0x3F_FFFF 0xC000 Unimplemented FLASH Unpaged 16K FLASH Reset Vectors FLASH_LOW 0xFFFF FLASH 0x7F_FFFF Figure 3-19. S12X CPU & BDM Global Address Mapping MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 177 All internal resources are connected to speciﬁc target buses (see Figure 3-20). S12X1 S12X0 Address Decoder & Priority Target Bus Controller XBUS0 Data FLASH PGMFLASH Peripherals Figure 3-20. MMC Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 178: Initialization/Application Information
The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks the PPAGE value and the return address and reﬁlls the queue. Execution resumes with the next instruction after the CALL instruction. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 179 This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 180 Memory Mapping Control (S12XMMCV4) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 181: Interrupt (S12Xintv2)
NOTE The HPRIO register and functionality of the original S12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 182 1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). 2. The IRQ interrupt can only be handled by the CPU MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 183 Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 4.3.2.1, “Interrupt Vector Base Register (IVBR)” for details. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 184 INT_XGPRIO = XGATE Interrupt Priority IVBR = Interrupt Vector Base = Interrupt Processing Level Figure 4-1. XINT Block Diagram External Signal Description The XINT module has no external signals. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 185 Interrupt Request Conﬁguration Data Register 4 (INT_CFDATA4) 0x012D Interrupt Request Conﬁguration Data Register 5 (INT_CFDATA5) 0x012E Interrupt Request Conﬁguration Data Register 6 (INT_CFDATA6) 0x012F Interrupt Request Conﬁguration Data Register 7 (INT_CFDATA7) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 186 0x012C INT_CFDATA4 R RQST PRIOLVL[2:0] 0x012D INT_CFDATA5 R RQST PRIOLVL[2:0] 0x012E INT_CFDATA6 R RQST PRIOLVL[2:0] 0x012F INT_CFDATA7 R RQST PRIOLVL[2:0] = Unimplemented or Reserved Figure 4-2. XINT Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 187 Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 188 (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt conﬁguration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt conﬁguration data register of the vector with the highest address, respectively. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 189 RQST PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-9. Interrupt Request Conﬁguration Data Register 3 (INT_CFDATA3) 1. Please refer to the notes following the PRIOLVL[2:0] description below. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 190 = Unimplemented or Reserved Figure 4-13. Interrupt Request Conﬁguration Data Register 7 (INT_CFDATA7) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 191 The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 192 CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 193 CPU will default to that of the spurious interrupt vector. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 194 2. only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor 3. only implemented if device features a Memory Protection Unit (MPU) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 195 Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 196 Interrupt request channels which are conﬁgured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 197: Background Debug Module (S12Xbdmv2)
Enhanced capability for allowing more ﬂexibility in clock rates • SYNC command to determine communication rate • GO_UNTIL command • Hardware handshake protocol to increase the performance of the serial communication MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 198 Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or EEPROM) other than allowing erasure. For more information please see Section 5.4.1, “Security”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 199 BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 200 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 5-2. BDM Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 201 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). Figure 5-3. BDM Status Register (BDMSTS) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 202 ﬁrst recognized. It will stay set until BDM ﬁrmware is exited by one of the following BDM commands: GO or GO_UNTIL. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 203 Bus clock dependent on oscillator Bus clock dependent on oscillator Alternate clock (refer to the device speciﬁcation to determine the alternate clock source) Bus clock dependent on the PLL MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 204 When entering background debug mode, the BDM CCR HIGH holding register is used to save the high byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be written to modify the CCR value. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 205 Commands”) and in secure mode (see Section 5.4.1, “Security”). Firmware commands can only be executed when the system is not secure and is in active background debug mode (BDM). MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 206 BDM. However, these registers are not readable by user programs. 3. BDM is enabled and active immediately out of special single-chip reset. 4. This method is provided by the S12X_DBG module. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 207 Write to memory with standard BDM ﬁrmware lookup table out of map. 16-bit data in Odd address data on low byte; even address data on high byte. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 208 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are received. The ﬁrmware commands are shown in Table 5-7. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 209 If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 210 ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 211 5. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 5.4.6, “BDM Serial Interface” Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 212 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 213 Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 214 ACK pulse, since the command execution depends upon the CPU bus frequency, which in some cases could be very slow MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 215 Target Host Target BDM Issues the ACK Pulse (out of scale) BDM Executes the BDM Decodes READ_BYTE Command the Command Figure 5-12. Handshake Protocol at Command Level MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 216 When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 217 ACK pulse and the SYNC request pulse. This conﬂict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 218 BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 5.4.3, “BDM Hardware Commands” Section 5.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 219 The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 220 All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 221 The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 222 Background Debug Module (S12XBDMV2) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 223: S12X Debug (S12Xdbgv3) Module
Background Debug Mode Device User Guide, describing the features of the device into which the DBG is integrated WORD 16 bit data entity Data Line 64 bit data entity MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 224 TRIG Immediate software trigger independent of comparators • Four trace modes — Normal: change of ﬂow (COF) PC information is stored (see Section 6.4.5.2.1) for change of ﬂow deﬁnition. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 225 Table 6-3. Mode Dependent Restriction Summary Comparator Breakpoints Tagging Tracing Enable Active Secure Matches Enabled Possible Possible Possible Only SWI Active BDM not possible when not enabled MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 226 DBGBRK reserved COMRV TRIG SSF2 SSF1 SSF0 0x0021 DBGSR 0x0022 DBGTCR reserved TSOURCE TRANGE TRCMOD TALIGN 0x0023 DBGC2 CDCM ABCM Figure 6-2. Quick Reference to S12XDBG Registers MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 227 S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0] MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 228 ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 229 On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-7 MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 230 Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a TALIGN tracing session. See Table 6-11. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 231 Table 6-13. 1–0 A and B Comparator Match Control — These bits determine the A and B comparator match mapping as ABCM[1:0] described in Table 6-14. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 232 The same is true for word reads while the debugger is armed. The POR state is undeﬁned Other resets do not affect the trace buffer contents. . MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 233 There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and deﬁnes the MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 234 Match2 triggers to State3..Other matches have no effect 0101 Match2 triggers to Final State..Other matches have no effect 0110 Match0 triggers to State2..Match1 triggers to State3..Other matches have no effect MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 235 0010 Any match triggers to Final State 0011 Match3 triggers to State1..Other matches have no effect 0100 Match3 triggers to State3..Other matches have no effect MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 236 These bits select the targeted next state whilst in State3, based upon the match event. SC[3:0] Table 6-24. State3 — Sequencer Next State Selection SC[3:0] Description 0000 Any match triggers to state1 0001 Any match triggers to state2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 237 Comparators A and C consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 238 Write: If DBG not armed. See Table 6-26 for visible register encoding. WARNING DBGXCTL[1] is reserved. Setting this bit maps the corresponding comparator to an MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 239 Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not used for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 240 [22:16] to a logic one or logic zero. . 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 241 [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 242 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 243 This section provides a complete functional description of the S12XDBG module. If the part is in secure mode, the S12XDBG module can generate breakpoints but tracing is not possible. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 244 If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 245 To detect an access of ADDR[n+1] through a word access of ADDR[n] the comparator can be configured to ADDR[n], DBGxDL is loaded with the data pattern and DBGxDHM is cleared so only the data[n+1] is compared on accesses of ADDR[n]. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 246 Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 247 This can be avoided by setting the upper or lower range limit to $7FFFFF or $000000 respectively. Interrupt vector fetches do not cause taghits MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 248 If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the ARM bit is cleared due to the hardware disarm. Table 6-39. Trigger Priorities Priority Source Action MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 249 BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 250 S12XDBG module is disarmed and no more data is stored. Using Mid-trigger with tagging, if the tagged instruction is about to MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 251 JMP COF has taken place. #SUB_1 MARK1 ; IRQ interrupt occurs during execution of this MARK2 MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 252 6.4.5.2.4 Pure PC Mode In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes, are stored. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 253 S12XCPU Detail CXINF2 CADRH2 CADRM2 CADRL2 CDATAH2 CDATAL2 CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0 CPU12X Other Modes CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2 MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 254 Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing CPU12X activity in Detail Mode. 0 Word Access 1 Byte Access MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 255 In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 256 6-43). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 257 On returning from BDM, the SWI from user code gets executed. Table 6-44. Breakpoint Mapping Summary DBGBRK BDM Bit S12X Breakpoint (DBGC1[3]) (DBGC1[4]) Enabled Active Mapping No Breakpoint Breakpoint to SWI No Breakpoint MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 258 SWI routine, if conﬁgured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program ﬂow past the tagged instruction. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 259: S12Xe Clocks And Reset Generator (S12Xecrgv2)
System Reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 260 It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 7.1.3 Block Diagram Figure 7-1 shows a block diagram of the S12XECRG. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 261: Signal Description
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 262 Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 263 (no locking and/or insufﬁcient stability). Table 7-2. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz 48MHz < f <= 80MHz Reserved 80MHz < f <= 120MHz MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 264 The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the ﬁnal divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f (divide by one). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 265 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 7-6. S12XECRG Flags Register (CRGFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 266 S12XECRG Interrupt Enable Register (CRGINT) This register enables S12XECRG interrupt requests. Module Base + 0x0004 RTIE LOCKIE SCMIE Reset = Unimplemented or Reserved Figure 7-7. S12XECRG Interrupt Enable Register (CRGINT) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 267 PSTP PLLWAI RTIWAI COPWAI Reset = Unimplemented or Reserved Figure 7-8. S12XECRG Clock Select Register (CLKSEL) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 268 7.3.2.7 S12XECRG IPLL Control Register (PLLCTL) This register controls the IPLL functionality. Module Base + 0x0006 PLLON FSTWKP SCME Reset Figure 7-9. S12XECRG IPLL Control Register (PLLCTL) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 269 0 Detection of crystal clock failure causes clock monitor reset (see Section 7.5.1.1, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 7.4.2.2, “Self Clock Mode”). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 270 RTICTL register. The source clock for the RTI is OSCCLK. Table 7-10. RTI Frequency Divide Rates for RTDEC = 0 RTR[6:4] = RTR[3:0] (OFF) 0000 (÷1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 271 40x10 80x10 200x10 400x10 800x10 0011 (÷4) 5x10 10x10 25x10 50x10 100x10 250x10 500x10 1x10 0100 (÷5) 6x10 12x10 30x10 60x10 120x10 300x10 600x10 1.2x10 0101 (÷6) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 272 – Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 273 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in emulation or special modes Table 7-13. COP Watchdog Rates OSCCLK Cycles to Timeout COP disabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 274 S12XECRG’s functionality. Module Base + 0x000A Reset = Unimplemented or Reserved Figure 7-13. Reserved Register (CTCTL) Read: Always read $00 except in special modes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 275 WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the ﬁrst 75% of the selected period will cause a COP reset. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 276 The following rules help to achieve optimum stability and shortest lock time: • Use lowest possible f ratio (SYNDIV value). • Use highest possible REFCLK frequency f MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 277 VCO frequency is out of a certain tolerance, ∆ • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 278 PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 279 CHECK WINDOW 49999 50000 PLLCLK 4096 OSCCLK 4095 OSC OK Figure 7-17. Check Window Example 6. IPLL is running at self clock mode frequency f MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 280 IPLL (f ) and an active VREG during Pseudo Stop Mode. 7. A Clock Monitor Reset will always set the SCME bit to logical’1’. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 281 OSCCLK to be the system clock and return to normal mode. See Section 7.4.1.4, “Clock Quality Checker” for more information on entering and leaving Self Clock Mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 282 S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the IPLL. There are two ways to restart the MCU from Wait Mode: 1. Any reset 2. Any interrupt MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 283 PLLCLK. NOTE In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature the clock monitor and the oscillator are disabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 284: Resets
Table 7-16. Reset Summary Reset Source Local Enable Power on Reset None Low Voltage Reset None External Reset None Illegal Address Reset None Clock Monitor Reset PLLCTL (CME=1, SCME=0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 285 MCU. If this requirement is not adhered to the reset source will always be recognized as “External Reset” even if the reset was initially caused by an other reset source. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 286 MCU has reached a certain level and asserts power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 287: Interrupts
Table 7-18. S12XECRG Interrupt Vectors Interrupt Source Local Enable Mask Real time interrupt I bit CRGINT (RTIE) LOCK interrupt I bit CRGINT (LOCKIE) SCM interrupt I bit CRGINT (SCMIE) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 288 SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt ﬂag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 289: Pierce Oscillator (S12Xosclcpv2)
2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor The oscillator mode selection is described in the Device Overview section, subsection Oscillator Conﬁguration. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 290 EXTAL is the external clock input or the input to the crystal oscillator ampliﬁer. XTAL is the output of the crystal oscillator ampliﬁer. The MCU internal system clock is derived MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 291 Figure 8-3. Full Swing Pierce Oscillator Connections (FSP mode selected) CMOS Compatible EXTAL External Oscillator Level) DDPLL XTAL Not Connected Figure 8-4. External Clock Connections (FSP mode selected) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 292 XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 293 Pierce Oscillator (S12XOSCLCPV2) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 294 Pierce Oscillator (S12XOSCLCPV2) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 295 Pierce Oscillator (S12XOSCLCPV2) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 296 Pierce Oscillator (S12XOSCLCPV2) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 297: Voltage Regulator (S12Vregl3V3V1)
Only the POR is available in this mode, LVD, LVR and HTD are disabled. The API is available. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 298 VREG_3V3 by means of a block diagram. The regulator core REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output voltages. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 299 Bus Clock LVD: Low Voltage Detect REG: Regulator Core LVR: Low Voltage Reset CTRL: Regulator Control POR: Power-on Reset API: Auto. Periodical Interrupt HTD: High Temperature Detect MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 300 Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 301 If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within it’s memory slice. See device level speciﬁcation for details. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 302 APIR11 APIR10 APIR9 APIR8 VREGAPIR 0x02F5 APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 Reserved 0x02F6 0x02F7 VREGHTTR HTOEN HTTR3 HTTR2 HTTR1 HTTR0 Table 9-3. Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 303 If enabled (HTIE=1), HTIF causes an interrupt request. 0 No change in HTDS bit. 1 HTDS bit has changed. Note: On entering the reduced power mode the HTIF is not cleared by the VREG. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 304 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 305 Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API timeout has not yet occurred. 1 API timeout has occurred. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 306 Decreases period less than APITR[5] increased it APITR[3] Decreases period less than APITR[4] APITR[2] Decreases period less than APITR[3] APITR[1] Decreases period less than APITR[2] APITR[0] Decreases period less than APITR[1] MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 307 Autonomous Periodical Interrupt Rate Bits — These bits deﬁne the timeout period of the API. See Table 9-10 APIR[15:0] for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL register. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 308 The period can be calculated as follows depending of APICLK: Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 309 Trimming Effect HTTR[3] Increases V twice of HTTR[2] HTTR[2] Increases V twice of HTTR[1] HTTR[1] Increases V twice of HTTR[0] HTTR[0] Increases V (to compensate Temperature Offset) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 310 Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below it’s corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 311 The ﬁrst period after enabling the counter by APIFE might be reduced by API start up delay t . The API internal RC oscillator clock is not available sdel if VREG_3V3 is in Shutdown Mode. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 312 LVIE = 1; available only in Full Performance Mode HTIE=1; High Temperature Interrupt (HTI) available only in Full Performance Mode Autonomous periodical interrupt (API) APIE = 1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 313 As soon as the conﬁgured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 314 Voltage Regulator (S12VREGL3V3V1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 315: Analog-To-Digital Converter (Adc12B12Cv1)
Left/right justiﬁed result data. • External trigger control. • Sequence complete interrupt. • Analog input multiplexer for 8 analog input channels. • Special conversions for V , (V )/2. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 316 The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity. • Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 317 In Freeze Mode the ADC12B12C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 318 Approximation ATD 7 ATD 8 Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN11 AN10 Sample & Hold Comparator Analog Figure 10-1. ADC12B12C Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 319 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 10-2. ADC12B12C Register Summary (Sheet 1 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 320 Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x0022 ATDDR9 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” = Unimplemented or Reserved Figure 10-2. ADC12B12C Register Summary (Sheet 2 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 321 0x0026 ATDDR11 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Unimple- 0x0028 - 0x002F mented = Unimplemented or Reserved Figure 10-2. ADC12B12C Register Summary (Sheet 3 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 322 Table 10-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN11 AN11 AN11 AN11 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 323 The coding is summarized in Table 10-5. Table 10-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data 12-bit data Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 324 Module Base + 0x0002 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 10-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 325 Interrupt will be requested whenever any of the respective CCF ﬂags is set. Table 10-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 326 10-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 327 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 Table 10-10. Conversion Sequence Length Coding Number of Conversions per Sequence MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 328 Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK Table 10-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 329 If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means external trigger always starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 330 Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN7 to AN0. Table 10-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN11 AN11 AN11 AN11 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 331 Analog-to-Digital Converter (ADC12B12CV1) Block Description Table 10-15. Analog Input Channel Select Coding Analog Input Channel Reserved SPECIAL17 Reserved ) / 2 Reserved Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 332 C) Write to ATDCTL5 (a new conversion sequence is started) 0 No over run has occurred 1 Overrun condition exists (result register has been written while associated CCFx ﬂag was still set) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 333 CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 334 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 335 0 If result of conversion n is lower or same than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 336 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi1 1 Bit 0 Reset = Unimplemented or Reserved Figure 10-15. Right justiﬁed ATD conversion result register (ATDDRn) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 337 Bit[11:4] = result, Bit[3:0]=0000 8-bit data Bit[7:0] = result, Bit[11:8]=0000 10-bit data Bit[11:2] = result, Bit[1:0]=00 10-bit data Bit[9:0] = result, Bit[11:10]=00 12-bit data Bit[11:0] = result MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 338 ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 11, conﬁgurable in ATDCTL1) is programmable to MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 339 At reset the ADC12B12C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 10.3.2, “Register Descriptions”) which details the registers and their bit-ﬁeld. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 340 Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 10.3.2, “Register Descriptions” for further details. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 341: Freescale's Scalable Controller Area Network (S12Mscanv3)
EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed application software. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 342 Transmit Interrupt Req. Message Receive Interrupt Req. Control Filtering Errors Interrupt Req. Status Buffering Wake-Up Interrupt Req. Conﬁguration Registers Wake-Up Low Pass Filter Figure 11-1. MSCAN Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 343 For a description of the speciﬁc MSCAN modes and the module operation related to the system operating modes refer to Section 11.4.4, “Modes of Operation”. 8. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 344 CAN bus and has current protection against defective CAN or defective stations. CAN node 2 CAN node n CAN node 1 CAN Controller (MSCAN) TXCAN RXCAN Transceiver CANH CANL CAN Bus Figure 11-2. CAN System MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 345 MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 346 IDAM0 CANIDAC 0x000C Reserved 0x000D BOHOLD CANMISC 0x000E R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CANRXERR = Unimplemented or Reserved Figure 11-3. MSCAN Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 347 The CANCTL0 register provides various control bits of the MSCAN module as described below. Module Base + 0x0000 Access: User read/write RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Reset: = Unimplemented Figure 11-4. MSCAN Control Register 0 (CANCTL0) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 348 0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN 1 Wake-up enabled — The MSCAN is able to restart MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 349 10. RSTAT1 and RSTAT0 are not affected by initialization mode. 11.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 350 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 351 11-7). Table 11-6. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 352 Figure 11-44). Time segment 1 (TSEG1) values are programmable as shown in Table 11-10. 1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 353 Every ﬂag has an associated interrupt enable bit in the CANRIER register. Module Base + 0x0004 Access: User read/write RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF Reset: = Unimplemented Figure 11-8. MSCAN Receiver Flag Register (CANRFLG) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 354 TxWRN: 96 < transmit error counter ≤ 127 TxERR: 127 < transmit error counter ≤ 255 Bus-Off: transmit error counter > 255 9. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 355 (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 356 Section 11.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 11.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 357 This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags. Module Base + 0x0007 Access: User read/write TXEIE2 TXEIE1 TXEIE0 Reset: = Unimplemented Figure 11-11. MSCAN Transmitter Interrupt Enable Register (CANTIER) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 358 The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE ﬂag is set. 0 No abort request 1 Abort request pending MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 359 Figure 11-14. MSCAN Transmit Buffer Selection Register (CANTBSEL) 1. Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 360 Figure 11-15. MSCAN Identiﬁer Acceptance Control Register (CANIDAC) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 361 FIFO the indicators are updated as well. 11.3.2.13 MSCAN Reserved Register This register is reserved for factory testing of the MSCAN module and is not available in normal system operating modes. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 362 1 Module is bus-off and holds this state until user request 11.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reﬂects the status of the MSCAN receive error counter. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 363 For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 364 Access: User read/write Reset Figure 11-21. MSCAN Identiﬁer Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 365 1 Ignore corresponding acceptance code register bit Module Base + 0x001C to Module Base + 0x001F Access: User read/write Reset Figure 11-23. MSCAN Identiﬁer Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 366 TIME bit is set (see Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 367 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 10. Exception: The transmit buffer priority registers are 0 out of reset. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 368 ID12 ID11 ID10 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLC3 DLC2 DLC1 DLC0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 369 The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits: ID[10:0], RTR, and IDE. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 370 ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 371 In the case of a transmit buffer, this ﬂag deﬁnes the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 372 In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send. 0 Standard format (11 bit) 1 Extended format (29 bit) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 373 Module Base + 0x00X4 to Module Base + 0x00XB Reset: Figure 11-34. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping Table 11-33. DSR0–DSR7 Register Field Descriptions Field Description Data bits 7-0 DB[7:0] MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 374 The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately before the SOF (start of frame) is sent. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 375 Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 376 Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 377 CAN Receive / Transmit Engine Memory Mapped I/O MSCAN CPU bus Receiver TXE0 PRIO TXE1 CPU bus MSCAN PRIO TXE2 Transmitter PRIO Figure 11-39. User Model for Message Buffer Organization MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 378 Section 11.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 379 MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF ﬂag, and 11. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 380 Although this mode can be used for standard identiﬁers, it is recommended to use the four or eight identiﬁer acceptance ﬁlters. 12. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 381 IDR1 ID10 IDR2 ID10 IDR3 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 11-40. 32-bit Maskable Identiﬁer Acceptance Filter MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 382 Standard Identiﬁer CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 11-41. 16-bit Maskable Identiﬁer Acceptance Filters MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 383 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 11-42. 8-bit Maskable Identiﬁer Acceptance Filters MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 384 If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 385 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 11-44. Segments within the Bit Time MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 386 Modes of Operation 11.4.4.1 Normal System Operating Modes The MSCAN module behaves as described within this speciﬁcation in all normal system operating modes. Write restrictions exist for some registers. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 387 CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message ﬁlters. See Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 388 Table 11-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 389 This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 11.4.4.5, “MSCAN Initialization Mode”. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 390 It is possible to access the transmit buffers and to clear the associated TXE ﬂags. No message abort takes place while in sleep mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 391 This causes some ﬁxed delay before the module enters normal mode again. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 392 At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx ﬂag of the empty message buffer is set. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 393 For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt ﬂags. These instructions may cause accidental clearing of interrupt ﬂags which are set after entering the current interrupt service routine. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 394 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 395: Inter-Integrated Circuit (Iicv3)
Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identiﬁcation interrupt • Start and stop signal generation/detection • Repeated start signal generation MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 396 Inter-Integrated Circuit (IICV3) Block Description • Acknowledge bit generation/detection • Bus busy detection • General Call Address detection • Compliant to ten-bit address MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 397 The block diagram of the IIC module is shown in Figure 12-1. Start Stop Registers Arbitration Control Interrupt In/Out Data Clock Shift Control bus_clock Register Address Compare Figure 12-1. IIC Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 398 IBSWAI IBCR RSTA 0x0003 IAAS RXAK IBAL IBIF IBSR 0x0004 IBDR 0x0005 GCEN ADTYPE ADR10 ADR9 ADR8 IBCR2 = Unimplemented or Reserved Figure 12-2. IIC Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 399 — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown Table 12-4. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 400 SCL to SDA changing, the SDA hold time. IBC7–6 deﬁnes the multiplier factor MUL. The values of MUL are shown in the Table 12-6. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 401 SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Table 12-7. IIC Divider and Hold Values (Sheet 1 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) MUL=1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 402 SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 20/22 22/24 24/26 26/28 28/30 30/32 34/36 40/42 28/32 32/36 36/40 40/44 44/48 48/52 56/60 68/72 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 403 (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MUL=2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 404 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 1026 3068 3074 7680 1026 3836 3842 MUL=4 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 405 1280 1536 1920 1280 1536 1792 2048 1016 1028 2304 1144 1156 2560 1272 1284 3072 1528 1540 3840 1912 1924 2560 1272 1284 3072 1528 1540 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 406 Module Base + 0x0002 IBEN IBIE MS/SL Tx/Rx TXAK IBSWAI RSTA Reset = Unimplemented or Reserved Figure 12-6. IIC Bus Control Register (IBCR) Read and write anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 407 IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 408 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 409 In master transmit mode, the ﬁrst byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 410 Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described brieﬂy in the following sections and illustrated in Figure 12-10. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 411 (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. START Condition STOP Condition Figure 12-11. Start and Stop Conditions MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 412 SCL at logical 1 (see Figure 12-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 413 ﬁrst device to complete its high period pulls the SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 12-12. IIC-Bus Clock Synchronization MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 414 12-15, the ﬁrst two bytes are the similar to Figure 12-14. After the repeated START(Sr),the ﬁrst slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 415 Section 12.3, “Memory Map and Register Deﬁnition,” which details the registers and their bit-ﬁelds. 12.6 Interrupts IICV3 uses only one interrupt vector. Table 12-11. Interrupt Summary Interrupt Offset Vector Priority Source Description MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 416: Application Information
The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 417 STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 418 A dummy read then releases the SCL line so that the master can generate a STOP signal. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 419 When considering these cases, the slave service routine should test the IBAL ﬁrst and the software should clear the IBAL bit if it is set. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 420 Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 12-16. Flow-Chart of Typical IIC Interrupt Routine MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 421 Inter-Integrated Circuit (IICV3) Block Description Caution:When IIC is conﬁgured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 422 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 423: Pulse-Width Modulator (S12Pwm8B8Cv1)
There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 424 This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature. 13.2.2 PWM6 — PWM Channel 6 This pin serves as waveform output of PWM channel 6. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 425 Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. . MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 426 0x0008 Bit 7 Bit 0 PWMSCLA 0x0009 Bit 7 Bit 0 PWMSCLB 0x000A PWMSCNTA = Unimplemented or Reserved Figure 13-2. PWM Register Summary (Sheet 1 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 427 Bit 0 PWMPER3 0x0018 Bit 7 Bit 0 PWMPER4 0x0019 Bit 7 Bit 0 PWMPER5 = Unimplemented or Reserved Figure 13-2. PWM Register Summary (Sheet 2 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 428 PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 429 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 430 13.3.2.3 PWM Clock Select Register (PWMCLK) Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 431 1 Clock SA is the clock source for PWM channel 0. 13.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK) This register selects the prescale clock source for clocks A and B independently. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 432 Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 Bus clock / 128 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 433 When channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 434 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 435 A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 436 Write: Anytime (causes the scale counter to load the PWMSCLB value). 13.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 437 Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7 Bit 7 Bit 0 Reset Figure 13-14. PWM Channel Counter Registers (PWMCNTx) Read: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 438 Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7 Bit 7 Bit 0 Reset Figure 13-15. PWM Channel Period Registers (PWMPERx) Read: Anytime Write: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 439 Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7 Bit 7 Bit 0 Reset Figure 13-16. PWM Channel Duty Registers (PWMDTYx) Read: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 440 All the other bits in this register are meaningful only if PWM7ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 441 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 442 PCLK5 PWMSCLB DIV 2 Clock to PWM Ch 6 PCLK6 Clock to PWM Ch 7 PCLK7 Prescale Scale Clock Select Figure 13-18. PWM Clock Select Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 443 PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 444 PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 13.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 445 A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 13-19 and described in Section 13.4.2.5, “Left Aligned Outputs” Section 13.4.2.6, “Center Aligned Outputs”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 446 Section 13.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 447 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 13-21. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 448 PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx PWMPERx PWMPERx Period = PWMPERx*2 Figure 13-22. PWM Center Aligned Output Waveform MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 449 — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 450 8-bit channel as also shown in Figure 13-24. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 451 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 452 • The 8-bit up/down counter is conﬁgured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 453 A description of the registers involved and affected due to this interrupt is explained in Section 13.3.2.15, “PWM Shutdown Register (PWMSDN)”. The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 454 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 455: Serial Communication Interface (S12Sciv5)
LIN: Local Interconnect Network LSB: Least Signiﬁcant Bit MSB: Most Signiﬁcant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 456 The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 457 Data Format Control Generator Transmit TDRE Interrupt Transmit Control 1/16 Generation Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 14-1. SCI Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 458 The total address for each register is the sum of the base address for the SCI module and the address offset for each register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 459 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 14-2. SCI Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 460 Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 461 Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the WAKE most signiﬁcant bit position of a received data character or an idle condition on the RXD pin. 0 Idle line wakeup 1 Address mark wakeup MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 462 Table 14-5. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 463 If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 464 Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt BKDIE requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 465 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 14-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 14-19) Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 466 SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 467 0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 468 Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 469 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 470 In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write ﬁrst to SCI data register high (SCIDRH), then SCIDRL. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 471 BKDIE SCI Data BKDFE Register LIN Transmit BERRIF Collision SCTXD Detect BERRIE R16XCLK BERRM[1:0] Infrared Transmit Ir_TXD Encoder R32XCLK TNP[1:0] IREN Figure 14-14. Detailed SCI Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 472 LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 473 A frame with nine data bits has a total of 11 bits. Table 14-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 474 Baud Rate 609,756.1 38,109.8 38,400 308,642.0 19,290.1 19,200 153,374.2 9585.9 9,600 76,687.1 4792.9 4,800 38,402.5 2400.2 2,400 1302 19,201.2 1200.1 1,200 2604 9600.6 600.0 5208 4800.0 300.0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 475 TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 476 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 477 • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 478 TDRE ﬂag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 479 The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ﬂag may be set incorrectly. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 480 After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 481 RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 482 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-19 summarizes the results of the stop bit samples. Table 14-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 483 RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 14-23. Start Bit Search Example 2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 484 ﬂag. Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 14-25. Start Bit Search Example 4 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 485 ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 486 The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 487 The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 488 SCI. The SCI uses the TXD pin for both receiving and transmitting. Transmitter Receiver Figure 14-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 489 Reset Initialization Section 14.3.2, “Register Descriptions”. 14.5.2 Modes of Operation 14.5.2.1 Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 14.4.5.2, “Character Transmission”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 490 Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 491 IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 492 The SCI interrupt request can be used to bring the CPU out of wait mode. 14.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 493: Serial Peripheral Interface (S12Spiv5)
15.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. • Run mode This is the basic mode of operation. • Wait mode MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 494 SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 495 This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data when it is conﬁgured as master. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 496 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved 0x0007 Reserved = Unimplemented or Reserved Figure 15-2. SPI Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 497 SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 498 BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 15-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 499 MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 500 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 501 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s 223.21 kbit/s 111.61 kbit/s 55.80 kbit/s MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 502 (SPICR2)”. The ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 503 Data in SPIDRH is undeﬁned in this case. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 504 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 15-10). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 505 SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 506 SPI is in idle state. 2. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 507 Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 508 BAUD RATE GENERATOR Figure 15-11. Master/Slave Transfer Block Diagram 3. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 509 SPI. 4. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 510 Figure 15-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 511 A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 5. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 512 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 15-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 513 (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 15-3. BaudRateDivisor = (SPPR + 1) • 2 (SPR + 1) Eqn. 15-3 MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 514 MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 515 In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 516 SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 517 This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing process which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 518 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 519: Timer Module (Tim16B8Cv2)
- in TCRE bit description part,add Note - Add Figure 16-31 16.4.3/16-543 16.1 Introduction The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable prescaler. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 520 Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 (0x0006) is cleared to 0. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 521 Input capture IOC6 Output compare PA overflow Channel 7 interrupt 16-bit Input capture IOC7 Pulse accumulator Output compare PA input interrupt Figure 16-1. TIM16B8CV2 Block Diagram MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 522 Divide by 64 M clock Figure 16-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 16-3. Interrupt Flag Setting MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 523 This pin serves as input capture or output compare for channel 3. 16.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin This pin serves as input capture or output compare for channel 2. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 524 TCNT10 TCNT9 TCNT8 TCNTH 0x0005 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 TCNTL = Unimplemented or Reserved Figure 16-5. TIM16B8CV2 Register Summary (Sheet 1 of 3) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 525 PACNT8 PACNTH 0x0023 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 PACNTL 0x0024–0x002B Reserved = Unimplemented or Reserved Figure 16-5. TIM16B8CV2 Register Summary (Sheet 2 of 3) MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 526 1 The corresponding channel acts as an output compare. 16.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset Figure 16-7. Timer Compare Force Register (CFORC) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 527 Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to be transferred from the output compare 7 data register to the timer port. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 528 A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 529 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 530 When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 531 Table 16-9. Compare Result Output Action Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 532 Figure 16-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset Figure 16-17. Timer Control Register 4 (TCTL4) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 533 TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set, the corresponding ﬂag is enabled to cause a interrupt. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 534 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 535 Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 536 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 537 Pulse Accumulator Overﬂow Interrupt Enable PAOVI 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 538 When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the ﬂags in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while clearing these bits. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 539 Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock ﬁrst. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 540 Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 16-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 541 Functional Description This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to the detailed timer block diagram in Figure 16-30 as necessary. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 542 The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 543 When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 544 The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator overﬂow interrupt enable bit, PAOVI, enables the PAOVF ﬂag to generate interrupt requests. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 545 — Timer Overﬂow Timer Overﬂow interrupt Chip Dependent. The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. MC9S12XHY-Family Reference Manual Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 546 Timer Overﬂow Interrupt (TOF) This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced by the system controller. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 547: Liquid Crystal Display (Lcd40F4Bv2)
Voltage Generator – Based on voltage applied to VLCD, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 548 This is a high level description only, detailed descriptions of operating modes are contained in Section 17.4.2, “Operation in Wait Mode”, and Section 17.4.3, “Operation in Stop Mode”. 17.1.3 Block Diagram Figure 17-1 is a block diagram of the LCD40F4BV2 module. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 549 Liquid Crystal Display (LCD40F4BV2) Block Description Internal Address/Data/Clocks IRCCLK Timing Prescaler Control 20 bytes Logic LCD Clock Frontplane Voltage Backplane Drivers Generator Drivers BP[3:0] FP[39:0] VLCD Figure 17-1. LCD40F4BV2 Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 550 The total address for each register is the sum of the base address for the LCD40F4BV2 module and the address offset for each register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 551 LCDRAM (Location 15) Read/Write 0x0018 LCDRAM (Location 16) Read/Write 0x0019 LCDRAM (Location 17) Read/Write 0x001A LCDRAM (Location 18) Read/Write 0x001B LCDRAM (Location 19) Read/Write 0x001C- Unimplemented 0x001F MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 552 Table 17-9. LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD40F4BV2 driver DUTY[1:0] system, as shown in Table 17-9. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 553 LCD Run in Pseudo Stop Mode This bit controls the LCD operation while in pseudo stop mode. LCDRPSTP 0 Stop LCD32F4B driver system when in pseudo stop mode. 1 LCD operates normally in pseudo stop mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 554 Figure 17-8. LCD Frontplane Enable Register 4 (FPENR4) These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1. Read: anytime Write: anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 555 FP14BP3 FP14BP2 FP14BP1 FP14BP0 LCDRAM Reset 0x0010 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 LCDRAM Reset I = Value is indeterminate Figure 17-9. LCD RAM (LCDRAM) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 556 Reset 0x001B FP39BP3 FP39BP2 FP39BP1 FP39BP0 FP38BP3 FP38BP2 FP38BP1 FP38BP0 LCDRAM Reset I = Value is indeterminate Figure 17-9. LCD RAM (LCDRAM) (continued) Read: anytime Write: anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 557 1/4 Duty 1024 IRCCLK = 0.5 2048 2048 IRCCLK = 1.0 4096 4096 IRCCLK = 2.0 8192 8192 IRCCLK = 4.0 16384 16384 IRCCLK = 8.0 32768 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 558 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) • 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) • 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 559 As a result, after exiting from stop mode, the LCD40F4BV2 driver system clocks will run (if LCDEN = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 560 Liquid Crystal Display (LCD40F4BV2) Block Description 17.4.4 LCD Waveform Examples Figure 17-10 through Figure 17-14 show the timing examples of the LCD output waveforms for the available modes of operation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 561 1 Frame VLCD VSSX VLCD FPx (xxx0) VSSX VLCD FPy (xxx1) VSSX +VLCD BP0-FPx (OFF) -VLCD +VLCD BP0-FPy (ON) -VLCD Figure 17-10. 1/1 Duty and 1/1 Bias MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 562 +VLCD +VLCD × 1/2 BP0-FPy (OFF) -VLCD × 1/2 -VLCD +VLCD +VLCD × 1/2 BP0-FPz (ON) -VLCD × 1/2 -VLCD Figure 17-11. 1/2 Duty and 1/2 Bias MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 563 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP2 and BP3 are not used, a maximum of 80 segments are displayed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 564 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 BP0-FPz (ON) -VLCD × 1/3 -VLCD × 2/3 -VLCD Figure 17-12. 1/2 Duty and 1/3 Bias MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 565 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 BP1-FPx (ON) -VLCD × 1/3 -VLCD × 2/3 -VLCD Figure 17-13. 1/3 Duty and 1/3 Bias MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 566 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 BP1-FPx (OFF) -VLCD × 1/3 -VLCD × 2/3 -VLCD Figure 17-14. 1/4 Duty and 1/3 Bias MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 567 Section 17.3, “Memory Map and Register Definition”. The behavior of the LCD40F4BV2 system during reset is described in Section 17.4.1, “LCD Driver Description”. 17.6 Interrupts This module does not generate any interrupts. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 568 Liquid Crystal Display (LCD40F4BV2) Block Description MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 569: Kbyte Flash Module (S12Xftmr256K1V1)
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Preliminary Downloaded from Elcodis.com...
Page 570 Fast sector erase and word program operation • Protection scheme to prevent accidental program or erase of D-Flash memory • Ability to program up to four words in a burst sequence MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Preliminary Downloaded from Elcodis.com electronic components distributor...
Page 571 127 Security Oscillator Clock (XTAL) Clock Divider FCLK Memory Controller D-Flash 4Kx22 Scratch RAM sector 0 384x16 sector 1 sector 31 Figure 18-1. FTMR256K1 Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 572 Section 18.3.1.9, “P-Flash Protection Register (FPROT)” D-Flash Protection byte 0x7F_FF0D Refer to Section 18.3.1.10, “D-Flash Protection Register (DFPROT)” Flash Nonvolatile byte 0x7F_FF0E Refer to Section 18.3.1.15, “Flash Option Register (FOPT)” MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 573 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 574 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 Flash Conﬁguration Field P-Flash END = 0x7F_FFFF 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 18-2. P-Flash Memory Map MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 575 CAUTION Writes to any Flash register must be avoided while a Flash command is active (CCIF=0) to prevent corruption of Flash register contents and Memory Controller behavior. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 576 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV0 0x000D FRSV1 Figure 18-3. FTMR256K1 Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 577 = Unimplemented or Reserved Figure 18-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 578 The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 579 30.45 31.50 0x1D 31.50 32.55 0x1E 32.55 33.60 0x1F FDIV shown generates an FCLK frequency of >0.8 MHz FDIV shown generates an FCLK frequency of 1.05 MHz MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 580 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. Table 18-8. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 581 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 18.3.1.14, “Flash ECC Error Results Register (FECCR),” for more details. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 582 SFDIE interrupt enable in the FERCNFG register is set (see Section 18.3.1.6) 18.3.1.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 583 CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 584 Reset = Unimplemented or Reserved Figure 18-11. Flash Error Status Register (FERSTAT) All ﬂags in the FERSTAT register are readable and only writable to clear the ﬂag. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 585 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 586 Table 18-18. Table 18-17. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x7F_F800–0x7F_FFFF 2 Kbytes 0x7F_F000–0x7F_FFFF 4 Kbytes 0x7F_E000–0x7F_FFFF 8 Kbytes 0x7F_C000–0x7F_FFFF 16 Kbytes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 587 The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 588 Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 18-13. P-Flash Protection Scenarios MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 589 P-Flash sector containing the D-Flash protection byte must be unprotected, then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 590 0x10_0000 – 0x10_11FF 4608 bytes 1_0010 0x10_0000 – 0x10_12FF 4864 bytes 1_0011 0x10_0000 – 0x10_13FF 5120 bytes 1_0100 0x10_0000 – 0x10_14FF 5376 bytes 1_0101 0x10_0000 – 0x10_15FF 5632 bytes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 591 CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 592 Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 18-17. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 593 Offset Module Base + 0x000F ECCR[7:0] Reset = Unimplemented or Reserved Figure 18-20. Flash ECC Error Results Low Register (FECCRLO) All FECCR bits are readable but not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 594 Offset Module Base + 0x0010 NV[7:0] Reset = Unimplemented or Reserved Figure 18-21. Flash Option Register (FOPT) All bits in the FOPT register are readable but are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 595 Figure 18-23. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 18.3.1.18 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 596 When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 597 CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic command write sequence is shown in Figure 18-25. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 598 Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 18-25. Generic Flash Command Write Sequence Flowchart MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 599 P-Flash Commands Table 18-27 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 600 Erase Flash Block An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT register is set prior to launching the command. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 601 The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 18-29. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x01 Not required MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 602 The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. The section to be verified cannot cross a 256 Kbyte boundary in the P-Flash memory space. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 603 Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF ﬂag will set after the Read Once operation has completed. Valid MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 604 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 605 Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 606 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 18.4.2.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 607 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 608 Table 18-7). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 609 P-Flash or D-Flash block. Table 18-51. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to identify the 0x0D Flash block Margin level setting MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 610 P-Flash or D-Flash block. Table 18-54. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to identify the Flash 0x0E block Margin level setting MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 611 The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified and the number of words. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 612 D-Flash block Global address [15:0] of word to be programmed Word 0 program value Word 1 program value, if desired Word 2 program value, if desired MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 613 Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF ﬂag will set after the Erase D-Flash Sector operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 614 Section 18.3.1.7, “Flash Status Register (FSTAT)”, and Section 18.3.1.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 18-26. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 615 KEYEN[1:0] bits are in the enabled state (see Section 18.3.1.2), the Verify Backdoor Access Key command (see Section 18.4.2.11) allows the user to present four prospective keys for comparison to the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 616 The BDM will execute the Erase Verify All Blocks command write sequence to verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 617: Initialization
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 618 256 KByte Flash Module (S12XFTMR256K1V1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 619: Kbyte Flash Module (S12Xftmr128K1V1)
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Preliminary Downloaded from Elcodis.com...
Page 620 No external high-voltage power supply required for Flash memory program and erase operations • Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Preliminary Downloaded from Elcodis.com electronic components distributor...
Page 621 Flash module is undeﬁned. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 622 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 623 8 Kbytes (up to 29 Kbytes) 0x7F_C000 Flash Protected/Unprotected Higher Region 0x7F_E000 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 Flash Conﬁguration Field P-Flash END = 0x7F_FFFF 16 bytes (0x7F_FF00 - 0x7F_FF0F) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 624 CAUTION Writes to any Flash register must be avoided while a Flash command is active (CCIF=0) to prevent corruption of Flash register contents and Memory Controller behavior. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 625 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV0 0x000D FRSV1 Figure 19-1. FTMR128K1 Register Summary MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 626 = Unimplemented or Reserved Figure 19-2. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 627 The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 628 30.45 31.50 0x1D 31.50 32.55 0x1E 32.55 33.60 0x1F FDIV shown generates an FCLK frequency of >0.8 MHz FDIV shown generates an FCLK frequency of 1.05 MHz MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 629 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. Table 19-7. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 630 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 19.2.1.14, “Flash ECC Error Results Register (FECCR),” for more details. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 631 SFDIE interrupt enable in the FERCNFG register is set (see Section 19.2.1.6) 19.2.1.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 632 CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 633 Reset = Unimplemented or Reserved Figure 19-9. Flash Error Status Register (FERSTAT) All ﬂags in the FERSTAT register are readable and only writable to clear the ﬂag. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 634 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 635 Table 19-17. Table 19-16. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x7F_F800–0x7F_FFFF 2 Kbytes 0x7F_F000–0x7F_FFFF 4 Kbytes 0x7F_E000–0x7F_FFFF 8 Kbytes 0x7F_C000–0x7F_FFFF 16 Kbytes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 636 The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 637 Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 19-11. P-Flash Protection Scenarios MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 638 P-Flash sector containing the D-Flash protection byte must be unprotected, then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 639 0x10_0000 – 0x10_11FF 4608 bytes 1_0010 0x10_0000 – 0x10_12FF 4864 bytes 1_0011 0x10_0000 – 0x10_13FF 5120 bytes 1_0100 0x10_0000 – 0x10_14FF 5376 bytes 1_0101 0x10_0000 – 0x10_15FF 5632 bytes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 640 CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 641 Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 19-15. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 642 Offset Module Base + 0x000F ECCR[7:0] Reset = Unimplemented or Reserved Figure 19-18. Flash ECC Error Results Low Register (FECCRLO) All FECCR bits are readable but not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 643 Offset Module Base + 0x0010 NV[7:0] Reset = Unimplemented or Reserved Figure 19-19. Flash Option Register (FOPT) All bits in the FOPT register are readable but are not writable. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 644 Figure 19-21. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 19.2.1.18 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 645 When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 646 CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic command write sequence is shown in Figure 19-23. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 647 Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 19-23. Generic Flash Command Write Sequence Flowchart MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 648 P-Flash Commands Table 19-26 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 649 Erase Flash Block An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT register is set prior to launching the command. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 650 The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 19-28. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x01 Not required MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 651 The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. The section to be verified cannot cross a Kbyte boundary in the P-Flash memory space. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 652 Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF ﬂag will set after the Read Once operation has completed. Valid MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 653 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 654 Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 655 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 19.3.2.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 656 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 657 Table 19-6). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 658 P-Flash or D-Flash block. Table 19-50. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to identify the 0x0D Flash block Margin level setting MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 659 P-Flash or D-Flash block. Table 19-53. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [22:16] to identify the Flash 0x0E block Margin level setting MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 660 The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified and the number of words. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 661 D-Flash block Global address [15:0] of word to be programmed Word 0 program value Word 1 program value, if desired Word 2 program value, if desired MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 662 Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF ﬂag will set after the Erase D-Flash Sector operation has completed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 663 Section 19.2.1.7, “Flash Status Register (FSTAT)”, and Section 19.2.1.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 19-24. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 664 KEYEN[1:0] bits are in the enabled state (see Section 19.2.1.2), the Verify Backdoor Access Key command (see Section 19.3.2.11) allows the user to present four prospective keys for comparison to the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 665 The BDM will execute the Erase Verify All Blocks command write sequence to verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 666 If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 667: Motor Controller (Mc10B8Cv1)
The motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the FAST bit. This bit influences all PWM channels. For details, please refer to Section 20.3.2.5, “Motor Controller Duty Cycle Registers”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 668 The behavior of the motor controller in low-power modes is programmable. For details, please refer to Section 20.4.5, “Operation in Wait Mode” Section 20.4.6, “Operation in Stop and Pseudo-Stop Modes”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 669 Duty Register 4 Comparator M2C0P M2C1M Duty Register 5 Comparator M2C1P M3C0M Duty Register 6 Comparator M3C0P M3C1M Duty Register 7 Comparator M3C1P Figure 20-1. MC10B8C Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 670 High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 671 Motor Controller Channel Control Register 2 (MCCC2) 0x0013 Motor Controller Channel Control Register 3 (MCCC3) 0x0014 Motor Controller Channel Control Register 4 (MCCC4) 0x0015 Motor Controller Channel Control Register 5 (MCCC5) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 672 0x0035 Reserved — 0x0036 Reserved — 0x0037 Reserved — 0x0038 Reserved — 0x0039 Reserved — 0x003A Reserved — 0x003B Reserved — 0x003C Reserved — 0x003D Reserved — MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 673 0 A motor controller timer counter overﬂow has not occurred since the last reset or since the bit was cleared. 1 A motor controller timer counter overﬂow has occurred. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 674 Motor Controller Timer Counter Overﬂow Interrupt Enable MCTOIE 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overﬂow interrupt ﬂag (MCTOIF) is set. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 675 Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is programmed to 0x0000. All PWM channels will be shut off after the next period timer counter overﬂow. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 676 Half H-bridge mode, PWM on MnCxP, MnCxM is released Full H-bridge mode Dual full H-bridge mode Table 20-8. PWM Alignment Mode MCAM[1:0] PWM Alignment Mode Channel disabled Left aligned Right aligned Center aligned MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 677 Offset Module Base + 0x0020 . . . 0x002F Access: User read/write Reset = Unimplemented or Reserved Figure 20-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 678 Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme. ⋅ 6. Odd duty cycle register: MCDCx+1, x = 2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 679 MCDCx + 1 PWM Channel x + 1, x = 2 MnC1M MnC1P MCMC0 MCDC0 PWM Channel 0 M0C0M M0C0P MCMC1 MCDC1 PWM Channel 1 M0C1M M0C1P MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 680 RECIRC bit. The value of the PWM duty cycle is determined by the value of the D[10:0] or D[8:2] bits respectively in the duty cycle register depending on the state of the FAST bit. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 681 MCOM[1:0] bits in the MCCCx (channel control) register. See register description in Section 20.3.2.4, “Motor Controller Channel Control Registers”. In half H-bridge mode, the state of the S bit has no effect. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 682 (high if RECIRC = 0 or low if RECIRC = 1) after the number of counts specified by the corresponding duty cycle register. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 683 Timer Counter PWM Output 1 Period 1 Period 100 Counts 100 Counts DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 684 S bit behavior is inverted if RECIRC = 1. Figure 20-12, Figure 20-13, Figure 20-14, and Figure 20-15 illustrate the effect of the RECIRC bit in (dual) full H-bridge modes. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 685 Figure 20-12. PWM Active Phase, RECIRC = 0, S = 0 Static 0 PWM 0 MnC0P MnC0M Static 0 PWM 0 Figure 20-13. PWM Passive Phase, RECIRC = 0, S = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 686 Figure 20-14. PWM Active Phase, RECIRC = 1, S = 0 Static 1 PWM 1 MnC0P MnC0M Static 1 PWM 1 Figure 20-15. PWM Passive Phase, RECIRC = 1, S = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 687 10 or 11 Passive (Dual) Full 10 or 11 Active (Dual) Full 10 or 11 Passive (Dual) Full 10 or 11 Active (Dual) Full 10 or 11 Passive MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 688 PWM period (when the motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 689 PWM Output 1 Period 100 Counts 100 Counts Figure 20-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 690 PWM Output 1 Period 100 Counts 100 Counts Figure 20-21. PWM Output: DITH = 1, MCAM[1:0] = 11, MCDC = 31, MCPER = 200, RECIRC = 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 691 MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel frequency of operation can be calculated using the following formula if DITH = 0: Motor Channel Frequency (Hz) ------------------------------ - ⋅ MCPER M MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 692 0, 1, 2, or 3 motor controller timer counter clock cycles. NOTE A PWM channel gets disabled at the next timer counter overﬂow without notice of the switching delay. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 693: Reset
PWM frame is finished. The interrupt is cleared by either setting the MCTOIE bit to 0 or to write a 1 to the MCTOIF bit in the motor controller control register 0. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 694 The period register is cleared after a certain time, which disables the motor controller. The table address is restored and the timer interrupt ﬂag is cleared. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 695 ; motor controller period ;------------------------------------------------------------------------------------------ ;------------------------------------------------------------------------------------------ CODE_START ; start of code #$1FFF ; set stack pointer MOVW #$000A,TABLESIZE ; number of configurations in the table MOVW TABLESIZE,TEMP_X MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 696 ; define pwm period NEW_SEQ: MOVW TABLESIZE,TEMP_X ; start new tx loop TEMP_X END_SR: TEMP_X ; save byte counter MOVB #$80,TFLG2 ; clear TOF ; wait for new timer overflow MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 697 $02, $60 ; MCDC1_HI, MCDC1_LO DC.B $02, $25 ; MCDC0_HI, MCDC0_LO 7. The values for the duty cycle table have to be deﬁned for the needs of the target application. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 698 Motor Controller (MC10B8CV1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 699: Stepper Stall Detector (Ssdv1)
Programmable full step state • Programmable integration polarity • Blanking (recirculation) state • 16-bit integration accumulator register • 16-bit modulus down counter with interrupt • Multiplex two stepper motors MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 700 – 16-bit accumulator VDDM register 16-bit load register sigma-delta converter 16-bit modulus (analog) VSSM down counter 4:1 MUX 2:1 MUX Bus Clock Figure 21-1. SSD Block Diagram MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 701 SINxM/SINxP — Sine Coil Pins for Motor x These pins interface to the sine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 702 This section describes in detail all the registers and register bits in the SSDV1 block. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 703 Polarity — This bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode. Table 21-5 shows the condition state of each switch from Figure 21-1 based on the ITG, STEP and POL bits. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 704 Table 21-4. Transistor Condition States (RTZE = 1) STEP DCOIL RCIR MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 705 Module Base + 0x0001 MCZIE MODMC RDMCL MCEN AOVIE FLMC Reset = Unimplemented or Reserved Figure 21-3. Modulus Down Counter Control Register (MDCCTL) Read: anytime Write: anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 706 Stepper Stall Detector Control Register (SSDCTL) Module Base + 0x0002 RTZE SDCPU SSDWAI FTST ACLKS Reset = Unimplemented or Reserved Figure 21-4. Stepper Stall Detector Control Register (SSDCTL) Read: anytime Write: anytime MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 707 500 kHz / 64 625 kHz 391 kHz 250 kHz NOTE A change in the accumulator sample frequency will not be effective until the ITG bit is cleared. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 708 Reset Figure 21-6. Modulus Down-Counter Count Register High (MDCCNT) Module Base + 0x0005 MDCCNT Reset Figure 21-7. Modulus Down-Counter Count Register Low (MDCCNT) Read: anytime Write: anytime. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 709 Figure 21-9. Integration Accumulator Register Low (ITGACC) Read: anytime. Write: Never. NOTE A separate read for high byte and low byte gives a different result than accessing the register as a word. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 710 (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is driven. In blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 711 Figure 21-10. Full Steps (CCW) Figure 21-11 shows the current ﬂow in the SINx and COSx H-bridges when STEP = 0, DCOIL = 1, ITG = 0 and RCIR = 0. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 712 Figure 21-12. Current Flow when STEP = 1, DCOIL = 1, ITG = 0, RCIR = 1 Figure 21-13 shows the current ﬂow in the SINx and COSx H-bridges when STEP = 2, DCOIL = 1 and ITG = 1. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 713 ﬂow in the SINx and COSx H-bridges when STEP = 3, DCOIL = 1 and ITG = 1. VDDM VDDM COSxP COSxM SINxP SINxM VSSM VSSM Figure 21-14. Current ﬂow when STEP = 3, DCOIL = 1, ITG = 1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 714 ﬂowchart and software setup for stall detection of a stepper motor. To control a second stepper motor, the SMS bit must be toggled during the SSD initialization. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 715 ITGACC < Threshold (RAM value)? Stall Detection? 1. Clear MCZIF. Disable SSD 2. Clear MCEN. 3. Clear ITG. 4. Clear RTZE; clear SDCPU. Figure 21-15. Return-to-Zero Flowchart MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 716 Stepper Stall Detector (SSDV1) Block Description MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 717: Electrical Characteristics
The 9S12XHY family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, and PLL as well as the digital core. The VDDA, VSSA pin pairs supply the A/D converter and parts of the internal voltage regulator. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 718: A.1.3 Pins
This group is made up by the VDDA/V and VSSA/V pins. A.1.3.3 Oscillator The pins EXTAL, XTAL dedicated to the oscillator have a nominal 1.8V level. They are supplied by VDDPLL. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 719: A.1.4 Current Injection
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V or V SS35 DD35 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 720: A.1.6 Esd Protection And Latch-Up Immunity
Complete DC parametric and functional testing is performed per the applicable device speciﬁcation at room temperature followed by hot temperature, unless speciﬁed otherwise in the device speciﬁcation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 721: A.1.7 Operating Conditions
Symbol Unit I/O, regulator and analog supply voltage 3.13 DD35 NVM logic supply voltage ∆ Voltage difference V to V to V refer to Table A-12 VDDX MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 722: A.1.8 Power Dissipation And Thermal Characteristics
The average chip-junction temperature (T obtained from: • Θ Junction Temperature, [°C ] Ambient Temperature, [°C ] Total Chip Power Dissipation, [W] Θ Package Thermal Resistance, [°C/W] MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 723 Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal voltage regulator disabled ⋅ ⋅ ⋅ DDPLL DDPLL 2. Internal voltage regulator enabled ⋅ ⋅ MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 724: A.1.9 I/O Characteristics
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 725 =5V, 10% to 90% of V Cload 4.7nF connected to GND, slew disabled — — Rload=1KΩ connected to GND, slew enabled Rload=1KΩ connected to VDD,, slew enabled MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 726: A.1.10 Supply Currents
An overhead of current consumption exists independent of the listed modules, due to voltage regulation and clock logic that is not dedicated to a speciﬁc module. This is listed in the table row named “overhead”. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 727 40MHz bus frequency from a 4MHz input. Characterized parameters are derived using a 4MHz loop controlled Pierce oscillator. Production test parameters are tested with a 4MHz square wave oscillator. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 728 DD35 Stop currents are measured with the oscillator conﬁgured for 4MHz LCP mode. Production test parameters are tested with a 4MHz square wave oscillator. A.1.10.4 Measurement Results MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 729 Run supply current (No external load, Peripheral Conﬁguration see Table A-8.) Peripheral Set 24.9 31.9 DD35 =4MHz, f =40MHz — Wait supply current Peripheral Set ,PLL on — 16.35 19.9 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 730 Stop Current (API active) µA –40°C — — 25°C — — 150°C — — Stop Current (ATD active) µA -40°C — — 25°C — — 150°C — — MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 731: A.2 Atd Characteristics
PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply pins. Although internal design measures are implemented to minimize the affect of output driver noise, it MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 732 The additional input voltage error on the converted channel can be calculated as: = K * R with I being the sum of the currents injected into the two pins adjacent to the converted channel. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 733: A.2.3 Atd Accuracy
A.2.3 ATD Accuracy Table A-14 Table A-15 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 734 The integral non-linearity (INL) is deﬁned as the sum of all DNLs: ∑ – INL n ( ) DNL i ( ) -------------------- - n – 1LSB MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 735 95 100 105 110 115 120 5000 + Figure A-1. ATD Accuracy Deﬁnitions NOTE Figure A-1 shows only deﬁnitions, for speciﬁcation values refer to Table A- Table A-15. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 736: A.3 Nvm, Flash
The program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV register. The frequency of this clock must be set within the limits speciﬁed as f NVMOP MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 737 The programming time for a single phrase of four P-Flash words + associated eight ECC bits is dependant on the bus frequency as a well as on the frequency f and can be calculated according to the NVMOP following formulas. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 738 NVMOP f NVMBUS A.3.1.7 Erase All Blocks (FCMD=0x08) Erasing all blocks takes: ≈ ⋅ ⋅ 100100 35000 --------------------------- - ------------------------ - mass f NVMOP f NVMBUS MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 739 The maximum set user margin level time is given by ⋅ --------------------------- - f NVMBUS A.3.1.13 Set Field Margin Level (FCMD=0x0E) The maximum set ﬁeld margin level time is given by MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 740 --------------------------- - ------------------------ - f NVMBUS NVMOP The D-Flash sector erase time on a new device is ~5ms and can extend to 20ms as the ﬂash is cycled. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 741: A.3.2 Nvm Reliability Parameters
However it is recommended that each block or sector is erased before factory programming to ensure that the full data retention capability is achieved. Data retention time is measured from the last erase operation. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 742 25°C using the Arrhenius equation. For additional information on how Freescale deﬁnes Typical Data Retention, please refer to Engineering Bulletin EB618 does not exceed 85°C in a typical temperature proﬁle over the lifetime of a consumer, industrial or automotive Javg application. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 743: A.4 Voltage Regulator
Monitors VDDX, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-2) The API Trimming bits must be set that the minimum period equals to 0.2 ms. A hysteresis is guaranteed by design MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 744: A.5 Output Loads
Figure A-2 LVID LVIA LVRXD LVRXA PORD LVI enabled LVI disabled due to LVR LVRX Figure A-2. 9S12XHY family - Chip Power-up and Voltage Drops (not scaled) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 745 V and V must be powered up together adhering to the operating conditions differential. power up must follow V to avoid current injection. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 746: A.6 Reset, Oscillator And Pll
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will resume operation in self-clock mode after t MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 747 The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts fetching the interrupt vector. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 748: A.6.2 Oscillator
VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 749 ⎝ ⎠ For N < 1000, the following equation is a good ﬁt for the maximum jitter: ------- - J(N) Figure A-5. Maximum bus clock jitter approximation MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 750: A.7 Lcd Driver
BP/FP cept GND 1) Outputs measured one at a time, low impedance voltage source connected to the VLCD pin. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 751 They are not to scale. The buffer output characteristic is shown in Figure A-8.. The resistive output characteristic is also valid if an output is forced to GND or VLCD. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 752 2/3VLCD 1/2VLCD 1/3VLCD Figure A-7. V transients (not to scale) 1/3, 1/2 or 2/3 VLCD BP/FP resistive region current source BP/FP region Figure A-8. buffer output characteristic MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 753: A.8 Mscan
Table A-4 unless otherwise noted Num C Rating Symbol Unit µs P MSCAN wakeup dominant pulse ﬁltered — — µs P MSCAN wakeup dominant pulse pass — — MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 754: A.9 Spi Timing
1. If conﬁgured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB. Figure A-9. SPI Master Timing (CPHA = 0) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 755 /2) means select minimum frequency value from 16MHZ and f /2MHZ. same for the other MIN(X,Y) 5. MAX(62.5, 2*t ) means select the maximum period value from 62.5ns and 2*t ns. same for the other MAX(X,Y) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 756: A.9.2 Slave Mode
Slave LSB OUT Note (Output) MOSI MSB IN Bit MSB-1 . . . 1 LSB IN (Input) NOTE: Not deﬁned Figure A-12. SPI Slave Timing (CPHA = 1) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 757 SPI on Port V with slew rate control enabled. All the SPI pins slew rate control should be enabled 0.5 t added due to internal synchronization delay MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 758: Package And Die Information
Package and Die Information Appendix B Package and Die Information This section provides the physical dimensions of the 9S12XHY family packages information. MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 759: B.1 112-Pin Lqfp Mechanical Dimensions
Package and Die Information 112-pin LQFP Mechanical Dimensions Figure B-1. 112-pin LQFP (case no. 987) - page 1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 760 Package and Die Information Figure B-2. 112-pin LQFP (case no. 987) - page 2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 761 Package and Die Information Figure B-3. 112-pin LQFP (case no. 987) - page 3 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 762: B.2 100-Pin Lqfp Mechanical Dimensions
Package and Die Information 100-Pin LQFP Mechanical Dimensions Figure B-4. 100-pin LQFP(case no.983) -page 1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 763 Package and Die Information Figure B-5. 100-pin LQFP(case no.983) - page 2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 764 Package and Die Information Figure B-6. 100-pin LQFP(case no.983) - page 3 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 765: Pcb Layout Guidelines
X7R/tantalum >=100 nF ﬁlter capacitor Ceramic X7R 220 nF ﬁlter capacitor Ceramic X7R 220 nF OSC load capacitor From crystal manufacturer OSC load capacitor Quartz — — MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 766: C.1.1 112-Pin Lqfp Recommended Pcb Layout
PCB Layout Guidelines C.1.1 112-Pin LQFP Recommended PCB Layout Figure C-1. 112-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 767: C.1.2 100-Pin Qfp Recommended Pcb Layout
PCB Layout Guidelines C.1.2 100-Pin QFP Recommended PCB Layout Figure C-2. 100-Pin QFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 768: Derivative Differences
PORTA PA 0 0x0001 PORTB 0x0002 DDRA DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0x0003 DDRB DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0x0004 Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 769 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0010 GPAGE 0x0011 DIRECT DP15 DP14 DP13 DP12 DP11 DP10 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 770 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001C ECLKCTL NECLK DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0x001D Reserved 0x001E IRQCR IRQE IRQEN XIRQEN 0x001F Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 771 This represents the contents if the Comparator A or C control register is blended into this address This represents the contents if the Comparator B or D control register is blended into this address MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com...
Page 772 RTR3 RTR2 RTR1 RTR0 0x003C COPCTL WCOP RSBCK WRTMAS 0x003D FORBYP Reserved For Factory Test 0x003E CTCTL Reserved For Factory Test 0x003F ARMCOP Bit 7 Bit 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 773 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0055 TC2L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 774 0x0064– Reserved 0x006B 0x006C OCPD OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0x006D Reserved 0x006E PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x006F Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 775 Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x0088 ATDDR4 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” 0x008A ATDDR5 Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 776 CAE0 0x00A5 PWMCTL CON67 CON45 CON23 CON01 PSWAI PFRZ PWMTST 0x00A6 Test Only 0x00A7 PWMPRSC 0x00A8 PWMSCLA Bit 7 Bit 0 0x00A9 PWMSCLB Bit 7 Bit 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 777 Bit 7 Bit 0 0x00BA PWMPER6 Bit 7 Bit 0 0x00BB PWMPER7 Bit 7 Bit 0 0x00BC PWMDTY0 Bit 7 Bit 0 0x00BD PWMDTY1 Bit 7 Bit 0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 778 RSRC WAKE 0x00C8 SCI0ASR1 RXEDGIF BERRV BERRIF BKDIF 0x00C9 SCI0ACR1 RXEDGIE BERRIE BKDIE 0x00CA SCI0ACR2 BERRM1 BERRM0 BKDFE 0x00CB SCI0CR2 TCIE ILIE TDRE RDRF IDLE 0x00CC SCI0SR1 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 779 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00D8 SPICR1 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x00D9 SPICR2 XFRW MODFEN BIDIROE SPISWAI SPC0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 780 0x00E7 Reserved 0x00E8–0x00FF Reserved Register Space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00E8- Reserved 0x00FF MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 781 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 0x010E FECCRHI ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 0x010F FECCRLO 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 782 0x0129 INT_CFDATA1 RQST PRIOLVL[2:0] 0x012A INT_CFDATA2 RQST PRIOLVL[2:0] 0x012B INT_CFDATA3 RQST PRIOLVL[2:0] 0x012C INT_CFDATA4 RQST PRIOLVL[2:0] 0x012D INT_CFDATA5 RQST PRIOLVL[2:0] 0x012E INT_CFDATA6 RQST PRIOLVL[2:0] 0x012F INT_CFDATA7 RQST PRIOLVL[2:0] MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 783 RXERR1 RXERR0 0x014E CAN0RXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0x014F CAN0TXERR 0x0150- CAN0IDAR0- 0x0153 CAN0IDAR3 0x0154- CAN0IDMR0- 0x0157 CAN0IDMR3 0x0158- CAN0IDAR4- 0x015B CAN0IDAR7 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 784 Extended ID ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 CANxTIDR1 0xXX0x XX10 Standard ID IDE=0 Extended ID ID14 ID13 ID12 ID11 ID10 CANxTIDR2 0xXX12 Standard ID MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 785 TXE0 0x0187 CAN1TIER TXEIE2 TXEIE1 TXEIE0 0x0188 CAN1TARQ ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 0x0189 CAN1TAAK 0x018A CAN1TBSEL IDHIT2 IDHIT1 IDHIT0 0x018B CAN1IDAC IDAM1 IDAM0 0x018C Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 786 MCOM0 MCAM1 MCAM0 0x01D1 MCCC1 MCOM1 MCOM0 MCAM1 MCAM0 0x01D2 MCCC2 MCOM1 MCOM0 MCAM1 MCAM0 0x01D3 MCCC3 MCOM1 MCOM0 MCAM1 MCAM0 0x01D4 MCCC4 MCOM1 MCOM0 MCAM1 MCAM0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 787 0x01E7 MCDC3 (lo) 0x01E8 MCDC4 (hi) 0x01E9 MCDC4 (lo) 0x01EA MCDC5 (hi) 0x01EB MCDC5 (lo) 0x01EC MCDC6 (hi) 0x01ED MCDC6 (lo) 0x01EE MCDC7 (hi) 0x01EF MCDC7 (lo) MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 788 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0 0x020F LCDRAM7 FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0 0x0210 LCDRAM8 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 789 0x0220 DCOIL RCIR STEP RTZ0CTL 0x0221 MCZIE MODMC RDMCL MCEN AOVIE MDC0CTL FLMC 0x0222 RTZE SDCPU SSDWAI FTST ACLKS SSD0CTL 0x0223 MCZIF AOVIF SSD0FLG 0x0224 MDCCNT[15:8] MDC0CNTH MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 790 0x0230 DCOIL RCIR STEP RTZ2CTL 0x0231 MCZIE MODMC RDMCL MCEN AOVIE MDC2CTL FLMC 0x0232 RTZE SDCPU SSDWAI FTST ACLKS SSD2CTL 0x0233 MCZIF AOVIF SSD2FLG 0x0234 MDCCNT[15:8] MDC2CNTH MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 791 DDRT2 DDRT1 DDRT0 0x0243 Reserved 0x0244 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0x0245 PPST PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0x0246 Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 792 PERP0 0x025D PPSP PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0 0x025E PTPRRH PTPRRH7 PTPRRH6 PTPRRH5 PTPRRH4 PTPRRH3 PTPRRH2 PTPRRH1 PTPRRH0 0x025F PTPRRL PTPRRL3 PTPRRL2 PTPRRL1 PTPRRL0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 793 PTIR2 PTIR1 PTIR0 0x0281 PTIR 0x0282 DDRR7 DDRR6 DDRR5 DDRR4 DDRR3 DDRR2 DDRR1 DDRR0 DDRR Reserved 0x0283 0x0284 PERR7 PERR6 PERR5 PERR4 PERR3 PERR2 PERR1 PERR0 PERR MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 794 PTV4 PTV3 PTV2 PTV1 PTV0 PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTIV1 PTIV0 0x0299 PTIV 0x029A DDRV7 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0 DDRV 0x029B Reserved MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 795 TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0x02AB TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0x02AC 0x02AD TSCR2 TCRE 0x02AE TFLG1 0x02AF TFLG2 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 796 PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 0x02C3 PACNTL PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0x02C4 – Reserved 0x02CB 0x02CC OCPD OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 797 Bit 0 0x02F8– Reserved 0x02FF 0x0300–0x03FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0300 PWME MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 798 Detailed Register Address Map 0x0400–0x07FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0400- Reserved 0x07FF MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 799: Ordering Information
S or SC = Maskset specific part number MC = Generic / mask-independent part number P or PC = prototype status (pre qualification) Figure F-1. Order Part Number Example MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 800 Ordering Information MC9S12XHY-Family Reference Manual, Rev. 1.01 Freescale Semiconductor Downloaded from Elcodis.com electronic components distributor...
Page 801 Downloaded from Elcodis.com electronic components distributor...
Page 802 “Typicals” must be validated for each customer application by customer’s technical experts. Asia/Paciﬁc: Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor H.K. Ltd. Freescale Semiconductor products are not designed, intended, or authorized for use as components...

This manual is also suitable for:

Mc9s12xhy256 S12