Freescale Semiconductor MC9S12VR Series Reference Manual

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MC9S12VR-Family

Reference Manual

S12

Microcontrollers

MC9S12VRRMV2

Rev. 2.2

June 20, 2011

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Page 1 MC9S12VR-Family Reference Manual Microcontrollers MC9S12VRRMV2 Rev. 2.2 June 20, 2011 freescale.com Downloaded from Elcodis.com electronic components distributor...
Page 2 • Added M.1.18 • Minor corrections in Clock, Reset and Power Management (S12CPMU_UHV) 20-June-2011 Rev 2.2 • Removed “Freescale Conﬁdential Proprietary” MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 3 Appendix K SPI Electrical Specifications ......549 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 4 Appendix O Detailed Register Address Map......571 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 5: Table Of Contents
1.11.3 Effects of Reset ............46 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 6 2.3.33 Port L Digital Input Enable Register (DIENL) ....... . 83 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 7 3.4.5 Interrupts ............117 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 8 5.1.3 Block Diagram ............177 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 9 6.5.6 Scenario 5 ............239 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 10 Interrupts ..............275 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 11 10.5.4 Recovery from Wait Mode ..........344 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 12 12.4.5 Event Counter Mode ........... 397 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 13 14.2.2 LSGND — Low Side Driver Ground Pin ........413 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 14 16.1.1 Features ............. 443 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 15 A.1.3 Current Injection ............511 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 16 G.3 Dynamic Electrical Characteristics ..........538 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 17 M.1.15 Program D-Flash (FCMD=0x11) ......... . 560 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 18 O.1 Detailed Register Map............571 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 19: Introduction
• Window lift modules • Door modules • Seat controllers • Smart actuators MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 20: Features
General purpose I/Os (5V) Up to 28 Direct battery sense pin Supply voltage sense Chip temperature sensor 1 general sensor MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 21: Chapter 1 Device Overview Mc9S12Vr-Family
20mA high-current output for use as Hall sensor supply • Battery voltage sense with low battery warning, internally reverse battery protected • Chip temperature sensor MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 22: Features
— Automated program and erase algorithm — User margin level setting for reads 1.4.3 On-Chip SRAM • 2 Kbytes of general-purpose RAM MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 23: Main External Oscillator (Xosclcp)
Computer operating properly (COP) watchdog with option to run on internal RC oscillator — Conﬁgurable as window COP for enhanced failure detection MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 24: Timer (Tim)
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable character length MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 25: Analog-To-Digital Converter Module (Atd)
— Linear voltage regulator with bandgap reference — Low-voltage detect with low-voltage interrupt on VDDA — Power-on reset (POR) circuit — Low-voltage reset (LVR) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 26: Low-Side Drivers (Lsdrv)
— Force This is valid on the ﬁrst instruction boundary after a match occurs • Four trace modes • Four stage state sequencer MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 27: Block Diagram
Block Diagram shows the maximum configuration! Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 28: Family Memory Map
0x0160-0x0167 LINPHY (LIN physical layer) 0x0168-0x016F Reserved 0x0170-0x0177 BATS (Supply Voltage Sense) 0x0178–0x023F Reserved 0x0240–0x027F PIM (port integration module) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 29 Flash space on page 0xC in Figure 1-2 is not available on S12VR48. This is only available on S12VR64. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 30 Page 0xE Page 0xE 0x3_C000 Flash Space Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 1-2. MC9S12VR-Family Global Memory Map. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 31: Part Id Assignments
To avoid current drawn from ﬂoating inputs, all non-bonded pins should be conﬁgured as output or conﬁgured as input with a pull up or pull down device enabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 32: Detailed Signal Descriptions
PS[5:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-up devices are enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 33 This signal is associated with the MISO functionality of the serial peripheral interface SPI. This signal acts as master input during master mode or as slave output during slave mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 34 IOC[3:0] Signals The signals IOC[3:0] are associated with the input capture or output compare functionality of the timer (TIM) module. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 35: Power Supply Pins
LGND is the the ground pin for the LIN physical layer LINPHY. 1.7.3.5 LSGND — Ground Pin for Low-Side Drivers LSGND is the shared ground pin for the low-side drivers. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 36: Device Pinouts
MC9S12VR-Familyis available in 48-pin package and 32-pin package. Signals in parentheses in Figure 1-3. and Figure 1-4. denote alternative module routing options. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 37: Pinout 48-Pin Lqfp
HS0 / (OC2) / (PWM3) SCK / PS4 VSUPHS SS / PS5 VSUP MODC / BKGD Figure 1-3. MC9S12VR 48-pin LQFP pinout MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 38: Pinout 32-Pin Lqfp
ECLK / MOSI / (TXD1) / (PWM5) / (ETRIG1) / PS3 VSUP MODC / BKGD Figure 1-4. MC9S12VR 32-pin LQFP pinout MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 39 — — — VSUPHS — — — — — — — — PWM3 — — — — — SUPH MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 40 Disabled — RXD0 RXD1 — — — PERS/PPSS — TXD0 LPDR1 TXD1 — — PERS/PPSS Timer Output Compare Channel MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 41: Modes Of Operation
(PLL) frequency. To save power, unused peripherals must not be enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 42: Security
External pin RESET None None $FFFE Illegal Address Reset None None $FFFC Clock monitor reset None OSCE Bit in CPMUOSC register MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 43 I bit ATDCTL2 (ASCIE) Vector base + $D0 Reserved Vector base + $CE Port L I bit PIEL (PIEL3-PIEL0) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 44: Resets
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 45 Table 1-11 Table 1-12 for coding Table 1-11. Initial COP Rate Conﬁguration NV[2:0] in CR[2:0] in FOPT Register COPCTL Register MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 46 BATS module SENSE 16.1.1 Features Internal_5 High voltage inputs Port L see 2.3.34 Port L Analog Access Register (PTAL) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 47 6-pin port S associated with 2 SCI and 1 SPI • 6-pin port P with pin interrupts and wakeup function; associated with — IRQ, XIRQ interrupt inputs MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 48: Port Integration Module (S12Vrpimv2
Input with selectable pullup or pulldown device Optional features supported on dedicated pins: • Two selectable output drive strengths • Open drain for wired-or connections MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 49: Chapter 2 Port Integration Module (S12Vrpimv2)
Serial Communication Interface 0 receive pin PWM6 O Pulse Width Modulator channel 6 IOC0 I/O TIM channel 0 PTT[0] I/O General-purpose MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 50 I/O General-purpose RXD1 Serial Communication Interface 1 receive pin (RXD0) Serial Communication Interface 0 receive pin PTS[0] I/O General-purpose MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 51 Function active when RESET asserted Memory Map and Register Deﬁnition This section provides a detailed description of all PIM registers. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 52 Address Range 0x0240 PTT3 PTT2 PTT1 PTT0 PTIT3 PTIT2 PTIT1 PTIT0 0x0241 PTIT 0x0242 DDRT DDRT3 DDRT2 DDRT1 DDRT0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 53 MODRR25 MODRR24 MODRR23 MODRR22 MODRR21 MODRR20 0x0250– Reserved 0x0257 0x0258 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 0x0259 PTIP MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 54 PIEL2 PIEL1 PIEL0 0x026F PIFL3 PIFL2 PIFL1 PIFL0 PIFL 0x0270 Reserved 0x0271 PT1AD PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 55 The conﬁguration bit PPS is used for two purposes: 1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 56 Figures of module routing registers also display the module instance or module channel associated with the related routing bit. 1. Not applicable for Port L. Refer to register descriptions. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 57 Address 0x0009 Access: User read/write DDRE1 DDRE0 Reset Figure 2-2. Port E Data Direction Register (DDRE) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 58: Port E, Bkgd Pin Pull Control Register (Pucr)
0 Pulldown devices disabled 2.3.6 ECLK Control Register (ECLKCTL) Address 0x001C Access: User read/write NECLK Reset Figure 2-4. ECLK Control Register (ECLKCTL) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 59: Pim Miscellaneous Register (Pimmisc)
2.3.8 IRQ Control Register (IRQCR) Address 0x001E Access: User read/write IRQE IRQEN Reset Figure 2-6. IRQ Control Register (IRQCR) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 60: Reserved Register
Writing to these registers when in special modes can alter the module’s functionality. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 61: Port T Data Register (Ptt)
• The routed LINPHY function takes precedence over the TIM output function and the general-purpose I/O function if the related channel is enabled. • The TIM function takes precedence over the general-purpose I/O function. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 62: Port T Input Register (Ptit)
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 63: Port T Data Direction Register (Ddrt)
TIM port associated with an enabled TIM output compare. In these cases the data direction bit will not change. 1 Associated pin is conﬁgured as output 0 Associated pin is conﬁgured as input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 64: Port T Pull Device Enable Register (Pert)
This bit selects a pullup or a pulldown device if enabled on the associated port input pin. 1 A pulldown device is selected 0 A pullup device is selected MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 65: Module Routing Register 0 (Modrr0)
01 TIM output compare channel 0 routed to LS0 if enabled 00 LS0 controlled by register bit LSDR[LSDR0]. Refer to LSDRV section. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 66: Module Routing Register 1 (Modrr1)
PWM function available on this pin only if not used with a routed HSDRV or LSDRV function. Refer to Section 2.3.15, “Module Routing Register 0 (MODRR0)” MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 67 • The routed SCI1 function takes precedence over the routed PWM and the general-purpose I/O function if enabled. • The routed PWM function takes precedence over the general-purpose I/O function if enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 68: Port S Input Register (Ptis)
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 69: Port S Data Direction Register (Ddrs)
The routed ETRIG function has no effect on the I/O state. 1 Associated pin is conﬁgured as output 0 Associated pin is conﬁgured as input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 70: Port S Pull Device Enable Register (Pers)
The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 71: Port S Polarity Select Register (Ppss)
1 Output buffer operates as open-drain output 0 Output buffer operates as push-pull output MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 72: Module Routing Register 2 (Modrr2)
SCI0 must be enabled for TXD0 routing to take effect on pins. LINPHY must be enabled for LPRXD and LPDR[LPDR1] routings to take effect on pins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 73 SCI0 connects to LINPHY, interface internal only 0001 Direct control setting: LPDR[LPDR1] register bit controls LPTXD, interface internal only MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 74: Port P Data Register (Ptp)
PWM function available on this pin only if not routed to port S. Refer to Section 2.3.16, “Module Routing Register 1 (MODRR1)” MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 75 • Pin interrupts can be generated if enabled in input or output mode. • An over-current interrupt can be generated if enabled. Refer to Section 2.4.4.3, “Over-Current Interrupt” MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 76: Port P Input Register (Ptip)
A read always returns the synchronized input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 77: Port P Data Direction Register (Ddrp)
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not change. 1 Associated pin is conﬁgured as output 0 Associated pin is conﬁgured as input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 78: Port P Reduced Drive Register (Rdrp)
PERP4 PERP3 PERP2 PERP1 PERP0 Reset Figure 2-27. Port P Pull Device Enable Register (PERP) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 79: Port P Polarity Select Register (Ppsp)
PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 Reset Figure 2-29. Port P Interrupt Enable Register (PIEP) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 80: Port P Interrupt Flag Register (Pifp)
1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 81: Port L Input Register (Ptil)
0 Associated pin digital input is disabled Refer to PTTEL bit description in Section 2.3.34, “Port L Analog Access Register (PTAL) for an override condition. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 82: Port L Analog Access Register (Ptal)
1 Input pin directly connected to ADC channel 0 Input voltage divider active on analog input to ADC channel MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 83 HVI pin connected PTAL[PTAL1] PTAL[PTAL0] to ADC HVI0 HVI1 HVI2 HVI3 Refer to device overview section for channel assignment MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 84: Port L Input Divider Ratio Selection Register (Pirl)
This bit selects the polarity of the active pin interrupt edge. 1 Rising edge selected 0 Falling edge selected MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 85: Port L Interrupt Enable Register (Piel)
1 Active edge on the associated bit has occurred 0 No active edge occurred 2.3.39 Port AD Data Register (PT1AD) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 86: Port Ad Input Register (Pti1Ad)
(ATDDIEN) is set to 1. Else a logic 1 is read. It can be used to detect overload or short circuit conditions on output pins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 87: Port Ad Data Direction Register (Ddr1Ad)
To use the digital input function the ADC Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”. 1 Associated pin is conﬁgured as output 0 Associated pin is conﬁgured as input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 88: Port Ad Pull Enable Register (Per1Ad)
This bit also selects the polarity of the active pin interrupt edge. 1 A pulldown device is selected; rising edge selected 0 A pullup device is selected; falling edge selected MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 89: Port Ad Interrupt Enable Register (Pie1Ad)
1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 90: Functional Description
This register deﬁnes whether the pin is used as an general-purpose input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-45). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 91 It becomes only active if the pin is used as an input. A pullup device can be activated if the pin is used as a wired-or output. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 92: General
Port T pins can be used for either general-purpose I/O or with the channels of the standard TIM, SPI, or SCI and LINPHY subsystems. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 93 Capable to wakeup from stop (pin interrupts in run mode not available). Open input detection. Figure 2-46 shows a block diagram of the HVI. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 94 (Ratio , Ratio ) can be chosen on each analog input (PIRL[x]) or the H_HVI L_HVI MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 95 MCU level. Table 2-50. PIM Interrupt Sources Module Interrupt Sources Local Enable XIRQ None IRQCR[IRQEN] Port P pin interrupt PIEP[PIEP5-PIEP0] MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 96 Sample count <= 4 (at active or passive level) and interrupt enabled (PIE[x]=1) and interrupt ﬂag not set (PIF[x]=0). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 97: Interrupts
If the related PWM channel is enabled and not routed for internal use, the PWM signal as seen on the pin will drive the ETRIG input. Else the ETRIG function will be triggered by other functions on the pin including general-purpose input. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 98: Over-Current Protection On Evdd
3. Enable function to force input buffer active on selected HVI in analog mode (PTAL[PTTEL]=1) 4. Verify PTILx=0 for a connected external pulldown device; read PTILx=1 for an open input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 99 21/22 * V (PIRL=1) Digital in 610K / 1050K PIRL=0 / PIRL=1 Figure 2-49. Digital Input Read with Pulldown Enabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 100 Port Integration Module (S12VRPIMV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 101 Port Integration Module (S12VRPIMV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 102 Port Integration Module (S12VRPIMV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 103: Introduction
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 104: S12G Memory Map Controller (S12Gmmcv1
3.1.5 Block Diagram Figure 3-1 shows a block diagram of the S12GMMC. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 105: Chapter 3 S12G Memory Map Controller (S12Gmmcv1)
A summary of the registers associated with the S12GMMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 106 Address: 0x000B MODC Reset MODC 1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 107 This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 108 0 Program ﬂash is mapped to the global address range from 0x04000 to 0x07FFF. 1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 109 The ﬁxed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by Registers, EEPROM and RAM space. See SoC Guide for details. The ﬁxed 16KB page from 0x4000–0x7FFF is the page number 0xD. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 110 (PPAGE[3:0]) to page 16x16 KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 111 CPU is executing a ﬁrmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see Figure 3-10). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 112 BDM FIRMWARE COMMAND Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] CPU Local Address [13:0] Figure 3-10. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 113 Page 0xE 0x3_C000 Flash Space Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 3-11. Local to Global Address Mapping MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 114 On S12VR devices, the CPU and the BDM are not able to access the memory in parallel. An arbitration occurs whenever both modules attempt a memory access at the same time. CPU accesses are handled with MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 115 In this case the pending BDM access will be processed immediately. 3.4.5 Interrupts The S12GMMC does not generate any interrupts. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 116 S12G Memory Map Controller (S12GMMCV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 117: Block Diagram
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal ﬁlter. • The Internal Reference Clock (IRC1M) provides a 1MHz internal clock. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 118 (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 119: Chapter 4 Clock, Reset And Power Management (S12Cpmu_Uhv)
— Low-voltage reset (LVR) — Illegal address access — COP time-out — Loss of oscillation (clock monitor fail) — External pin RESET MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 120: Modes Of Operation
— This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL conﬁguration is valid for the selected oscillator frequency. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 121 CSAD. When bit CSAD is set the ACLK clock source for the COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 122 Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description ﬁeld of Table 4-12 Section 4.3.2.9, “S12CPMU_UHV COP Control Register (CPMUCOP) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 123: S12Cpmu_Uhv Block Diagram
Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 4-1. Block diagram of S12CPMU_UHV MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 124 Peak Gain Control Detector VDD = 1.8 V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 4-2. XOSCLCP Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 125: Signal Description
VDDX, VSSX— Pad Supply Pins This supply domain is monitored by the Low Voltage Reset circuit. VDDX has to be connected externally to VDDA. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 126: Vss, Vssc — Ground Pins
ATD Converter. See device level speciﬁcation for connectivity of ATD special channels. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 127: Memory Map And Registers
LVCTL CPMU 0x02F2 APICLK APIES APIEA APIFE APIE APIF APICTL = Unimplemented or Reserved Figure 4-3. CPMU Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 128 CPMUOSC OSCE Reserved Reserved 0x02FB CPMUPROT PROT RESERVED 0x02FC CPMUTEST2 = Unimplemented or Reserved Figure 4-3. CPMU Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 129: Register Descriptions
Table 4-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz 48MHz < f <= 50MHz Reserved Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 130 REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 131 = Unimplemented or Reserved Figure 4-7. S12CPMU_UHV Flags Register (CPMUFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 132: Interrupts
0 The oscillator is off or oscillation is not qualiﬁed by the PLL. 1 The oscillator is qualiﬁed by the PLL. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 133 Oscillator Corrupt Interrupt Enable Bit OSCIE 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 134 After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL, RTIOSCSEL and COPOSCSEL was successful. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 135 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 136 1 COP clock source is OSCCLK Table 4-6. COPOSCSEL1, COPOSCSEL0 clock source select description COPOSCSEL1 COPOSCSEL0 COP clock source IRCCLK OSCCLK ACLK MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 137 16. See Table 4-8 for coding. Table 4-8. FM Amplitude selection FM Amplitude / Variation FM off ±1% ±2% ±4% MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 138 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 4-10 Table 4-11 show all possible divide values selectable by the CPMURTI register. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 139 1111 (÷16) Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 140 30x10 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (÷15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (÷16) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 141 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 142 (default out of reset) COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 143 Table 4-14. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 144 Mode can alter the S12CPMU_UHV’s functionality. 0x003E Reset = Unimplemented or Reserved Figure 4-14. Reserved Register (CPMUTEST1) Read: Anytime Write: Only in Special Mode MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 145 Figure 4-16. High Temperature Control Register (CPMUHTCTL) Read: Anytime Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 146 Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request. 0 No change in HTDS bit. 1 HTDS bit has changed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 147 1.Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 148 This ﬂag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 149 Clock, Reset and Power Management (S12CPMU_UHV) Figure 4-20. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 150 Decreases period less than ACLKTR[4] ACLKTR[2] Decreases period less than ACLKTR[3] ACLKTR[1] Decreases period less than ACLKTR[2] ACLKTR[0] Decreases period less than ACLKTR[1] MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 151 ACLK release when the API feature gets enabled (APIFE bit set) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 152 FFFE 131070 * Bus Clock period FFFF 131072 * Bus Clock period When f is trimmed to 10KHz. ACLK MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 153 Mode can alter the S12CPMU_UHV’s functionality. 0x02F6 Reset = Unimplemented or Reserved Figure 4-24. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 154 HTTR[2] Increases V twice of HTTR[1] HTTR[1] Increases V twice of HTTR[0] HTTR[0] Increases V (to compensate Temperature Offset) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 155 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 4-28 shows the relationship between the trim bits and the resulting IRC1M frequency. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 156 Clock, Reset and Power Management (S12CPMU_UHV) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 4-28. IRC1M Frequency Trimming Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 157 These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 158 Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 159 Do not alter these bits from their reset value. These are for Manufacturer use only and can change the PLL Reserved behavior. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 160 0 Protection of clock conﬁguration registers is disabled. 1 Protection of clock conﬁguration registers is enabled. (see list of protected registers above). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 161 Mode can alter the S12CPMU_UHV’s functionality. 0x02FC Reset = Unimplemented or Reserved Figure 4-32. Reserved Register CPMUTEST2 Read: Anytime Write: Only in Special Mode MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 162: Functional Description
Although it is possible to set the dividers to command a very high clock frequency, do not exceed the speciﬁed bus frequency limit for the MCU. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 163 • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 164: Startup From Reset
Stop Mode recovery time t . After exit from Stop Mode (Pseudo, Full) for this latency time STP_REC MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 165: Full Stop Mode Using Oscillator Clock As Bus Clock
Stop Mode request (STOP instruction) should be generated to make sure the COP counter can increment at each Stop Mode exit. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 166: External Oscillator
OSCCLK as Core/Bus Clock by writing PLLSEL to zero PLLSEL based on OSCCLK based on PLL Clock Core Clock MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 167: System Clock Conﬁgurations
PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 168: Resets
4-29, an internal circuit drives the RESET pin low for 512 PLLCLK cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU_UHV MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 169 If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is below the failure assert frequency f (see device electrical characteristics for values), the CMFA MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 170 Static (IRCCLK) Static (IRCCLK) Static (OSCCLK) Static (OSCCLK) Static (IRCCLK) Static (IRCCLK) Satic (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 171: Power-On Reset (Por)
The LVR assert and deassert levels for the supply voltage VDDX are V and V and are LVRXA LVRXD speciﬁed in the device Reference Manual. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 172: Interrupts
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 173 Table 4-19 for the trimming effect of APITR. 1. For details please refer to “4.4.6 System Clock Conﬁgurations” MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 174: Initialization/Application Information
If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 175: Chapter 5 Background Debug Module (S12Sbdmv1)
SYNC command to determine communication rate • GO_UNTIL command • Hardware handshake protocol to increase the performance of the serial communication MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 176: Modes Of Operation
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 177: Block Diagram
Memory Map and Register Deﬁnition 5.3.1 Module Memory Map Table 5-2 shows the BDM memory map when BDM is active. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 178: Register Descriptions
= Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 5-2. BDM Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 179 — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM ﬁrmware lookup table upon exit from BDM active mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 180 Flash EEPROM is conﬁgured for unsecure mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 181 BDM Program Page Index Bits 3–0 — These bits deﬁne the selected program page. For more detailed BPP[3:0] information regarding the program page window scheme, please refer to the S12S_MMC Block Guide. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 182: Family Id Assignment
After being enabled, BDM is activated by one of the following 1. BDM is enabled and active immediately out of special single-chip reset. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 183: Bdm Hardware Commands
BDM memory resources are 1. This method is provided by the S12S_DBG module. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 184: Standard Bdm Firmware Commands
BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are received. The ﬁrmware commands are shown in Table 5-6. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 185: Bdm Command Structure
If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 186 Section 5.4.6, “BDM Serial Interface” Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 187: Bdm Serial Interface
The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 188 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 189 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 190: Serial Interface Hardware Handshake Protocol
ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 191 ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 192: Hardware Handshake Abort Procedure
BDM internal behavior. It is not recommended that this procedure be used in a real application. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 193 To BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles Figure 5-13. ACK Pulse and SYNC Request Conﬂict MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 194 The ACK pulse related to this command could be aborted using the SYNC command. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 195: Sync — Request Timed Reference Pulse
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 196: Serial Communication Time Out
This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 197 The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 198 Background Debug Module (S12SBDMV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 199: Chapter 6 S12S Debug Module (S12Sdbgv2)
WORD: 16 bit data entity Data Line: 20 bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 200: Overview
— Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 201: Modes Of Operation
COMPARATOR C TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1. Debug Module Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 202: External Signal Description
0x002A DBGXAM Bit 15 Bit 8 0x002B DBGXAL Bit 7 Bit 0 Figure 6-2. Quick Reference to DBG Registers MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 203: Register Descriptions
ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 204 Visible Register at 0x0027 Comparator A DBGSCR1 Comparator B DBGSCR2 Comparator C DBGSCR3 None DBGMFR 6.3.2.2 Debug Status Register (DBGSR) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 205 Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State 101,110,111 Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 206 1 Trigger before storing data Table 6-8. TRCMOD Trace Mode Bit Encoding TRCMOD Description Normal Loop1 Detail Compressed Pure PC MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 207 Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 208 Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undeﬁned. Other resets do not affect the trace buffer contents. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 209 ARM bit will be cleared and the tracing session ends. 000001 64 lines valid, oldest data has been overwritten by most recent data 111110 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 210 DBGC1 to blend in the required register. The COMRV = 11 value blends in the match ﬂag register (DBGMFR). Table 6-14. State Control Register Access Encoding COMRV Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 211 ﬁnal state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 212 ﬁnal state has priority followed by the match on the lower channel number (0,1,2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 213 ﬁnal state has priority followed by the match on the lower channel number (0,1,2). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 214 The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 215 This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. (Comparators 0 Word access size is compared A and B) 1 Byte access size is compared MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 216 RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 217 Read: Anytime. See Table 6-24 for visible register encoding. Write: If DBG not armed. See Table 6-24 for visible register encoding. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 218 Figure 6-19. Debug Comparator Data High Register (DBGADH) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 219 Figure 6-21. Debug Comparator Data High Mask Register (DBGADHM) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 220: Functional Description
A match with a comparator register value can initiate a state sequencer transition to another state (see Figure 6-24). Either forced or tagged matches are possible. Using MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 221: Comparator Modes
RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 222 A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 223 $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n] $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1] MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 224 In the Inside Range comparator mode, comparator pair A and B can be conﬁgured for range comparisons. This conﬁguration depends upon the control register (DBGC2). The match condition requires that a valid MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 225: Match Modes (Forced Or Tagged)
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 226: State Sequence Control
If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 227: Trace Buffer Operation
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 228 ; Source address TRACE BUFFER ENTRY 4 IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 229 PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 230 Figure 6-25. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 231 Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode) 2-bits 6-bits 6-bits 6-bits Line Mode Number Field 3 Field 2 Field 1 Field 0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 232 In compressed Pure PC mode on rollover the line with the oldest MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 233: Tagging
If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 234: Breakpoints
Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 235 Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the ﬁrst instruction executed when normal program execution resumes. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 236: Application Information
A trigger is generated if a given sequence of 2 code events is executed. Figure 6-28. Scenario 2a SCR2=0101 SCR1=0011 Final State State2 State1 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 237: Scenario 3
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 238 Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 239: Scenario 5
OR forks as shown in red this scenario is possible. Figure 6-36. Scenario 7 SCR2=1100 SCR3=1101 SCR1=1101 Final State State3 State2 State1 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 240: Scenario 8
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 241 M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 242 S12S Debug Module (S12SDBGV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 243: Chapter 7 Interrupt Module (S12Sintv1)
7.1.2 Features • Interrupt vector base register (IVBR) • One spurious interrupt vector (at address vector base + 0x0080). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 244: Modes Of Operation
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 245: External Signal Description
Interrupt Vector Base Register (IVBR) Address: 0x0120 IVB_ADDR[7:0] Reset Figure 7-2. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 246: Functional Description
In this case, the CPU will receive the highest priority vector and the system will process this interrupt request ﬁrst, before the original interrupt request is processed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 247: Reset Exception Requests
D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 248: Initialization/Application Information
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 249 X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 250 Interrupt Module (S12SINTV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 251: Chapter 8 Analog-To-Digital Converter (Adc12B6Cv2)
Automatic return to low power after conversion sequence • Automatic compare with interrupt for higher than or less/equal than programmable value MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 252 • Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 253: Modes Of Operation
In Freeze Mode the ADC12B6C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 254: Block Diagram
VSSA ATD 5 Successive Approximation Register (SAR) and DAC Sample & Hold Comparator Analog Figure 8-1. ADC12B6C Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 255: Signal Description
Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 8-2. ADC12B6C Register Summary (Sheet 1 of 2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 256 Section 8.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)” Unimple- 0x001C - 0x002F mented = Unimplemented or Reserved Figure 8-2. ADC12B6C Register Summary (Sheet 2 of 2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 257: Register Descriptions
Table 8-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 258 The coding is summarized in Table 8-5. Table 8-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data 12-bit data Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 259 ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 8-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 260 Interrupt will be requested whenever any of the respective CCF ﬂags is set. Table 8-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 261 8-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 262 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 Table 8-10. Conversion Sequence Length Coding Number of Conversions per Sequence MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 263 Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK Table 8-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 264 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 265 WRAP3-0 the ﬁrst wrap around will be AN5 to AN0. Table 8-15. Analog Input Channel Select Coding Analog Input Channel MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 266 Channel Internal_6, Temperature sense of ADC hardmacro Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 267 C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx ﬂag was still set) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 268 CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 269 If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 270 0 If result of conversion n is lower or same than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is ﬂagged in ATDSTAT2 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 271 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 12-bit data Result-Bit[11:0] = result MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 272 8-bit data Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data Result-Bit[9:0] = result, Result-Bit[11:10]=00 12-bit data Result-Bit[11:0] = result MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 273: Functional Description
ATD module when a conversions is about to take place. The external trigger signal (out of reset ATD channel 5, conﬁgurable in ATDCTL1) is programmable to be edge MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 274 This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC12B6C. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 275: Resets
I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 8.3.2, “Register Descriptions” for further details. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 276 Analog-to-Digital Converter (ADC12B6CV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 277: Chapter 9 Pulse-Width Modulator (S12Pwm8B8Cv2)
The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1. Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 278: Block Diagram
PWM7 - PWM0 — PWM Channel 7 - 0 Those pins serve as waveform output of PWM channel 7 - 0. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 279: Memory Map And Register Deﬁnition
PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 1 of 4) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 280 Bit 7 Bit 0 PWMPER1 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 2 of 4) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 281 Bit 0 PWMDTY7 0x0024 RESERVED = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 3 of 4) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 282 PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 Reset Figure 9-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 283 Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 284 Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 285 PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 286 Figure 9-7. PWM Center Align Enable Register (PWMCAE) Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 287 PWM Function. NOTE Change these bits only when both corresponding channels are disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 288 Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 289 9-5. 1 Clock B or SB is the clock source for PWM channel 0, as shown in Table 9-5. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 290 Figure 9-11. PWM Scale B Register (PWMSCLB) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 291 The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 292 NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 293 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 294: Functional Description
A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 295 Clock Select Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 9-15. PWM Clock Select Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 296 For channels 2, 3, 6, and 7 the clock choices are clock B. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 297: Pwm Channel Timers
Section 9.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 298 Figure 9-16 and described in Section 9.4.2.5, “Left Aligned Outputs” Section 9.4.2.6, “Center Aligned Outputs”. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 299 Section 9.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 300 E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 9-18. PWM Left Aligned Output Example Waveform MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 301 — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 302 9-21. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 303 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 304: Resets
The 8-bit up/down counter is conﬁgured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 305: Interrupts
For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 306 Pulse-Width Modulator (S12PWM8B8CV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 307: Chapter 10 Serial Communication Interface (S12Sciv5)
MSB: Most Signiﬁcant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 308: Features
The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 309: Block Diagram
Transmit Control 1/16 Generation Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 10-1. SCI Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 310: External Signal Description
The total address for each register is the sum of the base address for the SCI module and the address offset for each register. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 311: Register Descriptions
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 10-2. SCI Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 312 Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 313 RXD pin. 0 Idle line wakeup 1 Address mark wakeup MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 314 Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 315 If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 316 Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt BKDIE requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 317 10-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 10-19) Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 318 SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 319 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 320 Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 321 RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 322 When transmitting in 9-bit data format and using 8-bit write instructions, write ﬁrst to SCI data register high (SCIDRH), then SCIDRL. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 323: Functional Description
Collision SCTXD Detect BERRIE R16XCLK BERRM[1:0] Infrared Transmit Ir_TXD Encoder R32XCLK TNP[1:0] IREN Figure 10-14. Detailed SCI Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 324: Infrared Interface Submodule
LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 325: Data Format
A frame with nine data bits has a total of 11 bits. Table 10-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 326: Baud Rate Generation
153,374.2 9585.9 9,600 76,687.1 4792.9 4,800 38,402.5 2400.2 2,400 1302 19,201.2 1200.1 1,200 2604 9600.6 600.0 5208 4800.0 300.0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 327: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 328 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 329 May set noise ﬂag NF, or receiver active ﬂag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 330 If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 331 The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ﬂag may be set incorrectly. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 332: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 333 Noise Flag If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 334 Table 10-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 335 Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 10-23. Start Bit Search Example 2 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 336 Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 10-25. Start Bit Search Example 4 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 337 The FE ﬂag is set at the same time that the RDRF ﬂag is set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 338 The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 339 The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 340: Single-Wire Operation
SCI. The SCI uses the TXD pin for both receiving and transmitting. Transmitter Receiver Figure 10-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 341: Loop Operation
Modes of Operation 10.5.2.1 Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 10.4.5.2, “Character Transmission”. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 342: Interrupt Operation
BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 343 IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 344: Recovery From Wait Mode
Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 345: Chapter 11 Serial Peripheral Interface (S12Spiv5)
Control of SPI operation during wait mode 11.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 346: Block Diagram
SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 347: External Signal Description
This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data when it is conﬁgured as master. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 348: Ss — Slave Select Pin
MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved 0x0007 Reserved = Unimplemented or Reserved Figure 11-2. SPI Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 349: Register Descriptions
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 350 Figure 11-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 351 Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 352 Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 353 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 354 SPIF Flag, please refer to Table 11-9. 0 Transfer not yet complete. 1 New data copied to SPIDR. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 355 SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 356 SPIDR (see Figure 11-10). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 357: Functional Description
SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 358: Master Mode
SPI is in idle state. 1. n depends on the selected transfer width, please refer to Section 11.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 359: Slave Mode
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 360: Transmission Formats
Figure 11-11. Master/Slave Transfer Block Diagram 1. n depends on the selected transfer width, please refer to Section 11.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 361 SPI. 1. n depends on the selected transfer width, please refer to Section 11.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 362 Figure 11-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 363 1. n depends on the selected transfer width, please refer to Section 11.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 364 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 11-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 365: Spi Baud Rate Generation
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 11-3. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 366: Special Features
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 367: Error Conditions
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 368: Low Power Mode Options
MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 369 This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing process which is described in Section 11.3.2.4, “SPI Status Register (SPISR)”. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 370 SPTEF has an automatic clearing process, which is described in Section 11.3.2.4, “SPI Status Register (SPISR)”. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 371: Chapter 12 Timer Module (Tim16B8Cv3)
Up to 8 channels available. (refer to device speciﬁcation for exact number) • All channels have same input capture/output compare functionality. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 372: Modes Of Operation
Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 373: Block Diagrams
Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 12-1. TIM16B8CV3 Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 374 Figure 12-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 12-3. Interrupt Flag Setting MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 375: External Signal Description
The total address for each register is the sum of the base address for the TIM16B8CV3 module and the address offset for each register. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 376: Register Descriptions
EDG0A TCTL4 0x000C 0x000D TCRE TSCR2 = Unimplemented or Reserved Figure 12-5. TIM16B8CV3 Register Summary (Sheet 1 of 2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 377 The related bit is available only if corresponding channel exists The register is available only if channel 7 exists. The register is available only if corresponding channel exists. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 378 Figure 12-7. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 379 Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to be transferred from the output compare 7 data register to the timer port. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 380 A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 381 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 382 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 383 Toggle OCx output line Clear OCx output line to zero Set OCx output line to one MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 384 Module Base + 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset Figure 12-17. Timer Control Register 4 (TCTL4) Read: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 385 TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set, the corresponding ﬂag is enabled to cause a interrupt. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 386 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 387 TEN bit of TSCR1 or PAEN bit of PACTL is set to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 388 Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 389 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 390 This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 391 Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 392 PTPS0 Reset Figure 12-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 393: Functional Description
This section provides a complete functional description of the timer TIM16B8CV3 block. Please refer to the detailed timer block diagram in Figure 12-30 as necessary. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 394 Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 12-30. Detailed Timer Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 395: Prescaler
A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 396: Pulse Accumulator
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two bus clocks. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 397: Event Counter Mode
This section describes interrupts originated by the TIM16B8CV3 block. Table 12-25 lists the interrupts generated by the TIM16B8CV3 to communicate with the MCU. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 398: Channel [7:0] Interrupt (C[7:0]F)
This active high output will be asserted by the module to request a timer overﬂow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 399: Chapter 13 High-Side Drivers - Hsdrv (S12Hsdrv1)
High-load resistance open-load detection when driver enabled and turned off. • Over-current protection for the drivers, while they are enabled, including: – Interrupt flag generation. – Driver shutdown. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 400: Modes Of Operation
Figure 13-1. HSDRV Block Diagram HS0 Open Load HS0 control HS0 Over Current VSUPHS HS1 Over Current HS1 control HS1 Open Load MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 401: External Signal Description
A summary of registers associated with the HSDRV module is shown in Table 13-3. Detailed descriptions of the registers and bits are given in the following sections. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 402 Reserved Reserved Reserved Reserved Reserved Reserved 0x0004 Reserved HSOL1 HSOL0 0x0005 HSSR 0x0006 HSOCIE HSIE 0x0007 HSOCIF1 HSOCIF0 HSIF MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 403: Register Deﬁnition
After enabling the high-side driver with the HSEx bit in HSCR register, the user must wait a minimum settling time t HS_settling before turning on the high-side driver gate. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 404: Hsdrv Conﬁguration Register (Hscr)
HS_settling allowed to be turned on (e.g. by writing HSDRx bits). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 405: Reserved Register
Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 406: Hsdrv Status Register (Hssr)
HSDRV Over-Current Interrupt Enable HSOCIE 0 Interrupt request is disabled 1Interrupt will be requested whenever a HSOCIFx ﬂag is set MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 407 Once these ﬂags are cleared, the related gate is again driven by the source selected in PIM module. 0No over-current event occurred since last clearing of ﬂag 1An over-current event occurred since last clearing of ﬂag MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 408: Hsdrv Interrupt Flag Register (Hsif)
The HSDRV interrupt vector is named in Table 13-10. Vector addresses and interrupt priorities are deﬁned at MCU level. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 409: Interrupts
Controlling directly the High Side Driver 13.5.1.2 Using the High Side Driver with a timer 13.5.1.3 Using the High Side Driver with PWM MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 410 High-Side Drivers - HSDRV (S12HSDRV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 411: Chapter 14 Low-Side Drivers - Lsdrv (S12Lsdrv1)
Open-load detection while enabled – While driver off: selectable high-load resistance open-load detection • Over-current protection with shutdown and interrupt while enabled MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 412: Modes Of Operation
Internal functions can be routed to control the low-side drivers. See PIM chapter for routing options. Figure 14-1. LSDRV Block Diagram LS0 control LSGND LS1 control MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 413: External Signal Description
LSDR1 LSDR0 LSDR 0x0001 LSOLE1 LSOLE0 LSE1 LSE0 LSCR 0x0002 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 414 Reserved Reserved Reserved Reserved Reserved Reserved 0x0004 Reserved LSOL1 LSOL0 0x0005 LSSR 0x0006 LSOCIE LSIE 0x0007 LSOCIF1 LSOCIF0 LSIF MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 415: Register Deﬁnition
OC=0 or PWM=0) and the load should be de-energized before going into Stop Mode or disabling the low-side driver with the LSEx bits. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 416: Lsdrv Conﬁguration Register (Lscr)
LS_settling allowed to be turned on (e.g. by writing LSDRx bits). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 417: General
Threshold trimming for both LS1 and LS0 over-current comparators. The trimming is coded representing an one-hot coding 0 -> “0001”, 1 -> “0010”, 2-> “0100” and 3 -> “1000”. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 418: Reserved Register
These bits show the over-current status of each driver. These bits are useful only with the over-current shutdown disabled. 0 No over-current condition 1 over-current condition MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 419: Lsdrv Status Register (Lssr)
< I 0 Open-load condition I HLROLDC ≥ I 1 Open-load condition I HLROLDC MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 420: Lsdrv Interrupt Enable Register (Lsie)
LSDRV Error Interrupt Enable LSOCIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LSOCIFx ﬂag is set MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 421: Lsdrv Interrupt Flag Register (Lsif)
Once these ﬂags are cleared, the related gate is again driven by the source selected in PIM module. 0 No over-current event occurred since last clearing of ﬂag 1 An over-current event occurred since last clearing of ﬂag MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 422: Open Load Detection
The LSDRV interrupt vector is named in Table 14-11. Vector addresses and interrupt priorities are deﬁned at MCU level. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 423: Application Information
Controlling directly the Low Side Driver 14.5.1.2 Using the Low Side Driver with a timer 14.5.1.3 Using the Low Side Driver with PWM MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 424 Low-Side Drivers - LSDRV (S12LSDRV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 425: Chapter 15 Lin Physical Layer (S12Linphyv1)
VSUP and the resistor. The fall time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions.. The symmetry between both slopes is guaranteed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 426: Modes Of Operation
LIN Physical Layer. The module consists of a receiver, a transmitter with slope control, a temperature and a current sensor as well as a control block. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 427 ADC (special channel) NOTE The external 220pF capacitance between LIN and LGND is strongly recommended for correct operation. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 428: External Signal Description
ﬁlter noise. 15.2.3 VSUP — Positive Power Supply External power supply to the chip.See device speciﬁcation. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 429: Memory Map And Register Deﬁnition
0x0004 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPOC 0x0005 LPSR 0x0006 LPOCIE LPIE 0x0007 LPOCIF LPIF MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 430: Register Descriptions
Port LP Data Bit 0 LPDR0 Read-only bit. The LIN Physical Layer LPRXD output state can be read at any time. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 431 0 The pull-up resistor is high ohmic 30kΩ). 1 If LPE=1, the pull-up resistor is the one speciﬁed in the LIN speciﬁcation ( MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 432 LPSLR0 Reset = Unimplemented Figure 15-5. LIN Slew Rate Register (LPSLR) Read: Anytime Write: Only when LPSLRWD is 0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 433 Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 434 (if any) lost. 0 No LIN over-current condition. 1 An over-current condition is occurring. The LIN transmitter is disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 435 LIN Over-current Interrupt Enable LPOCIE 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LPOCIF bit is set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 436: Functional Description
TXD. If the slew rate is changed less than 2us before a falling edge of TXD, the slew rate change may be effective only at the second next TXD falling edge. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 437: Modes
15.4.3 Modes Figure 15-10 shows the possible mode transitions depending on control bits, stop mode and error conditions. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 438 Setting LPE at 0 makes the module leave the Normal or Receive Only Modes and go back to Shutdown Mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 439 Since the wake-up interrupt is requested by the SCI, no wake-up feature is available if the SCI is not used. (For example when using with a timer for bit banging) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 440: Interrupts
OCLIM MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 441: Use Cases
Use Cases 15.5.2.1 LIN Physical Layer standalone 15.5.2.2 LIN Physical Layer with SCI 15.5.2.3 LIN Physical Layer with Timer MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 442 LIN Physical Layer (S12LINPHYV1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 443: Chapter 16 Supply Voltage Sensor - (Batsv2)
During stop mode operation the path from the VSENSE pin through the resistor chain to ground is opened and the low voltage sense features are disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 444: Block Diagram
This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 445: Vsup — Voltage Supply Pin
This section provides the detailed information of all registers for the BATS module. 16.3.1 Register Summary Figure 16-2 shows the summary of all implemented registers inside the BATS module. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 446: Register Descriptions
ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 447 Voltage Level Sense features measuring BVLC and BVHC.Setting this bit will clear bit BSUSE 0 Level Sense features disabled 1 Level Sense features enabled NOTE MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 448 This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 449 (falling edge) or V (rising edge) measured LBI_A measured LBI_D Figure 16-5. BATS Voltage Sensing HBI_A HBI_D LBI_D LBI_A MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 450 BVLIF Reset = Unimplemented Figure 16-7. BATS Interrupt Flag Register (BATIF) Read: Anytime Write: Anytime, write 1 to clear MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 451: Functional Description
(BSESE=1, BVHIE=1), while the VSUP pin voltage is routed to the ATD to allow regular measurement (BSUAE=1). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 452: Vlbi1_A
BVLC is set. BVLC status bit indicates that a low voltage at the selected pin is present. The Low Voltage Interrupt ﬂag (BVLIF) is set to 1 when the Voltage Low Condition (BVLC) changes state . The MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 453 Interrupt ﬂag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 454 Supply Voltage Sensor - (BATSV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 455 Supply Voltage Sensor - (BATSV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 456 Supply Voltage Sensor - (BATSV2) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 457: Chapter 17 64 Kbyte Flash Module (S12Ftmrg64K512V1)
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 458: Features
Protection scheme to prevent accidental program or erase of EEPROM memory • Ability to program up to four words in a burst sequence MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 459: Block Diagram
Clock Clock Divider FCLK Memory Controller EEPROM 256x22 sector 0 sector 1 sector 127 Figure 17-1. FTMRG64K512 Block Diagram MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 460: External Signal Description
The S12 architecture places the P-Flash memory between global addresses 0x3_0000 and 0x3_FFFF as shown in Table 17-2.The P-Flash memory map is shown in Figure 17-2. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 461 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved ﬁeld should be programmed to 0xFF. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 462 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 Flash Conﬁguration Field P-Flash END = 0x3_FFFF 16 bytes (0x3_FF00 - 0x3_FF0F) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 463 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 17.4.3 for NVMRES (NVM Resource) detail. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 464: Register Descriptions
KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX Figure 17-3. FTMRG64K512 Register Summary MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 465 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT Figure 17-3. FTMRG64K512 Register Summary (continued) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 466 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 467 17.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 468 Table 17-10. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED Preferred SEC state to set MCU to secured state. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 469 Flash Conﬁguration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 470 17.3.2.6) 17.3.2.6 Flash Error Conﬁguration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 471 CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 472 Figure 17-11. Flash Error Status Register (FERSTAT) All ﬂags in the FERSTAT register are readable and only writable to clear the ﬂag. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 473 FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 474 Table 17-18. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 0x3_F800–0x3_FFFF 2 Kbytes 0x3_F000–0x3_FFFF 4 Kbytes 0x3_E000–0x3_FFFF 8 Kbytes 0x3_C000–0x3_FFFF 16 Kbytes MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 475 Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 476 The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 477 Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 478 17-3) as indicated by reset condition F in . To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 479 The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 480 FCMD[7:0] deﬁning Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] Data 0 [15:8] Data 0 [7:0] MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 481 All bits in the FRSV2 register read 0 and are not writable. 17.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 482 17-20. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 483 All bits in the FRSV6 register read 0 and are not writable. 17.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 484: Functional Description
The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are deﬁned in Table 17-25. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 485: Internal Nvm Resource (Nvmres)
17.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 486 CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic command write sequence is shown in Figure 17-25. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 487 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 17-25. Generic Flash Command Write Sequence Flowchart MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 488 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. Secured Normal Single Chip mode. Secured Special Single Chip mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 489 Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 490: Allowed Simultaneous P-Flash And Eeprom Operations
‘normal’ level speciﬁed. See the Note on margin settings in Section 17.4.6.12 Section 17.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 491: Flash Command Description
Set if any errors have been encountered during the reador if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 492 Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 493 Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 494 The CCIF ﬂag will set after the Program P-Flash operation has completed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 495 Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 496 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 497 Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash Sector operation has completed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 498 17-9). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 499 Table 17-52. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Global address [17:16] to identify the 0x0D Flash block Margin level setting MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 500 If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 501 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 502 EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 503 Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF ﬂag is set when the operation has completed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 504 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 505: Interrupts
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 17.4.7, “Interrupts”). MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 506: Stop Mode
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 507: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 17-26. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 508: Initialization
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 509: A.1 General
All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 510: A.1.2 Pins
TEST This pin is used for production testing only. The TEST pin must be tied to ground in all applications. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 511: A.1.3 Current Injection
This device contains circuitry protecting against damage due to high static voltage or electrical ﬁelds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 512 EXTAL and XTAL are shared with PE0 and PE1 5V GPIO’s All digital I/O pins are internally clamped to V and V , or V and V MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 513: A.1.5 Esd Protection And Latch-Up Immunity
Direct Contact Discharge IEC61000-4-2 with and with out 220pF capacitor (R=330, C=150pF): +/-6 ESDIEC LIN vs LGND MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 514 °C LIN at T=125 positive +100 negative -100 For robustness of HVI[3:0], VSUP & VSUPHS pins refer to TBD MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 515: A.1.6 Operating Conditions
Θ Junction Temperature, [°C ] Ambient Temperature, [°C ] Total Chip Power Dissipation, [W] Θ Package Thermal Resistance, [°C/W] MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 516 GPIO and ground. GPIO This power component is included in P is subtracted from overall MCU power dissipa- tion P MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 517 VBAT LS[1:0] VSENSE VSUP SUPHS VSUPHS PHS0/1 VDDA HS[1:0] VDDX1 VDDX2 Switch HVI[3:0] Inputs VSSX1 GPIO VSSX2 EVDD EVDD MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 518 JEDEC speciﬁcation JESD51-7 in a horizontal conﬁguration in natural convection. 1. The values for thermal resistance are achieved by package simulations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 519: A.1.8 I/O Characteristics
— — T Injection current — Single pin limit –2.5 Total device Limit, sum of all injected currents –25 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 520: A.1.9 Supply Currents
PLLSEL=1 OSCE=0, CPMUOSC Reference clock for PLL is f trimmed to 1MHz irc1m API settings for STOP current measurement MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 521 Conditions are: V =18V, T =105°C, see Table A-10 Table A-9 SUPHS Rating Symbol Unit Run Current SUPR Wait Current SUPW MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 522 Conditions are: V =12V, API see Table A-9., COP & RTI enabled SUPHS Rating Symbol Unit µA = 25°C SUPPS MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 523: Appendix B
MCU will stay out of reset. Please note that the core current is derived from VDDX further limitation may apply due to maximum allowable T MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 524 (e.g. code execution) of the microcontroller, the LVR triggers. All values are subject to change after silicon evaluation. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 525: C.1 Atd Operating Characteristics
Source resistance, source capacitance and current injection have an inﬂuence on the accuracy of the ATD. A further factor is that PortAD pins that are conﬁgured as output drivers switching. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 526: C.2.1 Port Ad Output Drivers Switching
= K * R with I being the sum of the currents injected into the two pins adjacent to the converted channel. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 527: C.3 Atd Accuracy
The integral non-linearity (INL) is deﬁned as the sum of all DNLs: ∑ – INL n ( ) DNL i ( ) -------------------- - n – 1LSB MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 528 Figure A-1 shows only deﬁnitions, for speciﬁcation values refer to Table A-3 and Table A-4. Table C-3. ATD Conversion Performance 5V range MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 529 C Differential Nonlinearity 8-Bit -0.5 counts ±0.5 C Integral Nonlinearity 8-Bit counts ±1 C Absolute Error 8-Bit -1.5 counts MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 530 ATD Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 531: D.1 Operating Characteristics
Nominal Current for continuous operation. – – NOMHSX This value is valid for each HS-driver output. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 532: D.3 Dynamic Characteristics
Settling time after the high-side driver is enabled (write – HS_settling HSEx Bits) : Junction Temperature : Ambient Temperature MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 533: E.1 Reset, Oscillator And Pll
---------------------- - – ---------------------- - ⋅ ⋅ ⎝ ⎠ The following equation is a good ﬁt for the maximum jitter: MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 534 C Time to lock lock 256/f C Jitter ﬁt parameter 1 % deviation from target frequency = 1MHz, f = 25MHz MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 535: Appendix F
Rating Symbol Unit Junction Temperature - 40 to 150 Celsius 0.987 1.013 MHz IRC1M_TRIM Internal Reference Frequency, factory trimmed MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 536 IRC Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 537: G.1 Maximum Ratings
VDDX = 5V, VDDA = 5V, VDD = 1.8V, Tj = 25 C) µA on chip VSUP µA on VDDX µA on VDDA µA on VDD MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 538: G.3 Dynamic Electrical Characteristics
Rising/falling edge time (min to max / max to min) rise µs Over-current masking window (IRC trimmed at 1MHz) OCLIM MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 539 Over-current masking window (IRC trimmed at 1MHz) OCLIM For 3.5V<=VSUP<7V, the LINPHY is still working but with degraded parametrics. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 540 LINPHY Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 541: H.1 Static Characteristics
(if low-side driver is enabled and gate turned off) µA Leakage Current -40˚C < T < 80˚C – – LEAK_L µA Open Load Detection disabled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 542: H.2 Dynamic Characteristics
Low-Side Driver Operating Frequency – – Inductive Load on each LS-driver output – – PLS0/1 : Junction Temperature : Ambient Temperature MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 543: I.1 Maximum Ratings
Ratings Symbol Unit VSENSE Max Rating – VSENSE_M : Junction Temperature : Ambient Temperature MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 544: I.2 Static Electrical Characteristics
Absolute Error on V - compared to V / Ratio SENSE VSENSE - compared to V / Ratio VSUP MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 545: I.3 Dynamic Electrical Characteristics
The information given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Freescale and are subject to change without notice. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 546 BATS Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 547: J.1 High-Voltage Inputs (Hvi) Electrical Characteristics
Note: Always required externally at HVI pins. µs Enable Uncertainty Time – – UNC_HVI : Junction Temperature : Ambient Temperature Pin Interrupt Characteristics MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 548 1/f : Junction Temperature Parameter only applies in stop or pseudo stop mode. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 549: K.1 Timing
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure K-1. SPI Master Timing (CPHA=0) In Figure K-2. the timing diagram for master mode with transmission format CPHA=1 is depicted. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 550 Rise and Fall Time Inputs — — rﬁ Rise and Fall Time Outputs — — pls. see Figure K-3. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 551: K.1.2 Slave Mode
, please see Figure K-3.. K.1.2 Slave Mode In Figure K-3. the timing diagram for slave mode with transmission format CPHA=0 is depicted. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 552 MSB IN BIT 6 . . . 1 LSB IN (INPUT) NOTE: Not defined! Figure K-5. SPI Slave Timing (CPHA=1) MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 553 Rise and Fall Time Inputs — — rﬁ Rise and Fall Time Outputs — — 0.5t added due to internal synchronization delay MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 554 SPI Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 555: Appendix L Xosclcp Electrical Specifications
These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements. Needs to be measured at room temperature on the application board using a probe with very low (<=5pF) input capacitance. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 556 XOSCLCP Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 557: M.1 Timing Parameters
Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: for 64 Kbyte P-Flash (FMTRG64K512) ⋅ 16700 -------------------- - pcheck NVMBUS MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 558: M.1.3 Erase Verify P-Flash Section (Fcmd=0X03)
The time required to erase all blocks is given by: for 64 Kbyte P-Flash and 512byte D-Flash (FTMRG64K512) ≈ ⋅ ----------------- - 17500 -------------------- - mass NVMOP NVMBUS MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 559: M.1.8 Erase P-Flash Block (Fcmd=0X09)
Verify Backdoor Access Key (FCMD=0x0C) The maximum verify backdoor access key time is given by: ⋅ -------------------- - NVMBUS MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 560: M.1.12 Set User Margin Level (Fcmd=0X0D)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given ≈ ⋅ ⋅ 5025 -------------------- - ----------------- - dera NVMBUS NVMOP MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 561 NVMOP The D-Flash sector erase time is ~5ms on a new device and can extend to ~20ms as the ﬂash is cycled. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 562 The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table M-2 are preliminary and subject to further characterization. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 563 For additional information on how Freescale deﬁnes Typical Data Retention, please refer to Engineering Bulletin EB618. MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com...
Page 564 FTMRG Electrical Speciﬁcations MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 565: Appendix N Package Information
Package Information Appendix N Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 566 Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 567 Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 568 Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 569 Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 570 Package Information MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 571: Appendix O Detailed Register Address Map
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000A Reserved 0x000B MODE MODC MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 572 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0018 Reserved 0x0019 Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 573 Bit 2 Bit 1 Bit 0 0x0025 DBGTBL 0x0026 DBGCNT 0x0027 DBGSCRX 0x0027 DBGMFR 0x0028 DBGACTL COMPE 0x0028 DBGBCTL COMPE MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 574 VCOFRQ[1:0] SYNDIV[5:0] 0x0035 CPMUREFDIV REFFRQ[1:0] REFDIV[3:0] CPMUPOSTDI 0x0036 POSTDIV[4:0] LOCK UPOSC 0x0037 CPMUFLG RTIF PORF LVRF LOCKIF ILAF OSCIF MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 575 TOV1 TOV0 0x0048 Reserved 0x0049 TCTL2 0x004A Reserved 0x004B TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0x004C MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 576 0x0071 ATDCTL1 SRES1 SRES0 SMP_DIS 0x0072 ATDCTL2 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE 0x0073 ATDCTL3 FIFO FRZ1 FRZ0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 577 Bit6 0x0085 ATDDR2L Bit15 Bit8 0x0086 ATDDR3H Bit7 Bit6 0x0087 ATDDR3L Bit15 Bit8 0x0088 ATDDR4H Bit7 Bit6 0x0089 ATDDR4L MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 578 PWMCNT1 Bit 7 Bit 0 0x00AE PWMCNT2 Bit 7 Bit 0 0x00AF PWMCNT3 Bit 7 Bit 0 0x00B0 PWMCNT4 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 579 Bit 7 Bit 0 0x00C2 PWMDTY6 Bit 7 Bit 0 0x00C3 PWMDTY7 Bit 7 Bit 0 0x00C4- Reserved 0x00C7 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 580 0x00D1 SCI1ACR1 RXEDGIE BERRIE BKDIE 0x00D2 SCI1ACR2 BERRM1 BERRM0 BKDFE 0x00D3 SCI1CR2 TCIE ILIE TDRE RDRF IDLE 0x00D4 SCI1SR1 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 581 FCLKDIV FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0101 FSEC MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 582 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0114- Reserved 0x011F MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 583 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0148- Reserved 0x014F MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 584 LPDR0 0x0160 LPDR LPDR1 0x0161 LPCR RXONLY LPWUE LPPUE 0x0162 Reserved R LPSLRWD 0x0163 LPSLR LPSLR1 LPSLR0 0x0164 Reserved MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 585 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0178- Reserved 0x023F MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 586 PPST PPST3 PPST2 PPST1 PPST0 0x0246 PTTRR0 PTTRR07 PTTRR06 PTTRR05 PTTRR04 PTTRR03 PTTRR02 PTTRR01 PTTRR00 0x0247 PTTRR1 PTTRR15 PTTRR14 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 587 PPSS0 0x025E PIEP OCIE PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0x025F PIFP OCIF PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 588 Reserved 0x027D PIE1AD PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 0x027E Reserved 0x027A PIF1AD PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 589 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0300- Reserved 0x03FF MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 590 Detailed Register Address Map MC9S12VR Family Reference Manual, Rev. 2.2 Freescale Semiconductor Preliminary - Subject to Change Without Notice Downloaded from Elcodis.com electronic components distributor...
Page 591 Downloaded from Elcodis.com electronic components distributor...
Page 592 “Typicals” must be validated for each customer application by customer’s technical experts. Asia/Paciﬁc: Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor H.K. Ltd. Freescale Semiconductor products are not designed, intended, or authorized for use as components...

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Mc9s12vr48 Mc9s12vr64

Freescale Semiconductor MC9S12VR Series Reference Manual

Chapter 1 Device Overview MC9S12VR-Family

Port Integration Module (S12VRPIMV2

Chapter 2 Port Integration Module (S12VRPIMV2)

S12G Memory Map Controller (S12GMMCV1

Chapter 3 S12G Memory Map Controller (S12GMMCV1)

Chapter 4 Clock, Reset and Power Management (S12CPMU_UHV)

Chapter 5 Background Debug Module (S12SBDMV1)

Chapter 6 S12S Debug Module (S12SDBGV2)

Chapter 7 Interrupt Module (S12SINTV1)

Chapter 8 Analog-To-Digital Converter (ADC12B6CV2)

Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2)

Chapter 10 Serial Communication Interface (S12SCIV5)

Chapter 11 Serial Peripheral Interface (S12SPIV5)

Chapter 12 Timer Module (TIM16B8CV3)

Chapter 13 High-Side Drivers - HSDRV (S12HSDRV1)

Chapter 14 Low-Side Drivers - LSDRV (S12LSDRV1)

Chapter 15 LIN Physical Layer (S12LINPHYV1)

Chapter 16 Supply Voltage Sensor - (BATSV2)

Chapter 17 64 Kbyte Flash Module (S12FTMRG64K512V1)

Appendix A

Appendix B

Appendix C C.2.1 Port AD Output Drivers Switching

Appendix D Appendix F

Appendix G

Appendix H

Appendix I K.1.2 Slave Mode

Appendix L XOSCLCP Electrical Specifications

Appendix M

Appendix N Package Information

Appendix O Detailed Register Address Map

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Summary of Contents for Freescale Semiconductor MC9S12VR Series