Introduction; Mclk Generation; Reset Generation; Power Options - Texas Instruments DSP-Codec User Manual

Introduction

3.1 Introduction
3.1.1

MCLK Generation

Table 3-1. Jumper W2 Function
3.1.2

Reset Generation

3.1.3

Power Options

Table 3-2. Jumper W1 Function
3-2
The development platform supports a number of functions required by the
codecs:
-
MCLK generation
-
Reset generation
-
Power options
Alternatives for each function are described below.
MCLK is the clock required by the Sigma Delta converter. All other timing is
derived from MCLK. The DSK provides a clock that can be used as MCLK for
the codecs. Alternatively, a 100 MHz clock is available on the development
platform. Jumper W2 selects the clock source.
Position Function
1-2 DSP Clock is selected
2-3 100 MHz clock from development platform is selected
Reset may be generated by either the DSK via software, or manually by
momentarily pressing SW1. Either of these options is valid and generates a
RESET signal that is asynchronous to MCLK.
System power may be supplied from either the DSK via connector J2, or an
external source via connector J1. If an external source is used to supply
system power, switch the position of jumper W1.
Position W1 Function
1-2 3.3 V is supplied via the DSK
2-3 3.3 V is supplied via the J1 screw terminals