SMART Embedded Computing COMX-P2020 BSP User Manual page 63

PCIE3 connected to Slot0 as Root Complex (base addr ffe08000)
Current Status: LSR-11, LTSSM-16, PEX width-x1, Clock-2.5GT/s
PCIE3 on bus 00 - 01
PCIE2 connected to Slot 1 as Root Complex (base addr ffe09000)
PCIE2 on bus 02 - 02
PCIE1 connected to Slot 2 as Root Complex (base addr ffe0a000)
Current Status: LSR-11, LTSSM-16, PEX width-x1, Clock-2.5GT/s
PCIE1 on bus 03 - 04
The U-boot provides standard command "pci" to probe and configure PCI Express devices.
This part is not included in this document.
=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId
_____________________________________________________________
00.00.00
=> help pci
pci - list and access PCI Configuration Space
Usage:
pci [bus] [long]
- short or long list of PCI devices on bus 'bus'
pci header b.d.f
- show header of PCI device 'bus.device.function'
pci display[.b, .w, .l] b.d.f [address] [# of objects]
- display PCI configuration space (CFG)
pci next[.b, .w, .l] b.d.f address
- modify, read and keep CFG address
pci modify[.b, .w, .l] b.d.f address
- modify, auto increment CFG address
pci write[.b, .w, .l] b.d.f address value
- write to CFG address
COMX-P2020 BSP User Guide (6806800L84C)
Scanning PCI bus 01
01 00 8086 107d 0200
Scanning PCI bus 04
04 00 18ca 0027 0300
DeviceId
0x1957 0x0070
00
00
Device Class
Processor
U-boot Deployment
Sub-Class
0x20
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