Table of Contents
Advertisement
www.ti.com
3.6
Interrupt Pending/Set Register (INTPENDSET)
The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the
INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the
serial interface, these bits are cleared. The INTPENDSET is shown in
Table
11.
31
LEGEND: R/W = Read/Write; -n = value after reset
Table 11. Interrupt Pending/Set Register (INTPENDSET) Field Descriptions
Bit
Field
Value
31-0
INTSET
0-FFFF FFFFh
3.7
Interrupt Pointer Register (INTPTR)
The interrupt pointer register (INTPTR) typically contains the address of the interrupt pending/set register
(INTPENDSET) within the VLYNQ module. To program INTPTR to point to INTPENDSET, program a
value of 14h (the offset of INTPENDSET). Additionally, the INT2CFG bit in the control register (CTRL)
should be set to 1. The INTPTR is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
Value
31-2
INTPTR
0-3FFF FFFFh
1-0
Reserved
SPRU938B – September 2007
Submit Documentation Feedback
Figure 14. Interrupt Pending/Set Register (INTPENDSET)
Description
This field indicates the unmasked status of each pending interrupt.
0
Writing a 0 has no effect.
1
Writing a 1 to any bit:
if INTLOCAL = 0 in CTRL, interrupt packet is sent on the serial interface.
If INTLOCAL = 1 in CTRL, VLYNQ module interrupt (VLQINT) is asserted.
Figure 15. Interrupt Pointer Register (INTPTR)
INTPTR
R/W-0
Table 12. Interrupt Pointer Register (INTPTR) Field Descriptions
Description
Interrupt pointer. Program this register with the address (14h) of the interrupt pending/set
register (INTPENDSET).
0
Reserved. Always read as 0. Writes have no effect.
INTSET
R/W-0
Figure 15
and described in
VLYNQ Port Registers
Figure 14
and described in
Table
12.
2
VLYNQ Port
0
1
0
Reserved
R-0
31
Advertisement
Table of Contents
