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Peripheral Architecture
2.5
VLYNQ Functional Description
The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is
symmetrical. The VLYNQ module structure is shown in
Slave
Address
config bus
translation
interface
Registers
Master
Address
config bus
translation
interface
The VLYNQ core module implements two 32-bit configuration bus interfaces. Transmit operations and
control register access require the slave configuration bus interface. The master configuration bus
interface is required for receive operations. Converting to and from the 32-bit bus to the external serial
interface requires serializer and deserializer blocks.
8b/10b block coding encodes data on the serial interface. Frame delineation, initialization, and flow control
use special overhead code groups.
FIFOs buffer the entire burst on the bus for maximum performance, thus minimizing bus latency. Using
write operations of each VLYNQ module interfaced is typically recommended to ensure the best
performance on both directions of the link.
12
VLYNQ Port
Figure 4. VLYNQ Module Structure
System clock
Outbound
Outbound
command
commands
FIFO
(FIFO3)
Return
data
FIFO
(FIFO2)
Return
data
FIFO
(FIFO0)
Inbound
Inbound
command
commands
FIFO
(FIFO1)
Figure
4.
VLYNQ clock
TxSM
RxSM
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8B/10B
Serializer
encoding
8B/10B
Deserializer
decoding
SPRU938B – September 2007
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Serial
TxData
Serial
TxClk
Serial
RxClk
Serial
RxData
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