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VLYNQ Port
Texas Instruments VLYNQ Port Manuals
Manuals and User Guides for Texas Instruments VLYNQ Port. We have
1
Texas Instruments VLYNQ Port manual available for free PDF download: User Manual
Texas Instruments VLYNQ Port User Manual (49 pages)
Texas Instruments VLYNQ Port User's Guide
Brand:
Texas Instruments
| Category:
Network Card
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
7
Read this First
7
1 Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
10
Industry Standard(S) Compliance Statement
10
VLYNQ Port Functional Block Diagram
10
2 Peripheral Architecture
11
Clock Control
11
External Clock Block Diagram
11
Internal Clock Block Diagram
11
Signal Descriptions
12
Pin Multiplexing
12
Protocol Description
12
VLYNQ Port Pins
12
VLYNQ Functional Description
13
VLYNQ Module Structure
13
Write Operations
14
Read Operations
15
Initialization
16
Auto-Negotiation
16
Serial Interface Width Configuration
16
Serial Interface Width
16
Address Translation
17
Example Address Memory Map
18
Address Translation Example (Single Mapped Region)
18
Address Translation Example (Single Mapped Region)
19
2.10 Flow Control
20
2.11 Reset Considerations
21
2.12 Interrupt Support
21
Interrupt Generation Mechanism Block Diagram
22
2.13 DMA Event Support
23
2.14 Power Management
24
2.15 Emulation Considerations
24
3 VLYNQ Port Registers
25
VLYNQ Register Address Space
25
VLYNQ Port Controller Registers
25
Revision Register (REVID)
26
Revision Register (REVID) Field Descriptions
26
Control Register (CTRL)
27
Control Register (CTRL) Field Descriptions
27
Status Register (STAT)
29
Status Register (STAT) Field Descriptions
29
Interrupt Priority Vector Status/Clear Register (INTPRI)
31
Interrupt Status/Clear Register (INTSTATCLR)
31
Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions
31
Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions
31
Interrupt Pending/Set Register (INTPENDSET)
32
Interrupt Pointer Register (INTPTR)
32
Interrupt Pending/Set Register (INTPENDSET) Field Descriptions
32
Interrupt Pointer Register (INTPTR) Field Descriptions
32
Transmit Address Map Register (XAM)
33
Address Map Register (XAM) Field Descriptions
33
Receive Address Map Size 1 Register (RAMS1)
34
Receive Address Map Offset 1 Register (RAMO1)
34
Receive Address Map Size 1 Register (RAMS1) Field Descriptions
34
Receive Address Map Offset 1 Register (RAMO1) Field Descriptions
34
Receive Address Map Size 2 Register (RAMS2)
35
Receive Address Map Offset 2 Register (RAMO2)
35
Receive Address Map Size 2 Register (RAMS2) Field Descriptions
35
Receive Address Map Offset 2 Register (RAMO2) Field Descriptions
35
Receive Address Map Size 3 Register (RAMS3)
36
Receive Address Map Offset 3 Register (RAMO3)
36
Receive Address Map Size 3 Register (RAMS3) Field Descriptions
36
Receive Address Map Offset 3 Register (RAMO3) Field Descriptions
36
Receive Address Map Size 4 Register (RAMS4)
37
Receive Address Map Offset 4 Register (RAMO4)
37
Receive Address Map Size 4 Register (RAMS4) Field Descriptions
37
Receive Address Map Offset 4 Register (RAMO4) Field Descriptions
37
Chip Version Register (CHIPVER)
38
Auto Negotiation Register (AUTNGO)
38
Chip Version Register (CHIPVER) Field Descriptions
38
Auto Negotiation Register (AUTNGO) Field Descriptions
38
4 Remote Configuration Registers
39
VLYNQ Port Remote Controller Registers
39
SPRUE36A – September
40
Appendix A VLYNQ Protocol Specifications
40
Special 8B/10B Code Groups
40
Supported Ordered Sets
40
Packet Format (10-Bit Symbol Representation)
41
Packet Format (10-Bit Symbol Representation) Description
42
Appendix B Write/Read Performance
45
Scaling Factors
46
Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
46
Relative Performance with Various Latencies
47
Appendix C Revision History
48
Document Revision History
48
Important Notice
49
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