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SPRU938B
Texas Instruments SPRU938B Manuals
Manuals and User Guides for Texas Instruments SPRU938B. We have
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Texas Instruments SPRU938B manual available for free PDF download: User Manual
Texas Instruments SPRU938B User Manual (48 pages)
Texas Instruments VLYNQ Port User's Guide
Brand:
Texas Instruments
| Category:
Network Card
| Size: 0.39 MB
Table of Contents
Table of Contents
3
Preface
7
1 Introduction
8
Purpose of the Peripheral
8
Features
8
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
9
VLYNQ Port Functional Block Diagram
9
2 Peripheral Architecture
10
Clock Control
10
External Clock Block Diagram
10
Internal Clock Block Diagram
10
Signal Descriptions
11
Pin Multiplexing
11
Protocol Description
11
VLYNQ Signal Descriptions
11
VLYNQ Functional Description
12
VLYNQ Module Structure
12
Write Operations
13
Read Operations
14
Initialization
15
Auto-Negotiation
15
Address Translation
16
Example Address Memory Map
17
Address Translation Example (Single Mapped Region)
17
Address Translation Example (Single Mapped Region)
18
Flow Control
19
2.10 Reset Considerations
20
2.11 Interrupt Support
20
Interrupt Generation Mechanism Block Diagram
21
2.12 EDMA Event Support
22
2.13 Power Management
23
2.14 Endianness Considerations
23
2.15 Emulation Considerations
23
3 VLYNQ Port Registers
24
VLYNQ Register Address Space
24
VLYNQ Port Controller Registers
24
Revision Register (REVID)
25
Revision Register (REVID) Field Descriptions
25
Control Register (CTRL)
26
Control Register (CTRL) Field Descriptions
26
Status Register (STAT)
28
Status Register (STAT) Field Descriptions
28
Interrupt Priority Vector Status/Clear Register (INTPRI)
30
Interrupt Status/Clear Register (INTSTATCLR)
30
Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions
30
Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions
30
Interrupt Pending/Set Register (INTPENDSET)
31
Interrupt Pointer Register (INTPTR)
31
Interrupt Pending/Set Register (INTPENDSET) Field Descriptions
31
Interrupt Pointer Register (INTPTR) Field Descriptions
31
Transmit Address Map Register (XAM)
32
Address Map Register (XAM) Field Descriptions
32
Receive Address Map Size 1 Register (RAMS1)
33
Receive Address Map Offset 1 Register (RAMO1)
33
Receive Address Map Size 1 Register (RAMS1) Field Descriptions
33
Receive Address Map Offset 1 Register (RAMO1) Field Descriptions
33
Receive Address Map Size 2 Register (RAMS2)
34
Receive Address Map Offset 2 Register (RAMO2)
34
Receive Address Map Size 2 Register (RAMS2) Field Descriptions
34
Receive Address Map Offset 2 Register (RAMO2) Field Descriptions
34
Receive Address Map Size 3 Register (RAMS3)
35
Receive Address Map Offset 3 Register (RAMO3)
35
Receive Address Map Size 3 Register (RAMS3) Field Descriptions
35
Receive Address Map Offset 3 Register (RAMO3) Field Descriptions
35
Receive Address Map Size 4 Register (RAMS4)
36
Receive Address Map Offset 4 Register (RAMO4)
36
Receive Address Map Size 4 Register (RAMS4) Field Descriptions
36
Receive Address Map Offset 4 Register (RAMO4) Field Descriptions
36
Chip Version Register (CHIPVER)
37
Auto Negotiation Register (AUTNGO)
37
Chip Version Register (CHIPVER) Field Descriptions
37
Auto Negotiation Register (AUTNGO) Field Descriptions
37
4 Remote Configuration Registers
38
VLYNQ Port Remote Controller Registers
38
Appendix A VLYNQ Protocol Specifications
39
Introduction
39
Special 8B/10B Code Groups
39
Supported Ordered Sets
39
A.1 Introduction
39
SPRU938B – September
39
A-1 Special 8B/10B Code Groups
39
A-2 Supported Ordered Sets
39
Packet Format (10-Bit Symbol Representation)
40
Packet Format (10-Bit Symbol Representation) Description
41
Scaling Factors
45
Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
45
Relative Performance with Various Latencies
46
Document Revision History
47
Important Notice
48
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