Texas Instruments TMS320C645x User Manual
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Texas Instruments TMS320C645x User Manual

Texas Instruments TMS320C645x User Manual

Tms320c645x general-purpose input/output spru724 user's guide
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TMS320C645x DSP
General-Purpose Input/Output (GPIO)
User's Guide
Literature Number: SPRU724
December 2005

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Summary of Contents for Texas Instruments TMS320C645x

  • Page 1 TMS320C645x DSP General-Purpose Input/Output (GPIO) User’s Guide Literature Number: SPRU724 December 2005...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

  • Page 3: Read This First

    About This Manual This document describes the general-purpose input/output (GPIO) peripheral in the digital signal processors (DSPs) of the TMS320C645x™ DSP family. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 4 Trademarks Related Documentation From Texas Instruments / Trademarks TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000t DSPs and includes application program examples. TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studiot integrated develop- ment environment and software tools.

  • Page 5: Table Of Contents

    Overview ................GPIO Function .
  • Page 6 Figures Figures TMS320C645x DSP Block Diagram GPIO Peripheral Block Diagram Interrupt Per-Bank Enable Register (BINTEN) Direction Register (DIR) Output Data Register (OUT_DATA) Set Data Register (SET_DATA) Clear Data Register (CLR_DATA) Input Data Register (IN_DATA) Set Rising Edge Interrupt Register (SET_RIS_TRIG)
  • Page 7 GPIO Interrupt and EDMA Event Configuration Options GPIO Registers ..............Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions Direction Register (DIR) Field Descriptions Output Data Register (OUT_DATA) Field Descriptions...
  • Page 8 This page is intentionally left blank. General-Purpose Input/Output (GPIO) SPRU724...

  • Page 9: Overview

    In addition, the GPIO peripheral can produce CPU interrupts and EDMA synchronization events in different interrupt/event generation modes. Figure 1 shows the GPIO peripheral in the TMS320C645x™ DSP. Figure 2 shows the GPIO peripheral block diagram. SPRU724...

  • Page 10: Tms320C645X Dsp Block Diagram

    Overview Figure 1. TMS320C645x DSP Block Diagram EMIFA DDR2 memory controller PLL2 GPIO Other peripherals EDMA controller Boot PLL2 configuration Some GPIO pins are MUXed with other device pins. Refer to the device-specific datasheet for details on specific MUXing and for the availability of the register bits.

  • Page 11: Gpio Peripheral Block Diagram

    Figure 2. GPIO Peripheral Block Diagram GPIO peripheral Data input/output Direction SET_DATA data Output OUT_DATA data Clear CLR_DATA data Input IN_DATA data EDMA event and interrupt generation Set rising SET_RIS_TRIG edge trigger Rising edge RIS_TRIG trigger Clear rising CLR_RIS_TRIG edge trigger Set falling SET_FAL_TRIG edge trigger...

  • Page 12: Gpio Function

    GPIO Function GPIO Function You can independently configure each GPIO pin (GPn) as either an input or an output using the GPIO direction registers. The GPIO direction register (DIR) specifies the direction of each GPIO signal. Logic 0 indicates the GPIO pin is configured as output, and logic 1 indicates input.

  • Page 13: Interrupt And Event Generation

    Interrupt and Event Generation Each GPIO pin (GPn) can be configured to generate a CPU interrupt (GPINTn) and a synchronization event to the EDMA controller (GPINTn). The interrupt and EDMA event can be generated on the rising-edge, falling-edge, or on both edges of the GPIO signal.

  • Page 14: Emulation Halt Operation

    Emulation Halt Operation Interrupt and Event Generation / Interrupts and Events Reading the SET_RIS_TRIG or CLR_RIS_TRIG register returns the value of RIS_TRIG register. Reading from SET_FAL_TRIG and CLR_FAL_TRIG register returns the value of FAL_TRIG register. To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set to 1.

  • Page 15: Registers

    Registers The GPIO peripheral is configured through the registers listed in Table 2. See the device-specific datasheet for the memory address of these registers. Table 2. GPIO Registers Offsets Acronym 0008 BINTEN 0010 0014 OUT_DATA 0018 SET_DATA 001C CLR_DATA 0020 IN_DATA 0024 SET_RIS_TRIG...

  • Page 16: Interrupt Per-Bank Enable Register (Binten)

    Registers Interrupt Per-Bank Enable Register (BINTEN) To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown in Figure 3 and described in Table 3. Figure 3.

  • Page 17: Direction Register (Dir)

    Direction Register (DIR) The GPIO direction register (DIR) determines if a given GPIO pin is an input or an output. The GPDIR is shown in Figure 4 and described in Table 4. By default, all the GPIO pins are configured as input pins. When GPIO pins are configured as output pins, the GPIO output buffer drives the GPIO pin.

  • Page 18: Output Data Register (Out_Data)

    Registers Output Data Register (OUT_DATA) The GPIO output data register (OUT_DATA) indicates the value to be driven on a given GPIO output pin. The OUT_DATA registers are shown in Figure 5 and described in Table 5. Figure 5. Output Data Register (OUT_DATA) OUT15 OUT14 OUT13...

  • Page 19: Set Data Register (Set_Data)

    Set Data Register (SET_DATA) The GPIO set data register (SET_DATA) is shown in Figure 6 and described in Table 6. SET_DATA provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of SET_DATA sets the corresponding bit in OUT_DATA.

  • Page 20: Clear Data Register (Clr_Data)

    Registers Clear Data Register (CLR_DATA) The GPIO clear data register (CLR_DATA) is shown in Figure 7 and described in Table 7. CLR_DATA provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of CLR_DATA clears the corresponding bit in OUT_DATA.

  • Page 21: Input Data Register (In_Data)

    Input Data Register (IN_DATA) The GPIO input data register (IN_DATA) reflects the state of the GPIO pins. The IN_DATA register is shown in Figure 8 and described in Table 8. When read, IN_DATA returns the state of the GPIO pins regardless of the state of the corresponding bits in the DIR and OUT_DATA registers.

  • Page 22: Set Rising Edge Interrupt Register (Set_Ris_Trig)

    Registers Set Rising Edge Interrupt Register (SET_RIS_TRIG) The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the rising edge of GPn.

  • Page 23: Clear Rising Edge Interrupt Register (Clr_Ris_Trig)

    Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the rising edge of GPn.

  • Page 24: Set Falling Edge Interrupt Register (Set_Fal_Trig)

    Registers Set Falling Edge Interrupt Register (SET_FAL_TRIG) The GPIO falling trigger register (FAL_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals. Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the falling edge of GPn.

  • Page 25: Clear Falling Edge Interrupt Register (Clr_Fal_Trig)

    5.10 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG) The GPIO falling trigger register (FAL_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals. Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the falling edge of GPn.
  • Page 26 This page is intentionally left blank. General-Purpose Input/Output (GPIO) SPRU724...
  • Page 27 C645x DSP 10 GPIO 11 event generation 13 events 14 function 12 SPRU724 interrupt generation 13 interrupts 14 notational conventions 3 overview 9 registers 15 related documentation from Texas Instruments 3 trademarks 4 General-Purpose Input/Output (GPIO) Index Index...

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