Page 1 TMS320TCI648x Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13A September 2006...
Page 2 SPRUE13A – September 2006 Submit Documentation Feedback...
Page 3: Table Of Contents
Preface Overview General RapidIO System RapidIO Feature Support in SRIO Standards External Devices Requirements TI Devices Supported By This Document SRIO Functional Description Overview SRIO Pins Functional Operation Logical/Transport Error Handling and Logging Interrupt Conditions CPU Interrupts General Description Interrupt Condition Status and Clear Registers Interrupt Condition Routing Registers Interrupt Status Decode Registers Interrupt Generation...
Page 4 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) 5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) 5.29...
Page 5 5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) 5.72 Port Error and Status CSR n (SPn_ERR_STAT) 5.73 Port Control CSR n (SPn_CTL) 5.74 Error Reporting Block Header Register (ERR_RPT_BH) 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) 5.76...
Page 6 RapidIO Architectural Hierarchy RapidIO Interconnect Architecture Serial RapidIO Device to Device Interface Diagrams SRIO Peripheral Block Diagram Operation Sequence 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) Serial RapidIO Control Symbol Format SRIO Component Block Diagram SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3...
Page 7 RX CPPI Interrupt Condition Status and Clear Registers TX CPPI Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear Registers Error, Reset, and Special Event Interrupt Condition Status and Clear Registers Doorbell 0 Interrupt Condition Routing Registers RX CPPI Interrupt Condition Routing Registers TX CPPI Interrupt Condition Routing Registers LSU Interrupt Condition Routing Registers...
Page 8 LSUn FLOW_MASK Fields Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700h Transmit CPPI Supported Flow Mask Registers TX Queue n FLOW_MASK Fields Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) (Address Offset 0740h)
Page 9 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h Port-Write-In Capture CSRs Port Reset Option CSR n (SPn_RST_OPT) Port Control Independent Register n (SPn_CTL_INDEP) Port Silence Timer n Register (SPn_SILENCE_TIMER) Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Port Control Symbol Transmit n Register (SPn_CS_TX) SPRUE13A –...
Page 10 TI Devices Supported By This Document Registers Checked for Multicast DeviceID Packet Types Pin Description SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions Line Rate versus PLL Output Clock Frequency Effect of the RATE Bits Frequency Range versus MPY Value SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions EQ Bits SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Descriptions...
Page 11 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions PF_16B_CNTL Registers Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions PF_8B_CNTL Registers Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions SERDES_CFGRXn_CNTL Registers and the Associated Ports SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions EQ Bits SERDES_CFGTXn_CNTL Registers and the Associated Ports...
Page 12 LSUn_REG6 Registers and the Associated LSUs LSUn Control Register 6 (LSUn_REG6) Field Descriptions LSUn_FLOW_MASKS Registers and the Associated LSUs LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions LSUn FLOW_MASK Fields QUEUEn_TXDMA_HDP Registers Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) Field Descriptions QUEUEn_TXDMA_CP Registers Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field Descriptions QUEUEn_RXDMA_HDP Registers...
Page 13 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions...
Page 14: About This Manual
TMS320TCI648x Bootloader User's Guide(literature number SPRUEC7) describes the features of the on-chip Bootloader provided with the TMS320TCI648x Digital Signal Processor (DSP). Included are descriptions of the available boot modes and any interfacing requirements associated with them, instructions on generating the boot table, and information on the different versions of the Bootloader.
Page 15 Trademarks TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. RapidIO is a registered trademark of RapidIO Trade Association. InfiniBand is a trademark of the InfiniBand Trade Association. SPRUE13A – September 2006 Submit Documentation Feedback...
Page 16: Overview
Overview The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document, and the features supported and not supported for SRIO.
Page 17: Rapidio Architectural Hierarchy
www.ti.com Figure 1. RapidIO Architectural Hierarchy Logical specification Information necessary for the end point to process the transaction (i.e., transaction type, size, physical address) Transport specification Information to transport packet from end to end in the system (i.e., routing address) Physical specification Information necessary to move packet between two physical devices (i.e., electrical...
Page 18: Rapidio Interconnect Architecture
Overview 1.1.2 RapidIO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system. Figure 2. RapidIO Interconnect Architecture Host Subsystem Memory Memory Host Host Processor Processor RapidIO RapidIO RapidIO...
Page 19: Rapidio Feature Support In Srio
www.ti.com Figure 3. Serial RapidIO Device to Device Interface Diagrams Serial RapidIO 1x Device to 1x Device Interface Diagram Serial RapidIO 4x Device to 4x Device Interface Diagram RapidIO Feature Support in SRIO Features Supported in SRIO Peripheral: RapidIO Interconnect Specification V1.2 compliance, Errata 1.2 Physical Layer 1x/4x LP-Serial Specification V1.2 compliance 4x Serial RapidIO with auto-negotiation to 1x port, optional operation for four 1x ports Integrated clock recovery with TI SERDES...
Page 20: Standards
Overview Features Not Supported: Compliance with the Global Shared Memory specification (GSM) 8/16 LP-LVDS compatible Destination support of RapidIO Atomic Operations Simultaneous mixing of frequencies between 1x ports (all ports must be the same frequency) Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal L2 memory and registers Standards The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the...
Page 21: Srio Functional Description
www.ti.com SRIO Functional Description Overview 2.1.1 Peripheral Data Flow This peripheral is designed to be an externally driven slave module that is capable of acting as a master in the DSP system. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an interrupt to the CPU or without relying on the DSP EDMA.
Page 22: Srio Peripheral Block Diagram
SRIO Functional Description 1.25 to 3.125 Gbps differential data RX Clock recovery Clock recovery Clock recovery Clock recovery Within the physical layer, the data next goes to the 8-bit/10-bit (8b/10b) decode block. 8b/10b encoding is used by RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encoding overhead is removed as the 10-bit data is decoded to the raw 8-bit data.
Page 23: Operation Sequence
www.ti.com SRIO endpoints are typically not connected directly to each other but instead have intervening connection fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical interconnect. Control symbols are used for packet acknowledgment, flow control information, and maintenance functions.
Page 24: 1X/4X Rapidio Packet Data Stream (Streaming-Write Class)
SRIO Functional Description Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) address rsrv xamsbs acklD rsv tt ftype destID prio sourcelD prio ftype a c k l D destID sourcelD address rsrv xamsbs Note: Figure 6 assumes that addresses are 32-bit and device IDs are 8-bit. The device ID, being an 8-bit field, will address up to 256 nodes in the system.
Page 25: Srio Pins
www.ti.com The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are responded to with an error response packet.
Page 26: Functional Operation
SRIO Functional Description Pin Name Count RIOTX3/ RIOTX3 RIOTX2/ RIOTX2 RIOTX1/ RIOTX1 RIOTX0/ RIOTX0 RIORX3/ RIORX3 RIORX2/ RIORX2 RIORX1/ RIORX1 RIORX0/ RIORX0 RIOCLK/ RIOCLK Functional Operation 2.3.1 Component Block Diagram Figure 8 shows a component block diagram of the SRIO peripheral. The load/store unit (LSU) controls the transmission of direct I/O packets, and the memory access unit (MAU) controls the reception of direct I/O packets.
Page 27: Srio Component Block Diagram
www.ti.com Figure 8. SRIO Component Block Diagram Load/Store units (LSUs) TX direct I/O Maintenance 4.5 KB TX shared buffer TX buffering 32 x 276B 8 buffers per 1X port - all priorities 32 buffers per 4X port - 8 per priority Port 0 8 x 276 TX 8 x 276 RX...
Page 28: Serdes Macro Configuration Register 0 (Serdes_Cfg0_Cntl)
SRIO Functional Description 2.3.2 SERDES Macro and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency nodes specified in V1.2 of the RapidIO Interconnect Specification (1.25, 2.5, and 3.125 Gbps).
Page 29: Serdes Macro Configuration Register 0 (Serdes_Cfg0_Cntl) Field Descriptions
www.ti.com Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions Field Value 31–10 Reserved 0000h 9–8 7–6 Reserved 5–1 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01111b 1xxxxb ENPLL Based on the MPY value, the line rate versus PLL output clock frequency can be calculated. This is summarized in Table SPRUE13A –...
Page 30: Line Rate Versus Pll Output Clock Frequency
SRIO Functional Description Table 6. Line Rate versus PLL Output Clock Frequency Rate Full Half Quarter RIOCLK and RIOCLK FREQ The rate is defined by the RATE bits of the SERDES_CFGRXn_CNTL register and the SERDES_CFGTXn_CNTL register, respectively. The primary operating frequency of the SERDES macro is determined by the reference clock frequency and PLL multiplication factor.
Page 31: Serdes Receive Channel Configuration Register N (Serdes_Cfgrxn_Cntl)
www.ti.com The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the received message so that the data samples are taken midway between data transitions. The second order algorithm can be optionally disabled, and both can be configured to optimize their dynamics. Both algorithms use the same basic technique for determining whether the sampling clock is ideally placed, and if not whether it needs to be moved earlier or later.
Page 32 SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Field 25–24 Reserved Reserved 22–19 0000b–1111b 18–16 15–14 13–12 ALIGN Reserved 10–8 TERM INVPAIR 6–5 RATE Serial RapidIO (SRIO) Descriptions (continued) Value Description Always write 0s to these reserved bits. This read-only bit returns 0 when read.
Page 33: Serdes Transmit Channel Configuration Register N (Serdes_Cfgtxn_Cntl)
www.ti.com Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Field 4–2 BUSWIDTH Reserved ENRX CFGRX[22–19] 0000b 0001b 001xb 01xxb 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 2.3.2.3 Enabling the Transmitter To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTXn_CNTL registers (110h–10Ch) must be set high.
Page 34: De Bits Of Serdes_Cfgtxn_Cntl
SRIO Functional Description Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Field Value 15–12 0000b–1111b 11–9 SWING 000b–111b INVPAIR 6–5 RATE 4–2 BUSWIDTH 000b Reserved ENTX Table 12. DE Bits of SERDES_CFGTXn_CNTL DE Bits 0000b 0001b 0010b 0011b 0100b 0101b 0110b...
Page 35: Swing Bits Of Serdes_Cfgtxn_Cntl
www.ti.com Table 13. SWING Bits of SERDES_CFGTXn_CNTL SWING Bits 2.3.2.4 SERDES Configuration Example //full sample rate at 3.125 Gbps //SERDES reference clock (RIOCLK) 125 MHz //MPY = 12.5 125MHz = ((3.125 Gbps)(.5))/MPY SRIO_REGS->SERDES_CFG0_CNTL = 0x0000000F; SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;...
Page 36: Load/Store Registers For Rapidio
SRIO Functional Description Figure 12. Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3 LSU _REG0 LSU _REG1 LSU _REG2 LSU _REG3 LSU _REG4 OutPortID LSU _REG5 Drbll Info LSU _REG6 The mapping of LSU register fields to RapidIO packet header fields is explained in Table 14 has the fields of the control and command registers (LSUn_REG0 through LSUn_REG5), and Table 15...
Page 37: Lsu Status Register Fields
www.ti.com Table 14. LSU Control/Command Register Fields (continued) LSU Register Field RapidIO Packet Header Field DestID RapidIO destinationID field specifying the target device. Packet Type 4 MSBs: 4-bit ftype field for all packets 4 LSBs: 4-bit trans field for packet types 2, 5, and 8 OutPortID Not available in RapidIO header.
Page 38: Lsu Registers Timing
SRIO Functional Description LSU _REG1 LSU _REG2 LSU _REG3 LSU _REG4 LSU _REG5 Rdy/BSY Completion The following code illustrates an LSU registers programming example. SRIO_REGS->LSU1_REG0 = SRIO_REGS->LSU1_REG1 = SRIO_REGS->LSU1_REG2 = SRIO_REGS->LSU1_REG3 = SRIO_REGS->LSU1_REG4 = SRIO_REGS->LSU1_REG5 = Figure 14 gives an example of the data flow and field mappings for a burst NWRITE_R transaction. Serial RapidIO (SRIO) Figure 13.
Page 39: Example Burst Nwrite_R
www.ti.com Priority OutPortID LSU _REG5 Drbll Hop Count Packet 16 15 ackID prio ftype destID sourceID For WRITE commands, the payload is combined with the header information from the control/command registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for transmission.
Page 40: Load/Store Module Data Flow Diagram
SRIO Functional Description Figure 15. Load/Store Module Data Flow Diagram RapidIO transport and physical layers Port x transmission FIFO queues FIFO FIFO 2.3.3.2 Direct I/O TX Operation WRITE Transactions: The TX buffers are implemented in a single SRAM and shared between multiple cores. A state machine arbitrates and assigns available buffers between the LSUs.
Page 41 www.ti.com Data leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A reordering mechanism exists here, which transmits the highest priority packets first if RETRY acknowledges.
Page 42 SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request RapidIO address is non-64-bit aligned. In both cases, the outgoing request is broken up into multiple RapidIO request packets.
Page 43 www.ti.com So the general flow is as follows: Previously, the control/command registers were written and the request packet was sent Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority) The argetTID is examined to determine routing of a response to the appropriate core The status field of the response packet is checked for ERROR, RETRY or DONE If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address.
Page 44: Cppi Rx Scheme For Rapidio
SRIO Functional Description Out-of-order responses are allowed. A RETRY response is issued to the first received segment of a multi-segment message when the RX queue is busy servicing another request. – Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue.
Page 45: Message Request Packet
www.ti.com acklD prio ftype destID sourcelD msglen ftype = 1011 This enables the letter and mailbox fields to instead allow four concurrent single-segment messages to sixty-four possible mailboxes (256 total locations) for a source and destination pair. The mailbox mapper directs the inbound messages to the appropriate queue based on a pre-programmed routing table.
Page 46: Mailbox To Queue Mapping Register Pair
SRIO Functional Description Figure 18. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 30 29 LETTER_MASK MAILBOX_MASK R/W-11 R/W-111111 Mailbox to Queue Mapping Register H n (RXU_MAP_H n ) 10 9 Reserved LEGEND: R/W = Read/Write;...
Page 47: Rx Buffer Descriptor Fields
www.ti.com If a RX message’s length is greater than that of the targeted buffer descriptor, an ERROR response is sent back to the source device. In addition, the DSP is notified with the use of the CC field of the RX CPPI buffer descriptor, described as follows.
Page 48 SRIO Functional Description Table 18. RX Buffer Descriptor Field Descriptions (continued) Field ownership teardown_complete message_length src_id mailbox Serial RapidIO (SRIO) Description Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the DSP core and cleared by the port when the message has been transmitted. The DSP core uses this bit to reclaim buffers.
Page 49: Rx Cppi Mode Explanation
www.ti.com Although the switch fabric delivers the segments of multi-packet messages in the order they were sent, buffer resources at the receiving endpoint may only become available after the initial segment(s) of a message have had to be retried. The peripheral can accept out-of-order segments and track completion of the overall message.
Page 50 SRIO Functional Description In addition, multiple messages can be interleaved at the receive port due to ordering within a connected switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block can handle simultaneous interleaved multi-segment messages. This implies that state information (write pointers and sourceID) is maintained on each simultaneous message to properly store the segments in memory.
Page 51: Cppi Boundary Diagram
www.ti.com CPPI block CPPI control registers Data buffer 2.3.4.2 TX Operation Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs. The queues are configured and initialized upon reset. When a CPU wants to send a message to an external RapidIO device, it writes the buffer descriptor information via the configuration bus into the SRAM.
Page 52: Tx Buffer Descriptor Fields
SRIO Functional Description Table 20. TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh) Name Description 31–0 TX Queue TX Queue Completion Pointer: This field is the DSP core memory address for the transmit queue Completion Pointer completion pointer. This register is written by the DSP core with the buffer descriptor address for the last buffer processed by the DSP core during interrupt processing.
Page 53 www.ti.com Table 21. TX Buffer Descriptor Field Definitions (continued) Field retry_count message_length dest_id port_id SPRUE13A – September 2006 Submit Documentation Feedback Description Message Retry Count: Set by the DSP core to indicate the total number of retries allowed for this message, including all segments. Decremented by the port each time a message is retried.
Page 54 SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field ssize mailbox Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control. If the transaction has been flow controlled, the DMA bus READ request is postponed so that the TX buffer space is not wasted.
Page 55 www.ti.com TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1, it will re-attempt to send the same message from Queue 0 before moving on. Whether it is successful or not, the next attempt will come from Queue 1. Within a given queue, the hardware will always try to send the head buffer descriptor and can not move to the next buffer descriptor in the queue until a completion code is written.
Page 56: Weighted Round Robin Programming Registers (Address Offset 7E0H-7Ech)
SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) TX_QUEUE_CNTL0 - Address Offset 7E0h <-------------------------------- TX_Queue_Map3 -----------------------------> 28 27 Number of Msgs R/W-0h <-------------------------------- TX_Queue_Map1 -----------------------------> 12 11 Number of Msgs R/W-0h TX_QUEUE_CNTL1 - Address Offset 7E4h <-------------------------------- TX_Queue_Map7 ----------------------------->...
Page 57 www.ti.com Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair Register[Bits] TX_Queue_Map2 TX_QUEUE_CNTL0[19–16] TX_QUEUE_CNTL0[23–20] TX_Queue_Map3 TX_QUEUE_CNTL0[27–24] TX_QUEUE_CNTL0[31–28] TX_Queue_Map4 TX_QUEUE_CNTL1[3–0] TX_QUEUE_CNTL1[7–4] TX_Queue_Map5 TX_QUEUE_CNTL1[11–8] TX_QUEUE_CNTL1[15–12] TX_Queue_Map6 TX_QUEUE_CNTL1[19–16] TX_QUEUE_CNTL1[23–20] TX_Queue_Map7 TX_QUEUE_CNTL1[27–24] TX_QUEUE_CNTL1[31–28] TX_Queue_Map8 TX_QUEUE_CNTL2[3–0] TX_QUEUE_CNTL2[7–4] TX_Queue_Map9 TX_QUEUE_CNTL2[11–8] TX_QUEUE_CNTL2[15–12] TX_Queue_Map10 TX_QUEUE_CNTL2[19–16] TX_QUEUE_CNTL2[23–20] SPRUE13A –...
Page 58 SRIO Functional Description Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair Register[Bits] TX_Queue_Map11 TX_QUEUE_CNTL2[27–24] TX_QUEUE_CNTL2[31–28] TX_Queue_Map12 TX_QUEUE_CNTL3[3–0] TX_QUEUE_CNTL3[7–4] TX_Queue_Map13 TX_QUEUE_CNTL3[11–8] TX_QUEUE_CNTL3[15–12] TX_Queue_Map14 TX_QUEUE_CNTL3[19–16] TX_QUEUE_CNTL3[23–20] TX_Queue_Map15 TX_QUEUE_CNTL3[27–24] TX_QUEUE_CNTL3[31–28] The TX queues are treated differently than the RX queues. A TX queue can mix single and multi-segment message buffer descriptors.
Page 59 www.ti.com A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined by the 24-bit value in the port response time-out CSR (See Specification states that the maximum time interval (all 1s) is between 3 and 6 seconds.
Page 60 SRIO Functional Description 2.3.4.4 Message Passing Software Requirements Software performs the following functions for messaging: RX Operation Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM Link-lists the buffer descriptors, next_descriptor_pointer Assigns single segment (256-byte payload) and multi-segment (4K-byte payload) buffers to queues buffer_length Assigns buffer descriptor to data buffer, buffer_pointer...
Page 61 www.ti.com Initialization Example SRIO_REGS->Queue0_RXDMA_HDP SRIO_REGS->Queue1_RXDMA_HDP SRIO_REGS->Queue2_RXDMA_HDP SRIO_REGS->Queue3_RXDMA_HDP SRIO_REGS->Queue4_RXDMA_HDP SRIO_REGS->Queue5_RXDMA_HDP SRIO_REGS->Queue6_RXDMA_HDP SRIO_REGS->Queue7_RXDMA_HDP SRIO_REGS->Queue8_RXDMA_HDP SRIO_REGS->Queue9_RXDMA_HDP SRIO_REGS->Queue10_RXDMA_HDP SRIO_REGS->Queue11_RXDMA_HDP SRIO_REGS->Queue12_RXDMA_HDP SRIO_REGS->Queue13_RXDMA_HDP SRIO_REGS->Queue14_RXDMA_HDP SRIO_REGS->Queue15_RXDMA_HDP Queue Mapping SRIO_REGS->RXU_MAP01_L = CSL_FMK( SRIO_RXU_MAP01_L_LETTER_MASK, 3)| CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX_MASK, 0x3F) CSL_FMK( SRIO_RXU_MAP01_L_LETTER, 0) CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX, 1) CSL_FMK( SRIO_RXU_MAP01_L_SOURCEID, 0xBEEF); SRIO_REGS->RXU_MAP01_H = CSL_FMK( SRIO_RXU_MAP01_H_TT, 1) CSL_FMK( SRIO_RXU_MAP01_H_QUEUE_ID, 0) CSL_FMK( SRIO_RXU_MAP01_H_PROMISCUOUS, 1)| CSL_FMK( SRIO_RXU_MAP01_H_SEGMENT_MAPPING, 1);...
Page 62: Rx Buffer Descriptors
SRIO Functional Description Descriptor Descriptor TX Buffer Descriptor TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); TX_DESCP0_1 TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff1[0] ); Pointer TX_DESCP0_0->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF) CSL_FMK( SRIO_TXDESC2_PRI, 1) CSL_FMK( SRIO_TXDESC2_TT, 1) CSL_FMK( SRIO_TXDESC2_PORTID, 3) CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)| CSL_FMK( SRIO_TXDESC2_MAILBOX, 0); TX_DESCP0_0->TXDESC3 = CSL_FMK( SRIO_TXDESC3_SOP,1 ) CSL_FMK( SRIO_TXDESC3_EOP,1 )
Page 63: Tx Buffer Descriptors
www.ti.com Descriptor Descriptor Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP SRIO_REGS->Queue0_TXDMA_HDP 2.3.5 Maintenance The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command and status registers (CSRs), and data structures. Unlike other request formats, the type 8 packet format serves as both the request and the response format for maintenance operations. Type 8 packets contain no addresses and only contain data payloads for write requests and read responses.
Page 64: Doorbell Operation
SRIO Functional Description for any desired purpose; see the RapidIO Interconnect Specification, Section 3.1.4, Type 10 Packet Formats (Doorbell Class), for information about the info field. A processing element that receives a doorbell transaction takes the packet and puts it in a doorbell message queue within the processing element.
Page 65 www.ti.com SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 ); SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, 0); SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, 0); SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT, 0 ); SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,1 ) CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 ) CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 ) CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 ) CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )| CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,0 ); SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )| CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x03 )
Page 66: Flow Control Table Entry Registers (Address Offset 0900H-093Ch)
SRIO Functional Description Since CCPs do not have guaranteed delivery and can be dropped by the fabric, an implicit method of enabling an Xoff’d flow must exist. A simple timeout method is used. Additionally, flow control checks can be enabled or disabled through the Transmit Source Flow Control Masks. Received CCPs are not passed through the DMA bus interface.
Page 67: Transmit Source Flow Control Masks
www.ti.com Table 24. Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions Field 31–18 Reserved 17–16 15–0 FLOW_CNTL_ID Each transmit source, including any LSU and any TX CPPI queue, indicates which of the 16 flows it uses with a 16-bit flow mask. Figure 28 illustrates the general form of an individual flow mask.
Page 68: Fields Within Each Flow Mask
SRIO Functional Description Field Value Description FL15 TX source does not support Flow 15 from table entry TX source supports Flow 15 from table entry FL14 TX source does not support Flow 14 from table entry TX source supports Flow 14 from table entry FL13 TX source does not support Flow 13 from table entry TX source supports Flow 13 from table entry...
Page 69: Configuration Bus Example
www.ti.com 2.3.9.1 Translation for MMR space There are no Endian translation requirements for accessing the local MMR space. Regardless of the device memory Endian configuration, all configuration bus accesses are performed on 32-bit values at a fixed address position. The bit positions in the 32-bit word are defined by this specification. This means that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian configurations.
Page 70: Reset Hierarchy
SRIO Functional Description 2.3.10 Reset and Power Down The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in Table 26. With the exception of BLK0_EN for the memory-mapped registers (MMRs), when the BLKn_EN signals are deasserted, the clocks are gated to these blocks, effectively providing a shutdown function. Logical Block Reset DMA interface...
Page 71: Gbl_En (Address 0030H)
www.ti.com 2.3.10.1 Reset and Power Down Summary After reset, the state of the peripheral depends on the default register values. Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and BLKn_EN bits. The GBL_EN bit resets the peripheral, while the rest of the device is not reset. The BLKn_EN bits shut down unused portions of the peripheral, which minimizes power by resetting the appropriate logical block(s) and gating off the clock to the appropriate logical block(s).
Page 72: Blk0_En (Address 0038H)
SRIO Functional Description Table 27. Global Enable and Global Enable Status Field Descriptions Register (Bit) Field GBL_EN(31–1) Reserved GBL_EN(0) GBL_EN_STAT(31–10) Reserved GBL_EN_STAT(9) BLK8_EN_STAT GBL_EN_STAT(8) BLK7_EN_STAT GBL_EN_STAT(7) BLK6_EN_STAT GBL_EN_STAT(6) BLK5_EN_STAT GBL_EN_STAT(5) BLK4_EN_STAT GBL_EN_STAT(4) BLK3_EN_STAT GBL_EN_STAT(3) BLK2_EN_STAT GBL_EN_STAT(2) BLK1_EN_STAT GBL_EN_STAT(1) BLK0_EN_STAT GBL_EN_STAT(0) GBL_EN_STAT The 18 block-specific registers are represented by bits with the same functions, which are described in...
Page 73: Blk0_En_Stat (Address 003Ch)
www.ti.com LEGEND: R = Read, W = Write, -n = Value after reset LEGEND: R = Read, W = Write, -n = Value after reset LEGEND: R = Read, W = Write, -n = Value after reset LEGEND: R = Read, W = Write, -n = Value after reset LEGEND: R = Read, W = Write, -n = Value after reset Table 28.
Page 74: Peripheral Control Register (Pcr) - Address Offset 0004H
SRIO Functional Description 2.3.10.3 Software Shutdown Details Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply asserting the appropriate reset signal to each logical block within the peripheral, clocks are gated off to the corresponding logical block as well.
Page 75 www.ti.com Table 29. Peripheral Control Register (PCR) Field Descriptions (continued) Field Value Description SOFT Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation halts. Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO peripheral.) Soft stop FREE...
Page 76 SRIO Functional Description The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in which case a re-ordering algorithm is used. The algorithm searches backward through the buffer group for the first packet with the highest priority.
Page 77: Port Mode Register Settings
www.ti.com For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first segment, the TXU moves to the next queue in the round-robin loop. The TXU tries to send the unsent message again the next time around the loop. After the first segment is granted outbound credit and is sent to the physical layer for transmission, all subsequent segments are given 64K attempts to gain outbound credit.
Page 78 SRIO Functional Description SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013; SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000; SRIO_REGS->SERDES_CFGRX0_CNTL SRIO_REGS->SERDES_CFGRX1_CNTL SRIO_REGS->SERDES_CFGRX2_CNTL SRIO_REGS->SERDES_CFGRX3_CNTL SRIO_REGS->SERDES_CFGTX0_CNTL SRIO_REGS->SERDES_CFGTX1_CNTL SRIO_REGS->SERDES_CFGTX2_CNTL SRIO_REGS->SERDES_CFGTX3_CNTL 2.3.13.3 Peripheral Initializations Set Device ID Registers rdata = SRIO_REGS->DEVICEID_REG1; wdata = 0x00ABBEEF; mask = 0x00FFFFFF; mdata = (wdata & mask) | (rdata & ~mask); SRIO_REGS->DEVICEID_REG1 rdata = SRIO_REGS->DEVICEID_REG2;...
Page 79 www.ti.com SRIO_REGS->SP_RT_CTL SRIO_REGS->SP_GEN_CTL SRIO_REGS->SP0_CTL SRIO_REGS->SP1_CTL SRIO_REGS->SP2_CTL SRIO_REGS->SP3_CTL SRIO_REGS->ERR_DET SRIO_REGS->ERR_EN SRIO_REGS->H_ADDR_CAPT SRIO_REGS->ADDR_CAPT SRIO_REGS->ID_CAPT SRIO_REGS->CTRL_CAPT SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ; // clear SRIO_REGS->SP_IP_PW_IN_CAPT2 = 0x00000000 ; // clear SRIO_REGS->SP_IP_PW_IN_CAPT3 = 0x00000000 ; // clear //INIT_WAIT wait for lane initialization Read register to check portx(1-4) OK bit // polling SRIO_MAC's port_ok bit rdata = SRIO_REGS->P0_ERR_STAT ;...
Page 80: Bootload Operation
SRIO Functional Description 4. DSP executes idle instruction. 5. RapidIO ports send Idle control symbols to train PHYs. 6. Host enabled to explore system with RapidIO Maintenance packets. 7. Host identifies, enumerates and initializes the RapidIO device. 8. Host controller configures DSP peripherals through maintenance packets. SRIO Device IDs are set for DSPs (either by pin strapping or by host manipulation) 9.
Page 81: Packet Forwarding Register N For 16-Bit Device Ids (Pf_16B_Cntln) Offsets 0X0090, 0X0098, 0X00A0, 0X00A8
www.ti.com Device TMS320TCI6482 2.3.15.2 Daisy Chain Operation and Packet Forwarding Some applications may require daisy chaining of devices together versus using a switch fabric. Typically, these applications are low cost implementations. Daisy chains have variable system latency depending on device position within the chain. Daisy chain implementations also have reduced bandwidth capabilities, since the link bandwidth doesn’t change, the bandwidth allocated to each device in the chain is limited (sum of devices’...
Page 82: Packet Forwarding Register N For 8-Bit Device Ids (Pf_8B_Cntln) Offsets 0X0094, 0X009C, 0X00A4, 0X00Ac
SRIO Functional Description Figure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) Offsets 0x0094, LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 33. Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions Field 31–18 Reserved...
Page 83: Logical/Transport Error Handling And Logging
www.ti.com Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. The detectable errors are captured in the logical layer error detect CSR (see block(s) involved for each detectable error condition, and includes brief descriptions of the errors captured. Figure 44.
Page 84: Logical/Transport Layer Error Detect Csr (Err_Det)
Logical/Transport Error Handling and Logging Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Field MSG_REQ_TIMEOUT PKT_RSPNS_TIMEOUT UNSOLICITED_RSPNS UNSUPPORTED_TRANS 21–8 Reserved RX_CPPI_SECURITY RX_IO_DMA_ACCESS 5–0 Reserved Serial RapidIO (SRIO) Value Description Message request timeout (endpoint device only) A timeout has not been detected by RXU. A timeout has been detected by the RXU.
Page 85: Interrupt Conditions
www.ti.com Interrupt Conditions This section defines the CPU interrupt capabilities and requirements of the peripheral. CPU Interrupts The following interrupts are supported by the RIO peripheral. Error status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize the peripheral.
Page 86: Interrupt Condition Status And Clear Registers
Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers (see Table 23 for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers.
Page 87: Doorbell 0 Interrupt Condition Status And Clear Registers
www.ti.com Table 35. Interrupt Condition Status and Clear Bits Field Access Reset Value ICSx ICCx 4.3.1 Doorbell Interrupt Condition Status and Clear Registers The interrupt condition status registers (ICSRs) and the interrupt condition clear registers (ICCRs) for the four doorbells are shown in Figure 46 peripheral receives doorbell packets.
Page 88: Doorbell 2 Interrupt Condition Status And Clear Registers
Interrupt Conditions Figure 48. Doorbell 2 Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status Register (DOORBELL2_ICSR) (Address Offset 0220h) ICS15 ICS14 ICS13 ICS12 ICS11 Doorbell 2 Interrupt Condition Clear Register (DOORBELL2_ICCR) (Address Offset 0228h) ICC15 ICC14 ICC13 ICC12 ICC11 LEGEND: R = Read only;...
Page 89: Rx Cppi Interrupt Condition Status And Clear Registers
www.ti.com For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the queue (QUEUEn_TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This value is compared against the port written value in the CP register.
Page 90: Lsu Interrupt Condition Status And Clear Registers
Interrupt Conditions Figure 52. LSU Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status Register (LSU_ICSR) (Address Offset 0260h) ICS31 ICS30 ICS29 ICS28 ICS27 ICS15 ICS14 ICS13 ICS12 ICS11 LSU Interrupt Condition Clear Register (LSU_ICCR) (Address Offset 0268h) ICC31 ICC30 ICC29 ICC28...
Page 91: Error, Reset, And Special Event Interrupt Condition Status And Clear Registers
www.ti.com Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued) Associated LSU LSU1 LSU1 LSU1 LSU1 LSU1 LSU1 LSU1 4.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers The ICSR and the ICCR for the SRIO ports are shown in nonreserved status and clear bits corresponds to a particular interrupt condition in one or more of the SRIO ports.
Page 92: Interrupt Clearing Sequence For Special Event Interrupts
Interrupt Conditions The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR register (0x0278) in the same manner as other interrupts. However, in order for new event detection and interrupt generation to occur for these special interrupts, additional register bits must be cleared. The following table notes the additional interrupt source register bits that need to be cleared and the appropriated sequence.
Page 93: Interrupt Condition Routing Registers
www.ti.com Table 38. Interrupt Clearing Sequence for Special Event Interrupts (continued) Interrupt Function Port 3 Error (TMS320TCI6482 Only) Device Reset Interrupt Condition Routing Registers The interrupt conditions are programmable to select the interrupt output that will be driven. Using the interrupt condition routing registers (ICRRs), software can independently route each interrupt request to any of the interrupt destinations supported by the device.
Page 94: Doorbell 0 Interrupt Condition Routing Registers
Interrupt Conditions When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests to interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b in DOORBELL2_ICRR, the interrupt request from Doorbell 2, bit 6 is sent to interrupt destination 2. Figure 54.
Page 95: Tx Cppi Interrupt Condition Routing Registers
www.ti.com Figure 56. TX CPPI Interrupt Condition Routing Registers TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h) 28 27 ICR7 R/W-0000 12 11 ICR3 R/W-0000 TX CPPI Interrupt Condition Routing Register 2 (TX_CPPI_ICRR2) (Address Offset 02D4h) 28 27 ICR15 R/W-0000 12 11...
Page 96: Lsu Interrupt Condition Routing Registers
Interrupt Conditions Figure 57. LSU Interrupt Condition Routing Registers LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h) 28 27 ICR7 R/W-0000 12 11 ICR3 R/W-0000 LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h) 28 27 ICR15 R/W-0000 12 11 ICR11...
Page 97: Interrupt Status Decode Registers
www.ti.com Figure 58. Error, Reset, and Special Event Interrupt Condition Routing Registers Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h) 12 11 Reserved Error, Reset, & Special Event ICRR 2 (ERR_RST_EVNT_ICRR2) (Address Offset 02F4h) 12 11 ICR11 R/W-0000 Error, Reset, and Special Event ICRR 3 (ERR_RST_EVNT_ICRR3) (Address Offset 02F8h) LEGEND: R/W = Read/Write;...
Page 98: Interrupt Sources Assigned To Isdr Bits
Interrupt Conditions each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register.
Page 99: Interrupt Generation
www.ti.com Figure 61. Example Diagram of Interrupt Status Decode Register Mapping The following are suggestions for minimizing the number of register reads to identifying the interrupt source: Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a single read of the decode register.
Page 100: Interrupt Handling
Interrupt Conditions immediately starts down-counting each time the CPU writes these registers. When the rate control counter register is written, and the counter value reaches zero (note that the CPU may write zero immediately for a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the corresponding ICSR register bits are set (or become set after the zero count is reached).
Page 101 www.ti.com Interrupt Handler temp1 = SRIO_REGS->TX_CPPI_ICSR; if ((temp1 & 0x00000001) == 0x00000001) SRIO_REGS->Queue0_TXDMA_CP = (int )TX_DESCP0_0; temp2 = SRIO_REGS->RX_CPPI_ICSR; if ((temp2 & 0x00000001) == 0x00000001) SRIO_REGS->Queue0_RXDMA_CP = (int )RX_DESCP0_0; SRIO_REGS->DOORBELL0_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL1_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL2_ICCR=0xFFFFFFFF; SRIO_REGS->DOORBELL3_ICCR=0xFFFFFFFF; SRIO_REGS->INTDST0_Rate_CNTL=1; SPRUE13A – September 2006 Submit Documentation Feedback Interrupt Conditions Serial RapidIO (SRIO)
Page 102: Srio Registers
SRIO Registers SRIO Registers Introduction Table 40 lists the names and address offsets of the memory-mapped registers for the Serial RapidIO (SRIO) peripheral. See the device-specific data manual for the exact memory addresses of these registers. Offset Acronym 0000h 0004h 0020h PER_SET_CNTL 0030h...
Page 103 www.ti.com Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 011Ch SERDES_CFGTX3_CNTL 0120h SERDES_CFG0_CNTL 0124h SERDES_CFG1_CNTL 0128h SERDES_CFG2_CNTL 012Ch SERDES_CFG3_CNTL 0200h DOORBELL0_ICSR 0208h DOORBELL0_ICCR 0210h DOORBELL1_ICSR 0218h DOORBELL1_ICCR 0220h DOORBELL2_ICSR 0228h DOORBELL2_ICCR 0230h DOORBELL3_ICSR 0238h DOORBELL3_ICCR 0240h RX_CPPI_ICSR 0248h RX_CPPI_ICCR 0250h TX_CPPI_ICSR 0258h...
Page 104 SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 030Ch INTDST3_DECODE 0310h INTDST4_DECODE 0314h INTDST5_DECODE 0318h INTDST6_DECODE 031Ch INTDST7_DECODE 0320h INTDST0_RATE_CNTL 0324h INTDST1_RATE_CNTL 0328h INTDST2_RATE_CNTL 032Ch INTDST3_RATE_CNTL 0330h INTDST4_RATE_CNTL 0334h INTDST5_RATE_CNTL 0338h INTDST6_RATE_CNTL 033Ch INTDST7_RATE_CNTL 0400h LSU1_REG0 0404h LSU1_REG1 0408h LSU1_REG2...
Page 105 www.ti.com Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 0504h QUEUE1_TXDMA_HDP 0508h QUEUE2_TXDMA_HDP 050Ch QUEUE3_TXDMA_HDP 0510h QUEUE4_TXDMA_HDP 0514h QUEUE5_TXDMA_HDP 0518h QUEUE6_TXDMA_HDP 051Ch QUEUE7_TXDMA_HDP 0520h QUEUE8_TXDMA_HDP 0524h QUEUE9_TXDMA_HDP 0528h QUEUE10_TXDMA_HDP 052Ch QUEUE11_TXDMA_HDP 0530h QUEUE12_TXDMA_HDP 0534h QUEUE13_TXDMA_HDP 0538h QUEUE14_TXDMA_HDP 053Ch QUEUE15_TXDMA_HDP 0580h QUEUE0_TXDMA_CP 0584h...
Page 106 SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 063Ch QUEUE15_RXDMA_HDP 0680h QUEUE0_RXDMA_CP 0684h QUEUE1_RXDMA_CP 0688h QUEUE2_RXDMA_CP 068Ch QUEUE3_RXDMA_CP 0690h QUEUE4_RXDMA_CP 0694h QUEUE5_RXDMA_CP 0698h QUEUE6_RXDMA_CP 069Ch QUEUE7_RXDMA_CP 06A0h QUEUE8_RXDMA_CP 06A4h QUEUE9_RXDMA_CP 06A8h QUEUE10_RXDMA_CP 06ACh QUEUE11_RXDMA_CP 06B0h QUEUE12_RXDMA_CP 06B4h QUEUE13_RXDMA_CP 06B8h QUEUE14_RXDMA_CP...
Page 107 www.ti.com Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 0838h RXU_MAP_L7 083Ch RXU_MAP_H7 0840h RXU_MAP_L8 0844h RXU_MAP_H8 0848h RXU_MAP_L9 084Ch RXU_MAP_H9 0850h RXU_MAP_L10 0854h RXU_MAP_H10 0858h RXU_MAP_L11 085Ch RXU_MAP_H11 0860h RXU_MAP_L12 0864h RXU_MAP_H12 0868h RXU_MAP_L13 086Ch RXU_MAP_H13 0870h RXU_MAP_L14 0874h RXU_MAP_H14 0878h...
Page 108 SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 08F0h RXU_MAP_L30 08F4h RXU_MAP_H30 08F8h RXU_MAP_L31 08FCh RXU_MAP_H31 0900h FLOW_CNTL0 0904h FLOW_CNTL1 0908h FLOW_CNTL2 090Ch FLOW_CNTL3 0910h FLOW_CNTL4 0914h FLOW_CNTL5 0918h FLOW_CNTL6 091Ch FLOW_CNTL7 0920h FLOW_CNTL8 0924h FLOW_CNTL9 0928h FLOW_CNTL10 092Ch FLOW_CNTL11...
Page 109 www.ti.com Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 117Ch SP1_CTL 1180h SP2_LM_REQ 1184h SP2_LM_RESP 1188h SP2_ACKID_STAT 1198h SP2_ERR_STAT 119Ch SP2_CTL 11A0h SP3_LM_REQ 11A4h SP3_LM_RESP 11A8h SP3_ACKID_STAT 11B8h SP3_ERR_STAT 11BCh SP3_CTL 2000h ERR_RPT_BH 2008h ERR_DET 200Ch ERR_EN 2010h H_ADDR_CAPT 2014h ADDR_CAPT 2018h...
Page 110 SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym 2100h SP3_ERR_DET 2104h SP3_RATE_EN 2108h SP3_ERR_ATTR_CAPT_DBG0 210Ch SP3_ERR_CAPT_DBG1 2110h SP3_ERR_CAPT_DBG2 2114h SP3_ERR_CAPT_DBG3 2118h SP3_ERR_CAPT_DBG4 2128h SP3_ERR_RATE 212Ch SP3_ERR_THRESH 12000h SP_IP_DISCOVERY_TIMER 12004h SP_IP_MODE 12008h IP_PRESCAL 12010h SP_IP_PW_IN_CAPT0 12014h SP_IP_PW_IN_CAPT1 12018h SP_IP_PW_IN_CAPT2 1201Ch SP_IP_PW_IN_CAPT3...
Page 111: Peripheral Identification Register (Pid)
www.ti.com Peripheral Identification Register (PID) The peripheral identification register (PID) is a read-only register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. Writes have no effect to this register. The values are hard coded and will not change from their reset state. The peripheral ID register (PID) is shown in Figure 63.
Page 112: Peripheral Control Register (Pcr)
SRIO Registers Peripheral Control Register (PCR) The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior during emulation halts.
Page 113: Peripheral Settings Control Register (Per_Set_Cntl)
www.ti.com Peripheral Settings Control Register (PER_SET_CNTL) The peripheral settings control register (PER_SET_CNTL) is shown in Table 43. For additional programming information, see Figure 65. Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h) Reserved Reserved TX_PRI1_WM TX_PRI0_WM R/W-02h R/W-03h PRESCALER_SELECT R/W-0 LEGEND: R/W = Read/Write;...
Page 114 SRIO Registers Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Field 17–15 TX_PRI1_WM 14–12 TX_PRI0_WM 11–9 CBA_TRANS_PRI 1X_MODE 7–4 PRESCALER_SELECT Serial RapidIO (SRIO) Value Description 000b–111b Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI. This is valid for all ports in 1x mode only.
Page 115 www.ti.com Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Field ENPLL4 ENPLL3 ENPLL2 ENPLL1 SPRUE13A – September 2006 Submit Documentation Feedback Value Description Not used. Should always be programmed as "0". See enable SERDES PLL. Not used. Should always be programmed as "0". See enable SERDES PLL.
Page 116: Peripheral Global Enable Register (Gbl_En)
SRIO Registers Peripheral Global Enable Register (GBL_EN) GBL_EN is implemented with a single enable bit for the entire SRIO peripheral. This bit is logically ORed with the reset input to the module and is fanned out to all logical blocks within the peripheral. GBL_EN is shown in Figure 66 and described in...
Page 117: Peripheral Global Enable Status Register (Gbl_En_Stat)
www.ti.com Peripheral Global Enable Status Register (GBL_EN_STAT) The peripheral global enable status register (GBL_EN_STAT) is shown in Table 45. For additional programming information, see Figure 67. Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h BLK6_EN_ BLK5_EN_ BLK4_EN_ STAT STAT STAT LEGEND: R = Read only;...
Page 118 SRIO Registers Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued) Field BLK0_EN_STAT GBL_EN_STAT Serial RapidIO (SRIO) Value Description Block 0 enable status. Logical block 0 is the set of memory-mapped registers (MMRs) for the SRIO peripheral. Logical block 0 is in reset with its clock off. Logical block 0 is enabled with its clock running.
Page 119: Block N Enable Register (Blkn_En)
www.ti.com Block n Enable Register (BLKn_EN) There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in shown in Figure 68 and described in Section 2.3.10.
Page 120: Block N Enable Status Register (Blkn_En_Stat)
SRIO Registers Block n Enable Status Register (BLKn_EN_STAT) There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in (BLKn_EN_STAT) is shown in information, see Section 2.3.10.
Page 121: Rapidio Deviceid1 Register (Deviceid_Reg1)
www.ti.com RapidIO DEVICEID1 Register (DEVICEID_REG1) The RapidIO DEVICEID1 register (DEVICEID_REG1) is shown in Figure 70. RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) Reserved R-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 50. RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions Field Value 31–24...
Page 122: Rapidio Deviceid2 Register (Deviceid_Reg2)
SRIO Registers 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in additional programming information, see Figure 71. RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084) Reserved R-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 51.
Page 123: Packet Forwarding Register N For 16-Bit Device Ids (Pf_16B_Cntln)
www.ti.com 5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) There are four of these registers (see 16-bit DeviceIDs is shown in information, see Section 2.3.15 Register PF_16B_CNTL0 PF_16B_CNTL1 PF_16B_CNTL2 PF_16B_CNTL3 Figure 72. Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) 16BIT_DEVID_UP_BOUND R/W-FFFFh LEGEND: R/W = Read/Write;...
Page 124: Packet Forwarding Register N For 8-Bit Device Ids (Pf_8B_Cntln)
SRIO Registers 5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) There are four of these registers (see 16-bit DeviceIDs is shown in Section 2.3.15 and and Register PF_8B_CNTL0 PF_8B_CNTL1 PF_8B_CNTL2 PF_8B_CNTL3 Figure 73. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) LEGEND: R/W = Read/Write;...
Page 125: Serdes Receive Channel Configuration Register N (Serdes_Cfgrxn_Cntl)
www.ti.com 5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) There are four of these registers, to support four ports (see ). The general form for a SERDES receive channel configuration register is summarized by complete explanation of the programming of these registers. Table 56.
Page 126 SRIO Registers Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Field 15–14 13–12 ALIGN Reserved 10–8 TERM INVPAIR 6–5 RATE 4–2 BUSWIDTH Reserved ENRX CFGRX[22–19] 0000b 0001b 001xb 01xxb Serial RapidIO (SRIO) Descriptions (continued) Value Description Loss of signal. Enables loss of signal detection with 2 selectable thresholds. Disabled.
Page 127 www.ti.com CFGRX[22–19] 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b SPRUE13A – September 2006 Submit Documentation Feedback Table 58. EQ Bits (continued) Low Freq Gain Zero Freq (at e Adaptive SRIO Registers (min)) 1084MHz 805MHz 573MHz 402MHz 304MHz 216MHz 156MHz 135MHz Serial RapidIO (SRIO)
Page 128: Serdes Transmit Channel Configuration Register N (Serdes_Cfgtxn_Cntl)
SRIO Registers 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) There are four of these registers, to support four ports (see transmit channel configuration register is summarized by a complete explanation of the programming for these registers. Table 59. SERDES_CFGTXn_CNTL Registers and the Associated Ports Register SERDES_CFGTX0_CNTL SERDES_CFGTX1_CNTL...
Page 129: De Bits Of Serdes_Cfgtxn_Cntl
www.ti.com Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Field Value ENTX Table 61. DE Bits of SERDES_CFGTXn_CNTL DE Bits 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Table 62. SWING Bits of SERDES_CFGTXn_CNTL SWING Bits SPRUE13A –...
Page 130: Serdes Macro Configuration Register N (Serdes_Cfgn_Cntl)
SRIO Registers 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) There are four of these registers, to support four ports (see transmit channel configuration register is summarized by a complete explanation of the programming of this register. Table 63. SERDES_CFGn_CNTL Registers and the Associated Ports Register SERDES_CFG0_CNTL SERDES_CFG1_CNTL...
Page 131 www.ti.com Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions Field Value 5–1 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01111b 1xxxxb ENPLL SPRUE13A – September 2006 Submit Documentation Feedback (continued) Description PLL multiply. Select PLL multiply factors between 4 and 60. Reserved 12.5x Reserved...
Page 132: Doorbelln Interrupt Condition Status Register (Doorbelln_Icsr)
SRIO Registers 5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) The four doorbell interrupts are mapped to these registers (see interrupt condition status register is shown in programming information, see Register DOORBELL0_ICSR DOORBELL1_ICSR DOORBELL2_ICSR DOORBELL3_ICSR Figure 77. Doorbell n Interrupt Condition Status Register (DOORBELLn_ICSR) ICS15 ICS14 ICS13...
Page 133: Doorbelln Interrupt Condition Clear Register (Doorbelln_Iccr)
www.ti.com 5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) The four doorbells interrupts that are mapped are cleared by this register (see of a doorbell interrupt condition clear register is shown in additional programming information, see Register DOORBELL0_ICCR DOORBELL1_ICCR DOORBELL2_ICCR DOORBELL3_ICCR Figure 78.
Page 134: Rx Cppi Interrupt Status Register (Rx_Cppi_Icsr)
SRIO Registers 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) The bits in this register indicate any active interrupt requests from RX buffer descriptor queues. The RX CPPI interrupt status register (RX_CPPI_ICSR) is shown in additional programming information, see Figure 79. RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h ICS15 ICS14 ICS13...
Page 135: Rx Cppi Interrupt Clear Register (Rx_Cppi_Iccr)
www.ti.com 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) This register is used to clear bits in RX_CPPI_ICSR to acknowledge interrupts from the RX buffer descriptor queues. The RX CPPI interrupt clear register (RX_CPPI_ICCR) is shown in described in Table 70. For additional programming information, see Figure 80.
Page 136: Tx Cppi Interrupt Status Register (Tx_Cppi_Icsr)
SRIO Registers 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) The bits in this register indicate any active interrupt requests from TX buffer descriptor queues. TX_CPPI_ICSR is shown in Figure 81. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h ICS15 ICS14 ICS13...
Page 137: Tx Cppi Interrupt Clear Register (Tx_Cppi_Iccr)
www.ti.com 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer descriptor queues. TX_CPPI_ICCR is shown in Figure 82. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h ICC15 ICC14 ICC13...
Page 138: Lsu Interrupt Condition Status Register (Lsu_Icsr)
SRIO Registers 5.22 LSU Interrupt Condition Status Register (LSU_ICSR) Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt condition for a particular LSU. LSU_ICSR is shown in programming information, see Figure 83. LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h <--------------------------------- Bits for LSU4 --------------------------------->...
Page 139 www.ti.com Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Field Value Description ICS19 LSU3 interrupt condition not detected. LSU3 interrupt condition detected. Transaction was not sent due to unsupported transaction type or invalid field encoding. ICS18 LSU3 interrupt condition not detected. LSU3 interrupt condition detected.
Page 140 SRIO Registers Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Field Value Description ICS1 LSU1 interrupt condition not detected. LSU1 interrupt condition detected. Non-posted transaction received ERROR response, or error in response payload. ICS0 LSU1 interrupt condition not detected. LSU1 interrupt condition detected.
Page 141: Lsu Interrupt Condition Clear Register (Lsu_Iccr)
www.ti.com 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) Setting a bit in this register clears the corresponding bit in LSU_ICSR, to acknowledge the interrupt. LSU_ICCR is shown in Figure 84 Section 4.3.3. Figure 84. LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h <--------------------------------- Bits for LSU4 --------------------------------->...
Page 142: 5.24 Error, Reset, And Special Event Interrupt Condition Status Register
SRIO Registers 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Each of the nonreserved bits in this register indicate the status of a particular interrupt condition in one or more of the SRIO ports. ERR_RST_EVNT_ICSR is shown in additional programming information, see Figure 85.
Page 143: 5.25 Error, Reset, And Special Event Interrupt Condition Clear Register
www.ti.com 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field of ERR_RST_EVNT_ICCR are shown in information, see Section 4.3.4. Figure 86. Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address Offset 0278h Reserved ICC11...
Page 144: Doorbelln_Icrr2)
SRIO Registers 5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests from the associated doorbell ICSR to user-selected interrupt destinations. Each of the four doorbells can be mapped to these registers (see field of either register.
Page 145: Rx Cppi Interrupt Condition Routing Registers (Rx_Cppi_Icrr And Rx_Cppi_Icrr2)
www.ti.com 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) Figure 88 Table 79 summarize the ICRRs for the RXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 = 0010b in RX_CPPI_ICRR, the interrupt request from RX buffer descriptor queue 6 is sent to interrupt destination 2.
Page 146: Tx Cppi Interrupt Condition Routing Registers (Tx_Cppi_Icrr And Tx_Cppi_Icrr2)
SRIO Registers 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) Figure 89 Table 80 summarize the ICRRs for the TXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR, the interrupt request from TX buffer descriptor queue 6 is sent to interrupt destination 3.
Page 147: Lsu Interrupt Condition Routing Registers (Lsu_Icrr0-Lsu_Icrr3)
www.ti.com 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) Figure 90 shows the ICRRs for the LSU interrupt requests, and an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_ICSR to interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1 has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0.
Page 148: Lsu Interrupt Condition Routing Register Field Descriptions
SRIO Registers Table 81. LSU Interrupt Condition Routing Register Field Descriptions Field Value Description ICRx Interrupt condition routing. Routes the associated LSU interrupt request to one of eight interrupt (x = 0 to 31) destinations (INTDST0–INTDST7). Bits ICR0–ICR7 are for LSU1; bits ICR8–ICR15, for LSU2; bits ICR16–ICR23, for LSU3;...
Page 149: Error, Reset, And Special Event Interrupt Condition Routing Registers (Err_Rst_Evnt_Icrr, Err_Rst_Evnt_Icrr2, And Err_Rst_Evnt_Icrr3)
www.ti.com 5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) The ICRRs shown in Figure 91 destinations. For example, if ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EVNT_ICRR2, port 0 has generated an error interrupt request, and that request is routed to interrupt destination 1.
Page 150: Interrupt Status Decode Register (Intdstn_Decode)
SRIO Registers 5.31 Interrupt Status Decode Register (INTDSTn_DECODE) There are eight of these registers, one for each interrupt destination (see shown in Figure 92 and described in register only if the ICRRs routes the interrupt source to the corresponding physical interrupt. Each status decode bit is a logical OR of multiple interrupt sources that are mapped to the same bit.
Page 151: Interrupt Status Decode Register (Intdstn_Decode)
www.ti.com Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Field Value Description ISD27 No interrupt request routed to this bit. Interrupt request detected. Possible interrupt sources: TX buffer descriptor queue 4 (bit 4 of TX_CPPI_ICSR) RX buffer descriptor queue 4 (bit 4 of RX_CPPI_ICSR) ISD26 No interrupt request routed to this bit.
Page 152: Interrupt Status Decode Register (Intdstn_Decode)
SRIO Registers Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Field Value Description ISD15 No interrupt request routed to this bit. Interrupt request detected. Possible interrupt sources: Doorbell 0, bit 15 (bit 15 of DOORBELL0_ICSR) Doorbell 1, bit 15 (bit 15 of DOORBELL1_ICSR) Doorbell 2, bit 15 (bit 15 of DOORBELL2_ICSR) Doorbell 3, bit 15 (bit 15 of DOORBELL3_ICSR) ISD14...
Page 153 www.ti.com Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued) Field Value Description ISD7 No interrupt request routed to this bit. Interrupt request detected. Possible interrupt sources: Doorbell 0, bit 7 (bit 7 of DOORBELL0_ICSR) Doorbell 1, bit 7 (bit 7 of DOORBELL1_ICSR) Doorbell 2, bit 7 (bit 7 of DOORBELL2_ICSR) Doorbell 3, bit 7 (bit 7 of DOORBELL3_ICSR) ISD6...
Page 154: Intdstn Interrupt Rate Control Register (Intdstn_Rate_Cntl)
SRIO Registers 5.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) There are eight interrupt rate control registers, one for each interrupt destination (see Table 86 provide a general description for an interrupt rate control register. These registers are used to set the rate at which an interrupt can be generated for each interrupt destination. A write to one of the registers reloads a counter and immediately starts the counter decrementing.
Page 155: Lsun Control Register 0 (Lsun_Reg0)
www.ti.com 5.33 LSUn Control Register 0 (LSUn_REG0) There are four of these registers, one for each LSU (see control register 0 is shown in Section 2.3.3. Table 87. LSUn_REG0 Registers and the Associated LSUs Register LSU1_REG0 LSU2_REG0 LSU3_REG0 LSU4_REG0 Figure 94. LSUn Control Register 0 (LSUn_REG0) LEGEND: R/W = Read/Write;...
Page 156: Lsun Control Register 1 (Lsun_Reg1)
SRIO Registers 5.34 LSUn Control Register 1 (LSUn_REG1) There are four of these registers, one for each LSU (see ). This register's content is shown in and described in Table 90. For additional programming see Table 89. LSUn_REG1 Registers and the Associated LSUs Register LSU1_REG1 LSU2_REG1...
Page 157: Lsun Control Register 2 (Lsun_Reg2)
www.ti.com 5.35 LSUn Control Register 2 (LSUn_REG2) There are four of these registers, one for each LSU (see and described in Table 92. For additional programming see Table 91. LSUn_REG2 Registers and the Associated LSUs Register LSU1_REG2 LSU2_REG2 LSU3_REG2 LSU4_REG2 Figure 96.
Page 158: Lsun Control Register 3 (Lsun_Reg3)
SRIO Registers 5.36 LSUn Control Register 3 (LSUn_REG3) There are four of these registers, one for each LSU (see and described in Table 94. For additional programming see Table 93. LSUn_REG3 Registers and the Associated LSUs Register LSU1_REG3 LSU2_REG3 LSU3_REG3 LSU4_REG3 Figure 97.
Page 159: Lsun Control Register 4 (Lsun_Reg4)
www.ti.com 5.37 LSUn Control Register 4 (LSUn_REG4) There are four of these registers, one for each LSU (see and described in Table 96. For additional programming see Table 95. LSUn_REG4 Registers and the Associated LSUs Register LSU1_REG4 LSU2_REG4 LSU3_REG4 LSU4_REG4 Figure 98.
Page 160: Lsun Control Register 5 (Lsun_Reg5)
SRIO Registers 5.38 LSUn Control Register 5 (LSUn_REG5) There are four of these registers, one for each LSU (see and described in Table 98. For additional programming see Table 97. LSUn_REG5 Registers and the Associated LSUs Register LSU1_REG5 LSU2_REG5 LSU3_REG5 LSU4_REG5 Figure 99.
Page 161: Lsun Control Register 6 (Lsun_Reg6)
www.ti.com 5.39 LSUn Control Register 6 (LSUn_REG6) There are four of these registers, one for each LSU (see and described in Table 100. For additional programming see Table 99. LSUn_REG6 Registers and the Associated LSUs Register LSU1_REG6 LSU2_REG6 LSU3_REG6 LSU4_REG6 Figure 100.
Page 162: Lsun Congestion Control Flow Mask Register (Lsun_Flow_Masks)
SRIO Registers 5.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) There are four of these registers, one for each LSU (see LSUn_FLOW_MASKS register are summarized by within each FLOW_MASK field are summarized by Section 2.3.8. Table 101. LSUn_FLOW_MASKS Registers and the Associated LSUs Register LSU1_FLOW_MASKS LSU2_FLOW_MASKS...
Page 163: Lsun Flow_Mask Fields
www.ti.com Table 103. LSUn FLOW_MASK Fields (continued) Field Value Description LSUn does not support Flow 8 from table entry LSUn supports Flow 8 from table entry LSUn does not support Flow 7 from table entry LSUn supports Flow 7 from table entry LSUn does not support Flow 6 from table entry LSUn supports Flow 6 from table entry LSUn does not support Flow 5 from table entry...
Page 164: Queue N Transmit Dma Head Descriptor Pointer Register (Queuen_Txdma_Hdp)
SRIO Registers 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) There are sixteen of these registers (see described in Table 105. For additional programming information, see Table 104. QUEUEn_TXDMA_HDP Registers Register QUEUE0_TXDMA_HDP QUEUE1_TXDMA_HDP QUEUE2_TXDMA_HDP QUEUE3_TXDMA_HDP QUEUE4_TXDMA_HDP QUEUE5_TXDMA_HDP QUEUE6_TXDMA_HDP QUEUE7_TXDMA_HDP QUEUE8_TXDMA_HDP QUEUE9_TXDMA_HDP...
Page 165: Queue N Transmit Dma Completion Pointer Register (Queuen_Txdma_Cp)
www.ti.com 5.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) There are sixteen of these registers (see described in Table 107. For additional programming information, see Register QUEUE0_TXDMA_CP QUEUE1_TXDMA_CP QUEUE2_TXDMA_CP QUEUE3_TXDMA_CP QUEUE4_TXDMA_CP QUEUE5_TXDMA_CP QUEUE6_TXDMA_CP QUEUE7_TXDMA_CP QUEUE8_TXDMA_CP QUEUE9_TXDMA_CP QUEUE10_TXDMA_CP QUEUE11_TXDMA_CP QUEUE12_TXDMA_CP QUEUE13_TXDMA_CP QUEUE14_TXDMA_CP QUEUE15_TXDMA_CP...
Page 166: Queue N Receive Dma Head Descriptor Pointer Register (Queuen_Rxdma_Hdp)
SRIO Registers 5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) There are sixteen of these registers (see described in Table 109. For additional programming information, see Table 108. QUEUEn_RXDMA_HDP Registers Register QUEUE0_RXDMA_HDP QUEUE1_RXDMA_HDP QUEUE2_RXDMA_HDP QUEUE3_RXDMA_HDP QUEUE4_RXDMA_HDP QUEUE5_RXDMA_HDP QUEUE6_RXDMA_HDP QUEUE7_RXDMA_HDP QUEUE8_RXDMA_HDP QUEUE9_RXDMA_HDP...
Page 167: Queue N Receive Dma Completion Pointer Register (Queuen_Rxdma_Cp)
www.ti.com 5.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) There are sixteen of these registers (see described in Table 111. For additional programming information, see Register QUEUE0_RXDMA_CP QUEUE1_RXDMA_CP QUEUE2_RXDMA_CP QUEUE3_RXDMA_CP QUEUE4_RXDMA_CP QUEUE5_RXDMA_CP QUEUE6_RXDMA_CP QUEUE7_RXDMA_CP QUEUE8_RXDMA_CP QUEUE9_RXDMA_CP QUEUE10_RXDMA_CP QUEUE11_RXDMA_CP QUEUE12_RXDMA_CP QUEUE13_RXDMA_CP QUEUE14_RXDMA_CP QUEUE15_RXDMA_CP...
Page 168: Transmit Queue Teardown Register (Tx_Queue_Tear_Down)
SRIO Registers 5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Each bit in this register corresponds to one of the 16 TX buffer descriptor queues. If a 1 is written to a bit, the teardown process is initiated for the associated queue. TX_QUEUE_TEAR_DOWN is shown in Figure 107 and described in Figure 107.
Page 169: Transmit Cppi Supported Flow Mask Registers (Tx_Cppi_Flow_Masks[0-7])
www.ti.com 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7]) Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues (see Table 113). Figure 108 Each bit of a flow mask selects or deselects a flow for the associated TX queue (see additional programming information, see Table 113.
Page 170: Transmit Cppi Supported Flow Mask Registers
SRIO Registers Figure 108. Transmit CPPI Supported Flow Mask Registers Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0) QUEUE1_FLOW_MASK R/W-FFh Transmit CPPI Supported Flow Mask Register 1 (TX_CPPI_FLOW_MASKS1) QUEUE3_FLOW_MASK R/W-FFh Transmit CPPI Supported Flow Mask Register 2 (TX_CPPI_FLOW_MASKS2) QUEUE5_FLOW_MASK R/W-FFh Transmit CPPI Supported Flow Mask Register 3 (TX_CPPI_FLOW_MASKS3) QUEUE7_FLOW_MASK R/W-FFh...
Page 171 www.ti.com Table 114. TX Queue n FLOW_MASK Field Descriptions (continued) Field Value Description FL12 Queue n does not support Flow 12 from table entry Queue n supports Flow 12 from table entry FL11 Queue n does not support Flow 11 from table entry Queue n supports Flow 11 from table entry FL10 Queue n does not support Flow 10 from table entry...
Page 172: Receive Queue Teardown Register (Rx_Queue_Tear_Down)
SRIO Registers 5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Each of this register's bits corresponds to one of the 16 RX buffer descriptor queues. If a 1 is written to a bit, the teardown process is started for the associated queue. RX_QUEUE_TEAR_DOWN is shown in Figure 110 and described in Figure 110.
Page 173: Receive Cppi Control Register (Rx_Cppi_Cntl)
www.ti.com 5.48 Receive CPPI Control Register (RX_CPPI_CNTL) Each bit in this register indicates whether the associated RX buffer descriptor queue must receive messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and described in Table 116.
Page 174: Transmit Cppi Weighted Round Robin Control Registers (Tx_Queue_Cntl[0-3])
SRIO Registers 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3]) The transmission order among TX buffer descriptor queues is based on the programmable weighted round-robin scheme explained in mappers to determine the order in which the queues are serviced and how many messages are handled in each queue during each time around the round-robin cycle.
Page 175: Transmit Cppi Weighted Round Robin Control Register Field Descriptions
www.ti.com Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions Field Pair Register[Bits] TX_Queue_Map0 TX_QUEUE_CNTL0[3–0] TX_QUEUE_CNTL0[7–4] TX_Queue_Map1 TX_QUEUE_CNTL0[11–8] TX_QUEUE_CNTL0[15–12] TX_Queue_Map2 TX_QUEUE_CNTL0[19–16] TX_QUEUE_CNTL0[23–20] TX_Queue_Map3 TX_QUEUE_CNTL0[27–24] TX_QUEUE_CNTL0[31–28] TX_Queue_Map4 TX_QUEUE_CNTL1[3–0] TX_QUEUE_CNTL1[7–4] TX_Queue_Map5 TX_QUEUE_CNTL1[11–8] TX_QUEUE_CNTL1[15–12] TX_Queue_Map6 TX_QUEUE_CNTL1[19–16] TX_QUEUE_CNTL1[23–20] TX_Queue_Map7 TX_QUEUE_CNTL1[27–24] TX_QUEUE_CNTL1[31–28] TX_Queue_Map8 TX_QUEUE_CNTL2[3–0] TX_QUEUE_CNTL2[7–4] SPRUE13A –...
Page 176 SRIO Registers Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions (continued) Field Pair Register[Bits] TX_Queue_Map9 TX_QUEUE_CNTL2[11–8] TX_QUEUE_CNTL2[15–12] TX_Queue_Map10 TX_QUEUE_CNTL2[19–16] TX_QUEUE_CNTL2[23–20] TX_Queue_Map11 TX_QUEUE_CNTL2[27–24] TX_QUEUE_CNTL2[31–28] TX_Queue_Map12 TX_QUEUE_CNTL3[3–0] TX_QUEUE_CNTL3[7–4] TX_Queue_Map13 TX_QUEUE_CNTL3[11–8] TX_QUEUE_CNTL3[15–12] TX_Queue_Map14 TX_QUEUE_CNTL3[19–16] TX_QUEUE_CNTL3[23–20] TX_Queue_Map15 TX_QUEUE_CNTL3[27–24] TX_QUEUE_CNTL3[31–28] Serial RapidIO (SRIO) Field Value Description...
Page 177: Mailbox To Queue Mapping Registers (Rxu_Map_Ln And Rxu_Map_Hn)
www.ti.com 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports simultaneously. Packets are handled sequentially in order of receipt. A block of 32 mappers directs the inbound messages to the appropriate RX queues.
Page 178 SRIO Registers Table 118. Mailbox to Queue Mapping Registers and the Associated RX Register RXU_MAP_L18 RXU_MAP_H18 RXU_MAP_L19 RXU_MAP_H19 RXU_MAP_L20 RXU_MAP_H20 RXU_MAP_L21 RXU_MAP_H21 RXU_MAP_L22 RXU_MAP_H22 RXU_MAP_L23 RXU_MAP_H23 RXU_MAP_L24 RXU_MAP_H24 RXU_MAP_L25 RXU_MAP_H25 RXU_MAP_L26 RXU_MAP_H26 RXU_MAP_L27 RXU_MAP_H27 RXU_MAP_L28 RXU_MAP_H28 RXU_MAP_L29 RXU_MAP_H29 RXU_MAP_L30 RXU_MAP_H30 RXU_MAP_L31 RXU_MAP_H31 Serial RapidIO (SRIO)
Page 179: Mailbox To Queue Mapping Register Pair
www.ti.com Figure 113. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 30 29 LETTER_MASK MAILBOX_MASK R/W-11 R/W-111111 Mailbox to Queue Mapping Register H n (RXU_MAP_H n ) 10 9 Reserved LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 119.
Page 180 SRIO Registers Table 120. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions (continued) Field 7–6 Reserved 5–2 QUEUE_ID PROMISCUOUS SEGMENT_MAPPING Serial RapidIO (SRIO) Value Description These read-only bits return 0s when read. 0–15 Queue identification number. This field selects which of the 16 RX buffer queues is associated with mapper n.
Page 181: Flow Control Table Entry Register N (Flow_Cntln)
www.ti.com 5.51 Flow Control Table Entry Register n (FLOW_CNTLn) There are sixteen of these registers (see Table 122. For additional programming information, see Register FLOW_CNTL0 FLOW_CNTL1 FLOW_CNTL2 FLOW_CNTL3 FLOW_CNTL4 FLOW_CNTL5 FLOW_CNTL6 FLOW_CNTL7 FLOW_CNTL8 FLOW_CNTL9 FLOW_CNTL10 FLOW_CNTL11 FLOW_CNTL12 FLOW_CNTL13 FLOW_CNTL14 FLOW_CNTL15 Figure 114.
Page 182: Device Identity Car (Dev_Id)
SRIO Registers 5.52 Device Identity CAR (DEV_ID) The device identity CAR (DEV_ID) is shown in effect to this register. The values are hard coded and will not change from their reset state. Figure 115. Device Identity CAR (DEV_ID) - Address Offset 1000h DEVICEIDENTITY R-0000h LEGEND: R = Read only;...
Page 183: Device Information Car (Dev_Info)
www.ti.com 5.53 Device Information CAR (DEV_INFO) The device information CAR (DEV_INFO) is shown in no effect to this register. The values are hard coded and will not change from their reset state. Figure 116. Device Information CAR (DEV_INFO) - Address Offset 1004h LEGEND: R = Read only;...
Page 184: Assembly Identity Car (Asbly_Id)
SRIO Registers 5.54 Assembly Identity CAR (ASBLY_ID) The assembly identity CAR (ASBLY_ID) is shown in no effect to this register. The values are hard coded and will not change from their reset state. Figure 117. Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h ASSY_IDENTITY R-0000h LEGEND: R = Read only;...
Page 185: Assembly Information Car (Asbly_Info)
www.ti.com 5.55 Assembly Information CAR (ASBLY_INFO) The assembly information CAR (ASBLY_INFO) is shown in register is used by SERDES vendor to designate endpoints among the various function blocks of registers. Writes have no effect to this register. The values are hard coded and will not change from their reset state.
Page 186: Processing Element Features Car (Pe_Feat)
SRIO Registers 5.56 Processing Element Features CAR (PE_FEAT) The processing element features CAR (PE_FEAT) is shown in Figure 119. Processing Element Features CAR (PE_FEAT) - Address Offset 1010h BRIDGE MEMORY PROCESSOR FLOW_ RETRANSMIT_ CONTROL_ SUPPRESS SUPPORT LEGEND: R = Read only; -n = Value after reset Table 127.
Page 187 www.ti.com Table 127. Processing Element Features CAR (PE_FEAT) Field Descriptions (continued) Field 2–0 EXTENDED_ADDRESSING_SUPPORT SPRUE13A – September 2006 Submit Documentation Feedback Value Description Indicates the number address bits supported by the PE both as a source and target of an operation. All PEs shall at minimum support 34 bit addresses.
Page 188: Source Operations Car (Src_Op)
SRIO Registers 5.57 Source Operations CAR (SRC_OP) The source operations CAR (SRC_OP) is shown in Figure 120. Source Operations CAR (SRC_OP) - Address Offset 1018h STREAM_ READ WRITE WRITE ATOMIC_ ATOMIC_ ATOMIC_ INCRMNT DCRMNT LEGEND: R = Read only; -n = Value after reset Table 128.
Page 189: Destination Operations Car (Dest_Op)
www.ti.com 5.58 Destination Operations CAR (DEST_OP) The destination operations CAR (DEST_OP) is shown in Figure 121. Destination Operations CAR (DEST_OP) - Address Offset 101Ch READ WRITE STREAM_WRITE ATOMIC_ ATOMIC_ ATOMIC_ INCRMNT DCRMNT LEGEND: R = Read only; -n = Value after reset Table 129.
Page 190: Processing Element Logical Layer Control Csr (Pe_Ll_Ctl)
SRIO Registers 5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL) The processing element logical layer control CSR (PE_LL_CTL) is shown in Table 130. Figure 122. Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 130.
Page 191: Local Configuration Space Base Address 0 Csr (Lcl_Cfg_Hbar)
www.ti.com 5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) The local configuration space base address 0 CSR (LCL_CFG_HBAR) is shown in described in Table 131. Figure 123. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset Reserved LEGEND: R = Read only;...
Page 192: Local Configuration Space Base Address 1 Csr (Lcl_Cfg_Bar)
SRIO Registers 5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) The local configuration space base address 1 CSR (LCL_CFG_BAR) is shown in described in Table 132. Figure 124. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset LEGEND: R = Read only;...
Page 193: Base Device Id Csr (Base_Id)
www.ti.com 5.62 Base Device ID CSR (BASE_ID) The base device ID CSR (BASE_ID) is shown in Figure 125. Base Device ID CSR (BASE_ID) - Address Offset 1060h Reserved R-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 133.
Page 194: Host Base Device Id Lock Csr (Host_Base_Id_Lock)
SRIO Registers 5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) See Section 2.4.2 of the RapidIO Common Transport Specification for a description of this register. It provides a lock function that is write-once/reset-able. The host base device ID lock CSR (HOST_BASE_ID_LOCK) is shown in Figure 126.
Page 195: Component Tag Csr (Comp_Tag)
www.ti.com 5.64 Component Tag CSR (COMP_TAG) The component Tag CSR (COMP_TAG) is shown in Figure 127. Component Tag CSR (COMP_TAG) - Address Offset 106Ch LEGEND: R/W = Read/Write; -n = Value after reset Table 135. Component Tag CSR (COMP_TAG) Field Descriptions Field 31–0 COMPONENT_TAG...
Page 196: 1X/4X Lp Serial Port Maintenance Block Header Register (Sp_Mb_Head)
SRIO Registers 5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) The 1x/4x LP_Serial port maintenance block header register (SP_MB_HEAD) is shown in described in Table 136. Figure 128. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address EF_PTR R-1000h LEGEND: R = Read only;...
Page 197: Port Link Time-Out Control Csr (Sp_Lt_Ctl)
www.ti.com 5.66 Port Link Time-Out Control CSR (SP_LT_CTL) The port link time-out control CSR (SP_LT_CTL) is shown in Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h TIMEOUT_VALUE R/W-FFFFFFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 137.
Page 198: Port Response Time-Out Control Csr (Sp_Rt_Ctl)
SRIO Registers 5.67 Port Response Time-Out Control CSR (SP_RT_CTL) The port response time-out control CSR (SP_RT_CTL) is shown in For additional programming information, see Figure 130. Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h TIMEOUT_VALUE RW-FFFFFFh LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 138.
Page 199: Port General Control Csr (Sp_Gen_Ctl)
www.ti.com 5.68 Port General Control CSR (SP_GEN_CTL) The port general control CSR (SP_GEN_CTL) is shown in Figure 131. Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch MASTER_ HOST DISCOVERED ENABLE R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 139.
Page 200: Port Link Maintenance Request Csr N (Spn_Lm_Req)
SRIO Registers 5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) Each of the four ports is supported by a register of this type (see Figure 132 and described in Table 140. SPn_LM_REQ Registers and the Associated Ports Register SP0_LM_REQ SP1_LM_REQ SP2_LM_REQ SP3_LM_REQ Figure 132.
Page 201: Port Link Maintenance Response Csr N (Spn_Lm_Resp)
www.ti.com 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) Each of the four ports is supported by a register of this type (see response CSR n (SPn_LM_RESP) is shown in Table 142. SPn_LM_RESP Registers and the Associated Ports Register SP0_LM_RESP SP1_LM_RESP SP2_LM_RESP SP3_LM_RESP...
Page 202: Port Local Ackid Status Csr N (Spn_Ackid_Stat)
SRIO Registers 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) Each of the four ports is supported by a register of this type (see CSR n (SPn_ACKID_STAT) is shown in Table 144. SPn_ACKID_STAT Registers and the Associated Ports Register SP0_ACKID_STAT SP1_ACKID_STAT SP2_ACKID_STAT SP3_ACKID_STAT...
Page 203: Port Error And Status Csr N (Spn_Err_Stat)
www.ti.com 5.72 Port Error and Status CSR n (SPn_ERR_STAT) Each of the four ports is supported by a register of this type (see CSR n (SPn_ERR_STAT) is shown in Table 146. SPn_ERR_STAT Registers and the Associated Ports Register SP0_ERR_STAT SP1_ERR_STAT SP2_ERR_STAT SP3_ERR_STAT Figure 135.
Page 204 SRIO Registers Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Field 23–21 Reserved OUTPUT_RETRY_ENC OUTPUT_RETRIED OUTPUT_RETRY_STP OUTPUT_ERROR_ENC OUTPUT_ERROR_STP 15–11 Reserved INPUT_RETRY_STP INPUT_ERROR_ENC INPUT_ERROR_STP 7–5 Reserved PORT_WRITE_PND Reserved PORT_ERROR Serial RapidIO (SRIO) Value Description These read-only bits return 0s when read. Output retry condition encountered.
Page 205 www.ti.com Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued) Field PORT_OK PORT_UNINITIALIZED SPRUE13A – September 2006 Submit Documentation Feedback Value Description Port OK. This bit is a read-only bit. Port not-OK condition Port OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device.
Page 206: Port Control Csr N (Spn_Ctl)
SRIO Registers 5.73 Port Control CSR n (SPn_CTL) Each of the four ports is supported by a register of this type (see (SPn_CTL) is shown in Figure 136 are 2 registers that need to be programmed. The SP_IP_MODE (offset 0x12004) bits 31-30 are set to be 1x/4p or 4 ports (1x mode each).
Page 207 www.ti.com Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Field 26–24 PORT_WIDTH_OVERRIDE PORT_DISABLE OUTPUT_PORT_ENABLE INPUT_PORT_ENABLE ERROR_CHECK_DISABLE MULTICAST_PARTICIPANT 18–4 Reserved STOP_PORT_FLD_ENC_ENABLE DROP_PACKET_ENABLE PORT_LOCKOUT SPRUE13A – September 2006 Submit Documentation Feedback Value Description Port width override. This read-only field is available as a software means to override the hardware width.
Page 208 SRIO Registers Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued) Field PORT_TYPE Serial RapidIO (SRIO) Value Description Port type. This read-only bit indicates that the port is a serial port rather than a parallel port. www.ti.com SPRUE13A – September 2006 Submit Documentation Feedback...
Page 209: Error Reporting Block Header Register (Err_Rpt_Bh) - Address Offset 2000H
www.ti.com 5.74 Error Reporting Block Header Register (ERR_RPT_BH) The Error Reporting Block Header Register (ERR_RPT_BH) is shown in Table 150. Figure 137. Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h EF_PTR R-0000h LEGEND: R = Read only; -n = Value after reset Table 150.
Page 210: Logical/Transport Layer Error Detect Csr (Err_Det) - Address Offset 2008H
SRIO Registers 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) This register allows for the detection of logical/transport layer errors. The detectable errors are captured in the fields shown in Figure 138 Section 3 Figure 138. Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008h IO_ERR_ MSG_ERR_ Reserved...
Page 211 www.ti.com Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Field MSG_REQ_TIMEOUT PKT_RSPNS_TIMEOUT UNSOLICITED_RSPNS UNSUPPORTED_TRANS 21–8 Reserved RX_CPPI_SECURITY RX_IO_DMA_ACCESS 5–0 Reserved SPRUE13A – September 2006 Submit Documentation Feedback Value Description Message request timeout (endpoint device only) A timeout has not been detected by RXU. A timeout has been detected by the RXU.
Page 212: Logical/Transport Layer Error Enable Csr (Err_En) - Address Offset 200Ch
SRIO Registers 5.76 Logical/Transport Layer Error Enable CSR (ERR_EN) The logical/transport layer error enable CSR (ERR_EN) is shown in Table 152. Figure 139. Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch IO_ERR_ MSG_ERR_ Reserved RESP_ RESP_ (write 0) ENABLE ENABLE R/W-0...
Page 213 www.ti.com Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions (continued) Field PKT_RESP_TIMEOUT_ENABLE UNSOLICITED_RESP_ENABLE UNSUPPORTED_TRANS_ENABLE 21–8 Reserved RX_CPPI_SECURITY_ENABLE RX_IO_SECURITY_ENABLE 5–0 Reserved SPRUE13A – September 2006 Submit Documentation Feedback Value Description Packet response time-out error reporting enable Disable reporting of a packet response time-out error. Enable reporting of a packet response time-out error (endpoint device only).
Page 214: Logical/Transport Layer High Address Capture Csr (H_Addr_Capt) - Address Offset 2010H
SRIO Registers 5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) The logical/transport layer high address capture CSR (H_ADDR_CAPT) is shown in described in Table 153. Figure 140. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset LEGEND: R = Read only; -n = Value after reset Table 153.
Page 215: Logical/Transport Layer Address Capture Csr (Addr_Capt) - Address Offset 2014H
www.ti.com 5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) The logical/transport layer address capture CSR (ADDR_CAPT) is shown in Table 154. Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h ADDRESS_31_3 R-0000h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 154.
Page 216: Logical/Transport Layer Device Id Capture Csr (Id_Capt) - Address Offset 2018H
SRIO Registers 5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) The logical/transport layer device ID capture CSR (ID_CAPT) is shown in Table 155. Figure 142. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h MSB_DESTID R-00h MSB_SOURCEID R-00h LEGEND: R = Read only;...
Page 217: Logical/Transport Layer Control Capture Csr (Ctrl_Capt) - Address Offset 201Ch
www.ti.com 5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) The logical/transport layer control capture CSR (CTRL_CAPT) is shown in Table 156. Figure 143. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch 28 27 FTYPE R-0h LEGEND: R = Read only; -n = Value after reset Table 156.
Page 218: Port-Write Target Device Id Csr (Pw_Tgt_Id) - Address Offset 2028H
SRIO Registers 5.81 Port-Write Target Device ID CSR (PW_TGT_ID) The port-write target device ID CSR (PW_TGT_ID) is shown in For additional programming information, see Figure 144. Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h DEVICEID_MSB R/W-00h LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset Table 157.
Page 219: Port Error Detect Csr N (Spn_Err_Det)
www.ti.com 5.82 Port Error Detect CSR n (SPn_ERR_DET) Each of the four ports is supported by a register of this type (see (SPn_ERR_DET) is shown in Table 158. SPn_ERR_DET Registers and the Associated Ports Register SP0_ERR_DET SP1_ERR_DET SP2_ERR_DET SP3_ERR_DET Figure 145. Port Error Detect CSR n (SPn_ERR_DET) ERR_IMP_ SPECIFIC R/W-0...
Page 220 SRIO Registers Table 159. Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions (continued) Field RCVD_PKT_NOT_ACCPT PKT_UNEXPECTED_ACKID RCVD_PKT_WITH_BAD_CRC RCVD_PKT_OVER_276B 16–6 Reserved NON_OUTSTANDING_ACKID PROTOCOL_ERROR Reserved DELINEATION_ERROR UNSOLICITED_ACK_CNTL_SYM LINK_TIMEOUT Serial RapidIO (SRIO) Value Description Packet-not-accepted control symbol The port did not receive a packet-not-accepted acknowledge control symbol.
Page 221: Port Error Rate Enable Csr N (Spn_Rate_En)
www.ti.com 5.83 Port Error Rate Enable CSR n (SPn_RATE_EN) Each of the four ports is supported by a register of this type (see CSR n (SPn_RATE_EN) is shown in Table 160. SPn_RATE_EN Registers and the Associated Ports Register SP0_RATE_EN SP1_RATE_EN SP2_RATE_EN SP3_RATE_EN Figure 146.
Page 222 SRIO Registers Table 161. Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions (continued) Field PKT_UNEXPECTED_ACKID_EN RCVED_PKT_WITH_BAD_CRC_EN RCVED_PKT_OVER_276B_EN 16–6 Reserved NON_OUTSTANDING_ACKID_EN PROTOCOL_ERROR_EN Reserved DELINEATION_ERROR_EN UNSOLICITED_ACK_CNTL_SYM_EN LINK_TIMEOUT_EN Serial RapidIO (SRIO) Value Description Rate counting enable for packets with unexpected ackIDs Disable error rate counting of packets with unexpected/out-of-sequence ackIDs Enable error rate counting of packets with unexpected/out-of-sequence ackIDs.
Page 223: Port N Attributes Error Capture Csr 0 (Spn_Err_Attr_Capt_Dbg0)
www.ti.com 5.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Each of the four ports is supported by a register of this type (see ). The port n attributes error capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) is shown in Table 162. SPn_ERR_ATTR_CAPT_DBG0 Registers and the Associated Ports Register SP0_ERR_ATTR_CAPT_DBG0 SP1_ERR_ATTR_CAPT_DBG0...
Page 224: Port N Error Capture Csr 1 (Spn_Err_Capt_Dbg1)
SRIO Registers 5.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Each of the four ports is supported by a register of this type (see shown in Figure 148 and described in Table 164. SPn_ERR_CAPT_DBG1 Registers and the Associated Ports Register SP0_ERR_CAPT_DBG1 SP1_ERR_CAPT_DBG1 SP2_ERR_CAPT_DBG1...
Page 225: Port N Error Capture Csr 2 (Spn_Err_Capt_Dbg2)
www.ti.com 5.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Each of the four ports is supported by a register of this type (see shown in Figure 149 and described in Table 166. SPn_ERR_CAPT_DBG2 Registers and the Associated Ports Register SP0_ERR_CAPT_DBG2 SP1_ERR_CAPT_DBG2 SP2_ERR_CAPT_DBG2 SP3_ERR_CAPT_DBG2...
Page 226: Port N Error Capture Csr 3 (Spn_Err_Capt_Dbg3)
SRIO Registers 5.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Each of the four ports is supported by a register of this type (see shown in Figure 150 and described in Table 168. SPn_ERR_CAPT_DBG3 Registers and the Associated Ports Register SP0_ERR_CAPT_DBG3 SP1_ERR_CAPT_DBG3 SP2_ERR_CAPT_DBG3...
Page 227: Port N Error Capture Csr 4 (Spn_Err_Capt_Dbg4)
www.ti.com 5.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Each of the four ports is supported by a register of this type (see symbol error capture CSR 4 (SPn_ERR_CAPT_DBG4) is shown in Table 171. Table 170. SPn_ERR_CAPT_DBG4 Registers and the Associated Ports Register SP0_ERR_CAPT_DBG4 SP1_ERR_CAPT_DBG4...
Page 228: Port Error Rate Csr N (Spn_Err_Rate)
SRIO Registers 5.89 Port Error Rate CSR n (SPn_ERR_RATE) Each of the four ports is supported by a register of this type (see Figure 152 and described in Table 172. SPn_ERR_RATE Registers and the Associated Ports Register SP0_ERR_RATE SP1_ERR_RATE SP2_ERR_RATE SP3_ERR_RATE Figure 152.
Page 229: Port Error Rate Threshold Csr N (Spn_Err_Thresh)
www.ti.com 5.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Each of the four ports is supported by a register of this type (see ). The port error rate threshold CSR n (SPn_ERR_THRESH) is shown in Table 174. SPn_ERR_THRESH Registers and the Associated Ports Register SP0_ERR_THRESH SP1_ERR_THRESH...
Page 230: Port Ip Discovery Timer For 4X Mode Register (Sp_Ip_Discovery_Timer) - Address Offset 12000H
SRIO Registers 5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) The port IP discovery timer for 4x mode register (SP_IP_DISCOVERY_TIMER) is shown in and described in Table 176. Figure 154. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address 28 27 DISCOVERY_TIMER R/W-9h...
Page 231: Port Ip Mode Csr (Sp_Ip_Mode) - Address Offset 12004H
www.ti.com 5.92 Port IP Mode CSR (SP_IP_MODE) The port IP mode CSR (SP_IP_MODE) is shown in programming information, see Figure 155. Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h IDLE_ SP_MODE ERR_ FIFO_ BYPASS R/W-0 R/W-0 R/W-0 R/W-0 Reserved LEGEND: R/W = Read/Write;...
Page 232 SRIO Registers Table 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Field Value RST_EN RST_CS PW_EN PW_IRQ Serial RapidIO (SRIO) Description Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence Reset interrupt disable Reset interrupt enable Reset received status bit.
Page 233: Port Ip Prescaler Register (Ip_Prescal) - Address Offset 12008H
www.ti.com 5.93 Port IP Prescaler Register (IP_PRESCAL) The port IP prescaler register (IP_PRESCAL) is shown in register defines a prescaler for different frequencies of the DMA clock. The purpose of this register is to keep the timers of SP_LT_CTL (offset 01120h), SP0_ERR_RATE through SP3_ERR_RATE (offsets 02068h, 020A8h, 020E8, and 02128h), SP_IP_DISCOVERY_TIMER (offset 12000h), and SP0_SILENCE_TIMER through SP3_SILENCE_TIMER (offsets 14008h, 14108h, 14208h, and 14308h) within the same range for different frequencies of the DMA clock.
Page 234: Port-Write-In Capture Csrs
SRIO Registers 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers are shown in Figure 157. As can be seen in words of the payload. Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12010h Port-Write-In Capture CSR 1 (SP_IP_PW_IN_CAPT1) - Address Offset 12014h Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12018h Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 1201Ch...
Page 235: Spn_Rst_Opt Registers And The Associated Ports
www.ti.com 5.95 Port Reset Option CSR n (SPn_RST_OPT) Each of the four ports is supported by a register of this type (see Figure 158 and described in Table 180. SPn_RST_OPT Registers and the Associated Ports Register SP0_RST_OPT SP1_RST_OPT SP2_RST_OPT SP3_RST_OPT Figure 158.
Page 236: Spn_Ctl_Indep Registers And The Associated Ports
SRIO Registers 5.96 Port Control Independent Register n (SPn_CTL_INDEP) Each of the four ports is supported by a register of this type (see register n (SPn_CTL_INDEP) is shown in Table 182. SPn_CTL_INDEP Registers and the Associated Ports Register SP0_CTL_INDEP SP1_CTL_INDEP SP2_CTL_INDEP SP3_CTL_INDEP Figure 159.
Page 237 www.ti.com Table 183. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions (continued) Field DEBUG SEND_DBG_PKT ILL_TRANS_EN ILL_TRANS_ERR 19–18 Reserved MAX_RETRY_EN MAX_RETRY_ERR 15–8 MAX_RETRY_THR IRQ_EN IRQ_ERR 5–0 Reserved SPRUE13A – September 2006 Submit Documentation Feedback Value Description Mode of operation. Normal mode Debug mode.
Page 238: Spn_Silence_Timer Registers And The Associated Ports
SRIO Registers 5.97 Port Silence Timer n Register (SPn_SILENCE_TIMER) Each of the four ports is supported by a register of this type (see register (SPn_SILENCE_TIMER) is shown in Table 184. SPn_SILENCE_TIMER Registers and the Associated Ports Register SP0_SILENCE_TIMER SP1_SILENCE_TIMER SP2_SILENCE_TIMER SP3_SILENCE_TIMER Figure 160.
Page 239: Port Multicast-Event Control Symbol Request Register N (Spn_Mult_Evnt_Cs)
www.ti.com 5.98 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Each of the four ports is supported by a register of this type (see control symbol request register n (SPn_MULT_EVNT_CS) is shown in Table 187. Table 186. SPn_MULT_EVNT_CS Registers and the Associated Ports Register SP0_MULT_EVNT_CS SP1_MULT_EVNT_CS...
Page 240: Spn_Cs_Tx Registers And The Associated Ports
SRIO Registers 5.99 Port Control Symbol Transmit n Register (SPn_CS_TX) Each of the four ports is supported by a register of this type (see transmit n register (SPn_CS_TX) is shown in Table 188. SPn_CS_TX Registers and the Associated Ports Register SP0_CS_TX SP1_CS_TX SP2_CS_TX...
Page 241: Index
1x/4x LP serial port maintenance block header register 1x/4x mode selection field for ports 1X_MODE field of PER_SET_SNTL 2 MSBs of address for LSUn 4x/1x mode selection field for ports 4x mode data path in SRIO component block diagram discovery timer period field 8-bit/10-bit coding and decoding 8BIT_DEVID_LOW_BOUND field of PF_8B_CNTL 8BIT_DEVID_UP_BOUND field of PF_8B_CNTL...
Page 242 SRIO Registers bad CRC in control symbol at port n rate counting enable field status field bad CRC in packet at port n rate counting enable field status field bandwidth per differential pair based on 1x/4x LP-Serial specification BASE_DEVICEID field of BASE_ID BASE_ID base address registers for local configuration space 191, 192...
Page 243 at port n rate counting enable field status field bad CRC in control symbol at port n rate counting enable field status field detect 4 reset control symbols at port detect multicast-event control symbol at port enable interrupt if 4 reset control symbols received at port enable interrupt if multicast-event control symbol received at port...
Page 244 SRIO Registers DEV_INFO DEVICE_VENDORIDENTITY field of DEV_ID DEVICEID_MSB field of PW_TGT_ID DEVICEID_REG1 DEVICEID_REG2 device ID capture CSR for logical/transport errors device identity CAR DEVICEIDENTITY field of DEV_ID DEVICEID field of PW_TGT_ID device IDs base device ID for host PE base device ID for large common transport system base device ID for small common transport system device ID for port-write target disable base ID match requirement field for ports...
Page 245 ENPLL2 field of PER_SET_CNTL ENPLL3 field of PER_SET_CNTL ENPLL4 field of PER_SET_CNTL ENPLL field of SERDES_CFGn_CNTL ENRX field of SERDES_CFGRXn_CNTL ENTX field of SERDES_CFGTXn_CNTL eop field of RX buffer descriptor eop field of TX buffer descriptor eoq field of RX buffer descriptor eoq field of TX buffer descriptor EQ field of SERDES_CFGRXn_CNTL equalizer control field...
Page 246 SRIO Registers GBL_EN GBL_EN_STAT global enable bit global enable status bit global enabling/disabling of all logical blocks H_ADDR_CAPT head descriptor pointer field for RX queue n head descriptor pointer field for TX queue n header fields doorbell operation message request packet hexadecimal notational convention HOP_COUNT field of LSUn_REG5 host base device ID lock CSR...
Page 247 limiting which devices can access a mailbox line rate versus PLL output clock frequency LINK_STATUS field of SPn_LM_RESP LINK_TIMEOUT_EN field of SPn_RATE_EN LINK_TIMEOUT field of SPn_ERR_DET link maintenance command field for port n link-request control symbol generation register link responses acknowledge or link-response control symbol overdue at port n rate counting enable field...
Page 248 SRIO Registers MAX_RETRY_ERR field of SPn_CTL_INDEP MAX_RETRY_THR field of SPn_CTL_INDEP maximum packet size exceeded at port n rate counting enable field status field maximum retry error at port n reporting enable field reporting threshold field status field memory access unit. See MAU MEMORY field of PE_FEAT memory-mapped registers enable bit memory-mapped registers enable status bits...
Page 249 OUTBOUND_ACKID field of SPn_ACKID_STAT outbound credit outbound port number for packet forwarding out-of-order reception of message packets out-of-order responses during message-passing TX operation OUTPORTID field of LSUn_REG4 OUTPUT_DEGRD_ENC field of SPn_ERR_STAT OUTPUT_ERROR_ENC field of SPn_ERR_STAT OUTPUT_ERROR_STP field of SPn_ERR_STAT OUTPUT_FLD_ENC field of SPn_ERR_STAT OUTPUT_PKT_DROP field of SPn_ERR_STAT OUTPUT_PORT_ENABLE field of SPn_CTL OUTPUT_RETRIED field of SPn_ERR_STAT...
Page 250 SRIO Registers in SRIO component block diagram PID register pins/differential signals PKT_RESP_TIMEOUT_ENABLE field of ERR_EN PKT_RSPNS_TIMEOUT field of ERR_DET PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN PKT_UNEXPECTED_ACKID field of SPn_ERR_DET PLL block for SERDES 21, 28 PLL enable bit PLL multiply field for SERDES macro PLL output clock frequency versus line rate pointer to the next block in the data structure polarity inversion bit...
Page 251 PW_DIS field of SP_IP_MODE PW_EN field of SP_IP_MODE PW_IRQ field of SP_IP_MODE PW_TGT_ID PW_TIMER field of SP_IP_DISCOVERY_TIMER QUEUE_ID field of RXU_MAP_Hn QUEUEn_FLOW_MASK fields of TX_CPPI_FLOW_MASKS[0–7] QUEUEn_IN_ORDER fields of RX_CPPI_CNTL QUEUEn_RXDMA_CP QUEUEn_RXDMA_HDP QUEUEn_TEAR_DWN fields of RX_QUEUE_TEAR_DOWN QUEUEn_TEAR_DWN fields of TX_QUEUE_TEAR_DOWN QUEUEn_TXDMA_CP QUEUEn_TXDMA_HDP queue n receive DMA completion pointer register queue n receive DMA head descriptor pointer register...
Page 252 SRIO Registers for doorbell interrupt conditions for error, reset, and special event (port) interrupt conditions for LSU interrupt conditions RST_CS field of SP_IP_MODE RST_EN field of SP_IP_MODE rules for CPPI data traffic RX_CP field of QUEUEn_RXDMA_CP RX_CPPI_CNTL RX_CPPI_ICCR RX_CPPI_ICRR RX_CPPI_ICRR2 RX_CPPI_ICSR RX_CPPI_SECURITY_ENABLE field of ERR_EN RX_CPPI_SECURITY field of ERR_DET...
Page 253 SPn_ERR_CAPT_DBG1 SPn_ERR_CAPT_DBG2 SPn_ERR_CAPT_DBG3 SPn_ERR_CAPT_DBG4 SPn_ERR_DET SPn_ERR_RATE SPn_ERR_STAT SPn_ERR_THRESH SPn_LM_REQ SPn_LM_RESP SPn_MULT_EVNT_CS SPn_RATE_EN SPn_RST_OPT SPn_SILENCE_TIMER src_id field of RX buffer descriptor SRC_OP SRIO peripheral component block diagram data flow overview emulation halt behavior initialization example packets packet types peripheral block diagram pins/differential signals RapidIO features not supported RapidIO features supported...
Page 254 SRIO Registers transmitter enabling for SERDES macro introduction transmitter enable bit transport error handling and logging transport layer content in SRIO data stream definition in Load/Store module data flow diagram transport type field for message reception TRA. See transport layer TT field of FLOW_CNTLn tt field of RX buffer descriptor TT field of RXU_MAP_Hn...
Page 255 SRIO Registers Xoff SPRUE13A – September 2006 Index Submit Documentation Feedback...
Page 256: Important Notice
TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

Texas Instruments TMS320TCI648x User Manual

Preface

Overview

SRIO Functional Description

Logical/Transport Error Handling and Logging

Interrupt Conditions

SRIO Registers

Quick Links

Need help?

Questions and answers

Related Manuals for Texas Instruments TMS320TCI648x

Summary of Contents for Texas Instruments TMS320TCI648x