Texas Instruments TMS320C6455 User Manual page 5

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1 DDR2 Memory Controller Signal Descriptions
2 DDR2 SDRAM Commands
3 Truth Table for DDR2 SDRAM Commands
4 Addressable Memory Ranges
5 Bank Configuration Register Fields for Address Mapping
6 DDR2 Memory Controller FIFO Description
7 Refresh Urgency Levels
8 Device and DDR2 Memory Controller Reset Relationship
9 DDR2 SDRAM Mode Register Configuration
10 DDR2 SDRAM Extended Mode Register 1 Configuration
11 SDCFG Configuration
12 DDR2 Memory Refresh Specification
13 SDRFC Configuration
14 SDTIM1 Configuration
15 SDTIM2 Configuration
16 DMCCTL Configuration
17 DDR2 Memory Controller Registers
18 Module ID and Revision Register (MIDR) Field Descriptions
19 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
20 SDRAM Configuration Register (SDCFG) Field Descriptions
21 SDRAM Refresh Control Register (SDRFC) Field Descriptions
22 SDRAM Timing 1 Register (SDTIM1) Field Descriptions
23 SDRAM Timing 2 Register (SDTIM2) Field Descriptions
24 Burst Priority Register (BPRIO) Field Descriptions
25 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
SPRU970G - December 2005 - Revised June 2011
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Copyright © 2005-2011, Texas Instruments Incorporated
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