Table Of Contents - Texas Instruments TMS320C6455 User Manual

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Preface
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
1.4 Industry Standard(s) Compliance Statement
2 Peripheral Architecture
2.1 Clock Control
2.2 Memory Map
2.3 Signal Descriptions
2.4 Protocol Description(s)
2.5 Memory Width, Byte Alignment, and Endianness
2.6 Address Mapping
2.7 DDR2 Memory Controller Interface
2.8 Refresh Scheduling
2.9 Self-Refresh Mode
2.10 Reset Considerations
2.11 DDR2 SDRAM Memory Initialization
2.12 Interrupt Support
2.13 EDMA Event Support
2.14 Emulation Considerations
3 Using the DDR2 Memory Controller
3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM
3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
4 DDR2 Memory Controller Registers
4.1 Module ID and Revision Register (MIDR)
4.2 DDR2 Memory Controller Status Register (DMCSTAT)
4.3 SDRAM Configuration Register (SDCFG)
4.4 SDRAM Refresh Control Register (SDRFC)
4.5 SDRAM Timing 1 Register (SDTIM1)
4.6 SDRAM Timing 2 Register (SDTIM2)
4.7 Burst Priority Register (BPRIO)
4.8 DDR2 Memory Controller Control Register (DMCCTL)
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Revision History
SPRU970G - December 2005 - Revised June 2011
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Copyright © 2005-2011, Texas Instruments Incorporated
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Table of Contents