Loewe INDIVIDUAL SOUND PROJECTOR Service Manual page 64

DSP DIAGRAMS
All voltages are measured with a 10M /V DC electronic volt meter.
Components having special characteristics are marked and must be replaced
with parts having specifications equal to those originally installed.
Schematic diagram is subject to change without notice.
IC5: D60YA003BPYP225
Decoder
Digital Signal Processors
EMIF32 L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
McASP1 64K Bytes 4K Bytes Total
Total
McASP0
(4-Way)
C67x TM CPU
McBSP1
Instruction Fetch Control
Registers
McBSP0 Instruction Dispatch
Control
L2 Instruction Decode Logic
I2C1 Enhanced
Memory
DMA Data Path A Data Path B
Test
Controller
DA610:
I2C0 A Register File B Register File
(16 channel) 192K Bytes In-Circuit
Emulation
Timer 1 DA601:
Interrupt
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t
Control
Timer 0
GP1
L1D Cache
2-Way Set
GP0
R2 ROM
Associative
512K 4K Bytes Total
Bytes
HPI16
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
IC1-3: PQ1CZ41H2Z
Chopper regulators
V
V OUT
IN
1 2
Voltage ON/OFF
regulator circuit
ON/OFF
PWM COMP.
5
control
Q
Overcurrent
R
F/F
detection
circuit
S ERROR AMP. O
adj
4
V
ref
Overheat
detection
circuit
3
COM
IC18-20: YSS930-SZ
DSP
MICROPROCESSOR
INTERFACE
PROGRAM COEFFICIENT ADDRESS
RAM RAM RAM
CONTROL REGISTER 50 bit 1024 word 16 bit 1024 word 17 bit 256 word
CONTROL
SIGNALS
SDBCK
SDWCK
SDI0
SDO0
SDI1 SDO1
SDI2 SDO2
SDI3 SDO3
32 bit DSP Core
SDI4 SDO4
SDI5 SDO5
SDI6 SDO6
SDO7
SDI7
DSP INTERNAL
OPERATING CLOCK
CK (30.72~40.96MHz)
EXTERNAL RAM
INTERFACE
PLL
IC9: W9816G6CH-7
512K x 2 banks x 16 bits SDRAM
CLK 35
CLOCK
BUFFER
CKE 34
CONTROL COLUMN DECODER
CS 18
SIGNAL R
RAS 17 GENERATOR O
COMMAND W
CAS 16 DECODER
D CELL ARRAY
E
WE 15 BANK #0
C
O
D
E
R
A10 20
SENSE AMPLIFIER
MODE
A0 21
REGISTER
A3 24 ADDRESS
REFRESH DQ
BUFFER
COUNTER BUFFER
A4 27
A9 32
BA 19
REFRESH COLUMN
COLUMN DECODER
COUNTER COUNTER
R
O
W
D CELL ARRAY
E
BANK #1
C
O
D
E
R
SENSE AMPLIFIER
IC7: SN74LVC74APWR
Dual positive-edge-triggered D-type flip-flop
PRE
C
CLK C
C
Q
TG
C C C
C
D TG TG TG
Q
C C C
CLR
IC4: LC89057W-VF4D-E
Digital audio interface transceiver
EMPHA/UO AUDIO/VO INT CL CE CI XMODE
32 33 35 48 39 38 41
RXOUT 1 Microcontroller
Cbit, Ubit
37 DO
I/F
RX0 2
36 RERR
RX1 3
RX2 4
Demodulation
Input
Data
RX3 5 & 21 RDATA
Selector
Selector
RX4 Lock detect
8
RX5/VI 9
24 SDIN
RX6/UI
10
16 RMCK
LPF 13 PLL
17
RBCK
Clock
20 RLRCK
TMCK/PIO0 44
Selector
22 SBCK
Modulation
TBCK/PIO1 45
1/N
&
23 SLRCK
TLRCK/PIO2 46
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN XOUT XMCK CKST
IC22, 24: WM8728
24bit, 192kHz stereo DAC
MODE LATI2S SCKDSD SDIDEM MUTEB CSBIWL ZERO
1 6 20 19 18 17 1 5 5
8 VOUTR
BCKIN 3
LRCIN 1
DIN 2 11 VOUTL
12 VMID
4 10 7 14 1 3 9 6
MCLK AVDD DVDD VREFP VREFN AGND DGND
IC6: SN74AHC1G08DCKR IC8: SN74LV245APWR
2-input positive-AND gate Octal bus transceivers with 3-state outputs
DIR 1 20 Vcc
A 1 5 Vcc
B 2
A1 2 19 OE
GND 3 4 Y
A2 3 18 B1
A3 4 17 B2
2 DQ0
3 DQ1 5 16
A4 B3
5 DQ2
6 DQ3
A5 6 15 B4
8 DQ4
9 DQ5 A6 7 14 B5
11 DQ6
A7 8 13 B6
12 DQ7
39 DQ8
A8 9 12 B7
40 DQ9
42 DQ10
GND 10 11 B8
43 DQ11
45 DQ12
46 DQ13
48 DQ14
49 DQ15
14 LDQM
36 UDQM
IC12: D60YA003BPYP225
Decoder
EMIF32 L2 Cache/
Memory
1CLR VCC 4 Banks
1 14 McASP1
64K Bytes
Total
1D 2CLR
2 13 McASP0
(4-Way)
1CLK 3 12 2D
McBSP1
1PRE 4 11 2CLK
McBSP0
1Q 5 10 2PRE L2
I2C1 Enhanced
Memory
DMA
1Q 6 9 2Q
Controller DA610:
I2C0
(16 channel)
192K Bytes
GND 7 8 2Q
Timer 1
DA601:
64K Bytes
Timer 0
GP1
GP0
R2 ROM
512K
Bytes
HPI16
Total
IC16: W9864G6EH-7
1M x 4 banks x 16 bits SDRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
COLUMN DECODER COLUMN DECODER
WE
CELL ARRAY CELL ARRAY
A10 BANK #0 BANK #1
MODE
A0
REGISTER
SENSE AMPLIFIER SENSE AMPLIFIER
A9
A11
BS0
BS1
DQ0
DATA CONTROL DQ
CIRCUIT BUFFER
DQ15
REFRESH COLUMN
UDQM
COUNTER COUNTER
LDQM
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
IC23: S-29630AFJA
CMOS serial EEPROM
CS 1 8 VCC
VCC
Address
Memory array SK 2 7 NC
decoder GND
DI 3 6 TEST
DO 4 5 GND
Data register Output buffer DO
DI
Mode decode logic
CS
SK Clock generator
IC10: WM8738
24bit stereo ADC
6 4 11
AVDD 9
CONTROL
INTERFACE
CAP 5
AGND 10
ADC
RIN 7 2 SDATO
12 LRCLK
DIGITAL AUDIO
FILTERS INTERFACE
3 BCLK
13 MCLK
LIN 8 ADC
1 14
IC13: SN74AHC1G08DCKR
2-input AND gate
Digital Signal Processors
A 1 5 Vcc
L1P Cache
B 2
Direct Mapped
4K Bytes Total
GND 3 4 Y
C67x TM CPU
Instruction Fetch Control
Registers
Instruction Dispatch
Control
Instruction Decode Logic
Data Path A Data Path B
Test
A Register File B Register File
In-Circuit
Emulation
Interrupt
.L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t
Control
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
IC17: S29AL016D70TFI0
16M-bit COMS 3.0 volt-only boot sector flash memory
DQ0–DQ15 (A-1)
RY/ BY#
V
CC
Sect or Sw itc hes
V
SS
Erase V olt ag e In put/ Out put
RESET# Generat or
Buff ers
WE# State
Contr ol
BYTE#
Comm and
Regi st er
PGM Vo ltage
Generator
Data
Chip Enab le
Lat ch
Out put Enable STB
CE#
Logic
OE#
Y-Decoder Y- Gating
STB
V De te ct or Tim er
CC
X- Decoder Cell M atrix
A0– A19
IC21: SN74AHC1G08DCKR IC25: NJM2068MD-TE2
2-input AND gate
Dual operational amplifier
A 1 5 Vcc
OUT 1 1 8 +V CC
B 2
–IN 1 2 7 OUT 2
+ – + –
GND 3 4 Y
+IN 1 3 6 –IN 2
–V 4 5 +IN
CC 2
IC11: S29AL004D70TFI0
4M-bit COMS 3.0 volt-only boot sector flash memory
DQ0–DQ15 (A- 1)
RY/ BY#
V
CC
Sect or Sw itc hes
V
SS
Erase V olt ag e In put/ Out put
RESET# Generat or
Buff ers
WE# State
Contr ol
BYTE#
Comm and
Regi st er
PGM Vo ltage
Generator
Data
Chip Enab le
Out put Enable STB Lat ch
CE#
Logic
OE#
Y-Decoder Y- Gating
STB
V De te ct or Tim er
CC
X- Decoder Cell M atrix
A0– A17
POINT B-1 Pin 13 of IC26
POINT B-2 Pin 13 of IC26
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