Technical specifications
A.4 Specifications for the digital inputs and outputs
Technical data
Continuous permissible
voltage
Surge voltage
Logic 1 signal (min.)
Logic 0 signal (max.)
Isolation (field side to logic)
Isolation groups
Filter times
Number of inputs on
simultaneously
Cable length (meters)
NOTICE
When switching frequencies above 20 KHz, it is important that the digital inputs receive a
square wave. Consider the following options to improve the signal quality to the inputs:
Minimize the cable length
Change a driver from a sink only driver to a sinking and sourcing driver
Change to a higher quality cable
Reduce the circuit/components from 24 V to 5 V
Add an external load at the input
250
CPU, SM and SB
30 VDC, max.
35 VDC for 0.5 sec.
15 VDC at 2.5 mA
5 VDC at 1 mA
500 VAC for 1 minute
CPU: 1
SM 1221 DI 8: 2
SM 1221 DI 16: 4
SB 1223 DI 2: 1
SM 1223: 2
0.2, 0.4, 0.8, 1.6, 3.2, 6.4, and 12.8 ms
(selectable in groups of 4)
SM 1221 and SM 1223 DI 8: 8
SM 1221 and SM 1223 DI 16: 16
SB 1223 DI 2: 2
500 m shielded, 300 m unshielded
CPU: 50 m shielded for HSC
High-speed SB (200 KHz)
24 VDC SB: 28.8 VDC
5 VDC SB: 6 VDC
24 VDC SB: 35 VDC for 0.5 sec
5 VDC SB: 6 V
24 VDC SB: L+ minus 10 VDC at 2.9 mA
5 VDC SB: L+ minus 2.0 VDC at 5.1 mA
24 VDC SB: L+ minus 5 VDC at 1.4 mA
5 VDC SB: L+ minus 1.0 VDC at 2.2 mA
500 VAC for 1 minute
SB 1221 DI 4: 1
SB 1223 DI 2: 1
0.2, 0.4, 0.8, 1.6, 3.2, 6.4, and 12.8 ms
(selectable in groups of 4)
SB 1221 DI 4: 4
SB 1223 DI 2: 2
50 m shielded twisted pair
Manual, 11/2011, A5E02486774-04
Easy Book