12. 8-bit Timer/Counter0 with PWM
12.1
Overview
12.1.1
Definitions
Atmel ATmega16/32/64/M1/C1
90
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation. The main features are:
•
Two Independent Output Compare Units
•
Double Buffered Output Compare Registers
•
Clear Timer on Compare Match (Auto Reload)
•
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
•
Variable PWM Period
•
Frequency Generator
•
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
"8-bit Timer/Counter Register Description" on page
The PRTIM0 bit in
"Power Reduction Register" on page 42
Timer/Counter0 module.
Figure 12-1. 8-bit Timer/Counter Block Diagram
Timer/Counter
TCNTn
=
OCRnx
=
OCRnx
TCCRnA
Many register and bit references in this section are written in general form. A lower case "n"
replaces the Timer/Counter number, in this case 0. A lower case "x" replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
"Pin Descriptions" on page
count
clear
Control Logic
direction
clk
TOP
BOTTOM
=
=
0
Fixed
TOP
Values
TCCRnB
Figure
10. CPU accessible I/O Registers,
101.
must be written to zero to enable
Clock Select
Tn
Edge
Detector
( From Prescaler )
Waveform
Generation
Waveform
Generation
12-1. For the actual
TOVn
(Int.Req.)
Tn
OCnA
(Int.Req.)
OCnA
OCnB
(Int.Req.)
OCnB
7647H–AVR–03/12
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