Atmel ATmega32M1 Manual page 105

12.8.3 Timer/Counter Register – TCNT0
12.8.4 Output Compare Register A – OCR0A
12.8.5 Output Compare Register B – OCR0B
12.8.6 Timer/Counter Interrupt Mask Register – TIMSK0
7647H–AVR–03/12
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Bit 7
Read/Write R/W
Initial Value 0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
Bit 7
Read/Write R/W
Initial Value 0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
Bit 7
Read/Write R/W
Initial Value 0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
Bit 7
–
Read/Write R
Initial Value 0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
Atmel ATmega16/32/64/M1/C1
6 5 4
TCNT0[7:0]
R/W R/W R/W
0 0 0
6 5 4
OCR0A[7:0]
R/W R/W R/W
0 0 0
6 5 4
OCR0B[7:0]
R/W R/W R/W
0 0 0
6 5 4
– – –
R R R
0 0 0
3 2 1
R/W R/W R/W
0 0 0
3 2 1
R/W R/W R/W
0 0 0
3 2 1
R/W R/W R/W
0 0 0
3 2 1
– OCIE0B OCIE0A
R R/W R/W
0 0 0
0
TCNT0
R/W
0
0
OCR0A
R/W
0
0
OCR0B
R/W
0
0
TOIE0 TIMSK0
R/W
0
105