Digital Interface; J2: Serial Interface Pins - Texas Instruments ADS1256EVM-PDK User Manual

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Digital Interface

3.1 Serial Data Interface
The ADS1256EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J2. This header/socket provides access to the digital control and serial data pins of the
TSC. Consult Samtec at
options.
All logic levels on J2 are 3.3V CMOS, except for the I
Some pins on J2 have weak pullup resistors. These resistors provide default settings for many of the
control pins. Most pins on J2 correspond directly to ADS1256 pins. See the
for complete details on these pins.
Pin Number
J2.1
J2.2
J2.3
J2.4
J2.5
J2.6
J2.7
J2.8
J2.9
J2.10
J2.11
J2.12
J2.13
J2.14
J2.15
J2.16
J2.17
J2.18
J2.19
J2.20
3.2 GPIO
The ADS1256 has four general-purpose I/O (GPIO) pins. One of these pins can also be configured as a
buffered system clock output. This output is typically used to clock additional ADS1255/ADS1256 devices,
but can be used for other purposes as well. The GPIO pins for the ADS1256 are shown in
pins (from left to right) are D3 to D0.
SBAU090E – November 2003 – Revised November 2018
Submit Documentation Feedback
www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector
Table 2 describes the J2 serial interface pins.
Table 2. J2: Serial Interface Pins
Standard
Pin Name Name
— CNTL
— GPIO0
SCLK CLKX
DGND DGND
— CLKR
— GPIO1
CS FSX
— GPIO2
— FSR
DGND DGND
DIN DX
— GPIO3
DOUT DR
RESET GPIO4
DRDY INT
SCL SCL
EXTCLK TOUT
DGND DGND
SYNC/PDW GPIO5
N
SDA SDA
Copyright © 2003–2018, Texas Instruments Incorporated
2
C pins, which conform to 3.3V I
Direction Pulldown
— None Unused
— None Unused
Input None Serial clock input
I/O Power Digital ground
— None Unused
— None Unused
Input None Chip select (via J8)
— None Unused
— None Unused
I/O Power Digital ground
Input None Serial data input
— None Unused
Input None Serial data output
Input Yes Reset input (via J7)
Output None Data ready signal
2
I/O None I C clock line
Input None External system clock input
I/O Power Digital lround
Input Yes Synchronization and power
down control pin (via J6)
2
I/O None I C data line
ADS1256EVM and ADS1256EVM-PDK
Digital Interface
2
C rules.
ADS1256 product data sheet
Function
Figure 2. These
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