Espressif ESP8266 Technical Reference page 98

Address RegName Signal
0x0 UART_FIFO
rxfifo_rd_byte
0x4 UART_INT_RAW UART_INT_RAW
rxfifo_tout_int_raw
brk_det_int_raw
cts_chg_int_raw
dsr_chg_int_raw
rxfifo_ovf_int_raw
frm_err_int_raw
parity_err_int_raw
txfifo_empty_int_raw
rxfifo_full_int_raw
0x8 UART_INT_ST UART_INT_ST
rxfifo_tout_int_st
brk_det_int_st
cts_chg_int_st
dsr_chg_int_st
rxfifo_ovf_int_st
frm_err_int_st
parity_err_int_st
txfifo_empty_int_st
rxfifo_full_int_st
0xC UART_INT_ENA UART_INT_ENA
rxfifo_tout_int_ena
brk_det_int_ena
cts_chg_int_ena
dsr_chg_int_ena
rxfifo_ovf_int_ena
frm_err_int_ena
parity_err_int_ena
txfifo_empty_int_ena
rxfifo_full_int_ena
0x10 UART_INT_CLR UART_INT_CLR
rxfifo_tout_int_clr
brk_det_int_clr
cts_chg_int_clr
dsr_chg_int_clr
rxfifo_ovf_int_clr
frm_err_int_clr
parity_err_int_clr
txfifo_empty_int_clr
rxfifo_full_int_clr
0x14 UART_CLKDIV UART_CLKDIV
uart_clkdiv
0x18 UART_AUTOBAUD UART_AUTOBAUD
glitch_filt
autobaud_en
UART_ST UART_STATUS UART_STATUS
ATUS
txd
rtsn
dtrn
txfifo_cnt
rxd
ctsn
dsrn
rxfifo_cnt
0x20 UART_CONF0 UART_CONF0
uart_dtr_inv
uart_rts_inv
uart_txd_inv
uart_dsr_inv
uart_cts_inv
uart_rxd_inv
txfifo_rst
rxfifo_rst
tx_flow_en
uart_loopback
txd_brk
sw_dtr
sw_rts
stop_bit_num
bit_num
parity_en
parity
UART_CONF1
0x24 UART_CONF1 rx_tout_en
rx_tout_thrhd
rx_flow_en
rx_flow_thrhd
txfifo_empty_thrhd
rxfifo_full_thrhd
0x28 UART_LOWPULSE UART_LOWPULSE
lowpulse_min_cnt
0x2C UART_HIGHPULSE UART_HIGHPULSE
highpulse_min_cnt
0x30 UART_RXD_CNT
rxd_edge_cnt
0x78 UART_DATE uart_date
0x7C UART_ID uart_id
Appendix 3 UART Registers
BitPos Default SW(R/W) Description
[31:8] 24'h0 RO UART FIFO,length 128
[7:0] 8'b0 RO R/W share the same address
UART INTERRUPT RAW STATE
The interrupt raw bit for Rx time-out interrupt(depands on the
[8] 1'b0 RO
UART_RX_TOUT_THRHD)
[7] 1'b0 RO The interrupt raw bit for Rx byte start error
[6] 1'b0 RO The interrupt raw bit for CTS changing level
[5] 1'b0 RO The interrupt raw bit for DSR changing level
[4] 1'b0 RO The interrupt raw bit for rx fifo overflow
[3] 1'b0 RO The interrupt raw bit for other rx error
[2] 1'b0 RO The interrupt raw bit for parity check error
The interrupt raw bit for tx fifo empty interrupt(depands on
[1] 1'b0 RO
UART_TXFIFO_EMPTY_THRHD bits)
The interrupt raw bit for rx fifo full interrupt(depands on
[0] 1'b0 RO
UART_RXFIFO_FULL_THRHD bits)
UART INTERRUPT STATE
REGISTER UART_INT_RAW&UART_INT_ENA
[8] 1'b0 RO The interrupt state bit for Rx time-out event
[7] 1'b0 RO The interrupt state bit for rx byte start error
[6] 1'b0 RO The interrupt state bit for CTS changing level
[5] 1'b0 RO The interrupt state bit for DSR changing level
[4] 1'b0 RO The interrupt state bit for RX fifo overflow
[3] 1'b0 RO The interrupt state for other rx error
[2] 1'b0 RO The interrupt state bit for rx parity error
[1] 1'b0 RO The interrupt state bit for TX fifo empty
[0] 1'b0 RO The interrupt state bit for RX fifo full event
UART INTERRUPT ENABLE REGISTER
[8] 1'b0 R/W The interrupt enable bit for rx time-out interrupt
[7] 1'b0 R/W The interrupt enable bit for rx byte start error
[6] 1'b0 R/W The interrupt enable bit for CTS changing level
[5] 1'b0 R/W The interrupt enable bit for DSR changing level
[4] 1'b0 R/W The interrupt enable bit for rx fifo overflow
[3] 1'b0 R/W The interrupt enable bit for other rx error
[2] 1'b0 R/W The interrupt enable bit for parity error
[1] 1'b0 R/W The interrupt enable bit for tx fifo empty event
[0] 1'b0 R/W The interrupt enable bit for rx fifo full event
UART INTERRUPT CLEAR REGISTER
[8] 1'b0 WO Set this bit to clear the rx time-out interrupt
[7] 1'b0 WO Set this bit to clear the rx byte start interrupt
[6] 1'b0 WO Set this bit to clear the CTS changing interrupt
[5] 1'b0 WO Set this bit to clear the DSR changing interrupt
[4] 1'b0 WO Set this bit to clear the rx fifo over-flow interrupt
[3] 1'b0 WO Set this bit to clear other rx error interrupt
[2] 1'b0 WO Set this bit to clear the parity error interrupt
[1] 1'b0 WO Set this bit to clear the tx fifo empty interrupt
[0] 1'b0 WO Set this bit to clear the rx fifo full interrupt
UART CLK DIV REGISTER
[19:0] 20'h2B6 R/W BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
UART BAUDRATE DETECT REGISTER
[15:8] 8'h10 R/W
[7:1] 7'h0 RO
[0] 1'b0 R/W Set this bit to enable baudrate detect
UART STATUS REGISTER
[31] 8'h0 RO The level of the uart txd pin
[30] 1'b0 RO The level of uart rts pin
[29] 1'b0 RO The level of uart dtr pin
[28:14] 5'b0 RO
[23:16] 8'b0 RO Number of data in UART TX fifo
[15] 1'b0 RO The level of uart rxd pin
[14] 1'b0 RO The level of uart cts pin
[13] 1'b0 RO The level of uart dsr pin
[12:8] 5'b0 RO
[7:0] 8'b0 RO Number of data in uart rx fifo
UART CONFIG0(UART0 and UART1)
[24] 1'h0 R/W Set this bit to inverse uart dtr level
[23] 1'h0 R/W Set this bit to inverse uart rts level
[22] 1'h0 R/W Set this bit to inverse uart txd level
[21] 1'h0 R/W Set this bit to inverse uart dsr level
[20] 1'h0 R/W Set this bit to inverse uart cts level
[19] 1'h0 R/W Set this bit to inverse uart rxd level
[18] 1'h0 R/W Set this bit to reset uart tx fifo
[17] 1'h0 R/W Set this bit to reset uart rx fifo
[15] 1'b0 R/W Set this bit to enable uart tx hardware flow control
[14] 1'b0 R/W Set this bit to enable uart loopback test mode
[8] 1'b0 R/W RESERVED, DO NOT CHANGE THIS BIT
[7] 1'b0 R/W sw dtr
[6] 1'b0 R/W sw rts
[5:4] 2'd1 R/W Set stop bit: 1:1bit 2:1.5bits 3:2bits
[3:2] 2'd3 R/W Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
[1] 1'b0 R/W Set this bit to enable uart parity check
[0] 1'b0 R/W Set parity check: 0:even 1:odd
UART CONFIG1
[31] 1'b0 R/W Set this bit to enable rx time-out function
[30:24] 7'b0 R/W Config bits for rx time-out threshold,uint: byte,0-127
[23] 1'b0 R/W Set this bit to enable rx hardware flow control
[22:16] 7'h0 R/W The config bits for rx flow control threshold,0-127
[15] 1'b0 RO
[14:8] 7'h60 R/W The config bits for tx fifo empty threshold,0-127
[7] 1'b0 RO
[6:0] 7'h60 R/W The config bits for rx fifo full threshold,0-127
[19:0] 20'hFFFF RO used in baudrate detect
F
[19:0] 20'hFFFF RO used in baudrate detect
F
[9:0] 10'h0 RO used in baudrate detect
[31:0] 32'h0620 R/W UART HW INFO
00
[31:0] 32'h0500 R/W