I2S Module Description; Functional Overview; System Configuration; I2S Module Configuration - Espressif ESP8266 Technical Reference

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10.

10.1. Functional Overview

The I2S module of the ESP8266 contains a Tx (transport) unit and a Rx (receive) unit. Both
the Tx and the Rx unit have a three-wire interface that includes:
Clock line;
•
• Data line;
Channel selection line (the line for selecting the left or the right channel).
•
! Note:
The clock and data output will stop when 0 is written into the data line.
The transmission direction of the I2S module is shown in Table 10-1.
Clock line
Data line
Channel selection line
! Note:
Both the Tx and Rx unit have a separate FIFO, which has a depth of 128 and a width of 32 bits, and can be
visited by software directly. You can also make an automatic DMA operation to FIFO by the SLC module.
10.2. System Configuration
10.2.1. I2S Module Configuration
10.2.1.1.I2S Module Reset
Bits 0 ~ 3 in the I2SCONF register provide the software reset feature to the I2S. Write 1 and
then 0 to complete the reset operation. Different bits are used for:
Bit 0: I2S_TX_RESET
•
Bit 1: I2S_RX_RESET
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Bit 2: I2S_TX_FIFO_RESET
•
Bit 3: I2S_RX_FIFO_RESET
•
Espressif

I2S Module Description

Table 10-1. Transmission Direction of The I2S Module
output input
output
output
53 86 ! /!
Tx unit
output input
input
input
10. I2S Module Description
Rx unit
2016.05