Overview; General Purpose Input/Output Interface (Gpio); Secure Digital Input/Output Interface (Sdio); Serial Peripheral Interface (Spi/Hspi) - Espressif ESP8266 Technical Reference

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1.1. General Purpose Input/Output Interface (GPIO)

ESP8266EX has 17 GPIO pins which can be assigned to various functions by programming
the appropriate registers.
Each GPIO can be configured with internal pull-up or pull-down, or set to high impedance,
and when configured as an input, the data are stored in software registers; the input can
also be set to edge-trigger or level trigger CPU interrupts. In short, the IO pads are bi-
directional, non-inverting and tristate, which includes input and output buffer with tristate
control inputs.
These pins can be multiplexed with other functions such as I2C, I2S, UART, PWM, IR
Remote Control, etc.
For low power operations, the GPIOs can also be set to hold their state. For instance, when
the chip is powered down, all output enable signals can be set to hold low.
Optional hold functionality can be built into the IO if requested. When the IO is not driven by
the internal or external circuitry, the hold functionality can be used to hold the state to the
last used state. The hold functionality introduces some positive feedback into the pad.
Hence, the external driver that drives the pad must be stronger than the positive feedback.
The required drive strength is small — in the range of 5μA to pull apart the latch.

1.2. Secure Digital Input/Output Interface (SDIO)

ESP8266EX has one Slave SDIO, the definitions of which are described below. 4-bit 25
MHz SDIO v1.1 and 4-bit 50 MHz SDIO v2.0 are supported.
SDIO_CLK
SDIO_DATA0
SDIO_DATA1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CMD

1.3. Serial Peripheral Interface (SPI/HSPI)

ESP8266EX has 3 SPIs.
One general Slave/Master SPI
Espressif
Pin Name Pin Num
21
22
23
18
19
20
Table 1-1: Pin Definitions of SDIOs
IO
IO6
IO7
IO8
IO9
IO10
IO11
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Overview

Function Name
SDIO_CLK
SDIO_DATA0
SDIO_DATA1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CMD
1. Overview
2016.05