Link List Configuration - Espressif ESP8266 Technical Reference

!
Value
0
1
2
10.2.1.5.Clock Mode
in the I2SCONF:
Bits16 ~ 21 are the prescaler of the input clock (I2S_CLKM_DIV_NUM).
•
Bits 22 ~ 27 are the frequency divider of the communication clock signal
•
(I2S_BCK_DIV_NUM).
10.2.1.6.Other Configurations
Register I2SRXEOF_NUM sets the number of data to be received when the Rx FIFO
triggers the SLC transport (unit: 4 bytes).
See the definitions of i2s_reg.h in DEMO. Other instructions will be updated.
10.2.2. Link List Configuration
In the ESP8266, the DMA transfers the receive and transport packets in the SDIO to the
corresponding memory. The software will define the structure (or group) of the registration
list and cache space(s).
As shown in Figure 10-1, there is only one cache space and one registration list. Write the
first address of the cache and other information to the registration list, and then write the
first address of the registration list to the hardware register of the ESP8266. Therefore, the
DMA will automatically operate the SDIO and the cache space.
word 0
word 1
word 2
!
Field name
owner
Espressif
Dual-channel
Right channel
Left channel
owner eof sub_sof
Figure 10-1. Registration List
1'b0 Software operates the buffer of the current link. The MAC shouldn't use this bit.
1'b1 Hardware operates the buffer of the current link.
56 86 !
Description
5'b0
buf_ptr [31:0]
next_link_ptr [31:0]
Description
/!
10. I2S Module Description
length［11:0］ size［11:0］
2016.05