Espressif ESP8266 Technical Reference page 63

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10.2.1.2. I2S Module Start
Provide a running clock
To start the I2S module to transport or receive data, firstly you need to provide a running
clock for the I2S by invoking the system function below:
i2c_writeReg_ Mask_def (i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1)
Start the Tx module
Bit 8 in the I2SCONF register is used to start the Tx module.
In the master Tx mode, when bit 8 is 1 the Tx mode will output the clock signal, the
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left and right channel signals and data. The first frame data is 0, and then the FIFO
data will be shifted out.
- If no data is written into the the FIFO, the data line will remain 0.
- If the FIFO has transported all the written data and no new data is written in the
In the slave passive Tx mode, the Tx module will be started when it receives a clock
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signal from the Rx module.
Start the Rx module
Bit 9 in the I2SCONF register is used to start the Rx module. In the master receive mode:
When bit 9 is 1 the Rx mode will output the clock signal, and sample the data line
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and the channel selection line.
When bit 9 is 0, it will stop the clock signal transport.
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In the slave receive mode, it is prepared to receive any data from the master.
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10.2.1.3.Tx/Rx FIFO Mode
FIFO access mode
Bit 12 of I2S_FIFO_CONF defines the access mode of the FIFO.
When bit 12 is 1, the SLC will make a DMA operation to the FIFO. Direct access to
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the FIFO will be invalid.
When bit 12 is 0, the FIFO can be accessed directly by software.
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The default value of bit12 is 1.
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Tx FIFO mode
Bits 13 ~ 15 of I2S_FIFO_CONF are used to control the transport data format for
i2s_tx_fifo_mod.
Value
0
Espressif
FIFO, the data line will loop the last data in the FIFO.
16bits_per_channel full data (dual channel, FIFO data organisation, 16 bits data in the left
channel,16 bits data in the right channel, and 16 bits data in the left channel)
Description
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10. I2S Module Description
2016.05