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6.
6.1. Functional Overview
This protocol uses the ESP8266 slave mode to communicate with other processor's SPI
master. Signal line No.5 is used to implement this protocol. Apart from signal line No.4
needed for standard SPI, signal line No.1 is also needed to inform the master of the update
of the slave status register.
6.2. ESP8266 SPI Slave Protocol Format
6.2.1. SPI Slave Clock Polarity Configuration
Clock polarity of the master clock which communicates with the ESP8266 SPI slave should
be set to be low in the idle state, sampling for rising edge, and changing data for falling
edge. When it reads/writes 34 bytes at a time, or when it reads 2 bytes at a time to get
information of the slave status register, selection signal CS must be kept at low level. If CS
is pulled high when data is being sent, the slave interior status will be reset.
6.2.2. Communication Format Supported by The SPI Slave
The ESP8266 SPI slave communication format should be command+address+read/write
data or command+slave status value. To be specific:
Command: length, 8 bits; master output slave input (MOSI).
•
0x02 is the data sent by the master and received by the slave. The master writes 32 bytes
of data through MOSI into SPI_W7 in corresponding register SPI_W0 of the slave data
buffer.
0x03 is the data received by the master and sent by the slave. 32 bytes of data from
corresponding register of the slave buffer between SPI_FLASH_C8 and SPI_FLASH_C15
are sent to the master through MISO.
0x04 and 0x05 can read the lower 8 bits of SPI_FLASH_STATUS in the slave status
register.
⚠ Notice:
Other values are used to read/write the SPI slave status register SPI_FLASH_STATUS. Their communication
formats are different from those of the read/write buffer, using them will cause read/write errors for the slave.
So users should not use these values.
address: length, 8 bits; master output slave input (MOSI). The address content must
•
be 0.
Espressif
SPI Wi-Fi Passthrough 1-
6. SPI Wi-Fi Passthrough 1-Interrupt Mode
Interrupt Mode
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2016.05
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