Instruction On The Data Flow Control Line; Gpio0 Mosi Buffer Status; Gpio2 Master Receives The Slave Send Buffer Status; Master Communication Logic Implementation - Espressif ESP8266 Technical Reference

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7.3. Instruction on The Data Flow Control Line

The ESP8266 uses 2 GPIOs to output the slave receive buffer status and send buffer
status.
7.3.1. GPIO0 MOSI Buffer Status
When GPIO0 enters the slave receive interrupt, the interrupt program will resume the SPI
slave to communicable status in order to prepare for the next communication. Then, GPIO0
will be written to be low level, data received will be processed, and GPIO0 will be written to
be high level to exit the interrupt program. Therefore:
Between the master enables an SPI write communication to GPIO0 generates a
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falling edge, if users enable any other SPIs, communication errors will occur.
When GPIO0 is at low level, if the master enables any SPI to write (0x02 command),
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SPI_W0 to SPI_W7 in the slave receive register will be covered. But if there is
effective data in the slave send register (refer to GPIO2 instructions), when GPIO0 is
at low level, master can be started to read (0x03 command) data between SPI_W8 to
SPI_W15 in the slave send register.
If GPIO0 shifts from low level to high level, it means the slave has processed data
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from SPI_W0 to SPI_W7 in the receive register, and the master can start another
write operation (0x02 command).
7.3.2. GPIO2 Master Receives The Slave Send Buffer Status
GPIO2 activities are slightly different from those of GPIO0. In the slave send interrupt, the
interrupt program will resume the SPI slave to communicable status in order to prepare for
the next communication. Then, GPIO0 will be written to be low level, and quit the interrupt
program. After that, if data is sent to the ESP8266 through WiFi and is required to be
forwarded by SPI, ESP8266 software will be written into SPI_W8 to SPI_W15, and GPIO2
will be set to be high level. Therefore:
Between the master enables an SPI read communication to GPIO2 generates a
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falling edge, if users enable any other SPIs, communication errors will occur.
When GPIO2 is at low level, if the master enables any SPI to read (0x03 command), it
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can only read data the same as the previous data, or incomplete data. But if data in
the slave receive register has been processed (refer to GPIO2 instructions), when
GPIO2 is at low level, master can be started to write (0x02 command).
If GPIO2 shifts from low level to high level, it means the slave has updated data from
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SPI_W8 to SPI_W15 in the send register, and the master can start the another read
operation (0x03 command).

7.3.3. Master Communication Logic Implementation

Incomplete C code is used to briefly introduce the communication logic:
Espressif
7. SPI Wi-Fi Passthrough 2-Interrupt Mode
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