Espressif ESP8266 Technical Reference page 77

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To enable interrupt:
In UART_INT_ENA register,
#define UART_PARITY_ERR_INT_ENA (BIT(2)) //Parity error enable interrupt bit, 1:enable;
0:disable
#define UART_BRK_DET_INT_ENA (BIT(7)) //Terminal line error enable interrupt bit
1: enable;0: disable
#define UART_FRM_ERR_INT_ENA (BIT(3)) //Received frame error to enable interrupt bit
1: enable;0: disable
Clear interrupt status:
Clear the interrupt status bit after dealing with corresponding error.
Flow control status interrupt
Interruption status bit:
UART_CTS_CHG_INT_ST
UART_DSR_CHG_INT_ST
Definition:
When the CTS, DSR pin-line level changes, trigger this interrupt.
Application:
Generally use with flow control, when the trigger the interrupt, check the corresponding
flow control line status,if it's high, stop writing to tx queue.
#define UART_CTS_CHG_INT_ST
#define UART_DSR_CHG_INT_ST
Set enable interrupt:
In UART_INT_ENA register,
#define UART_CTS_CHG_INT_ENA (BIT(6)) CTS //Line status enable interrupt bit,
1:enable;0:disable
#define UART_DSR_CHG_INT_ENA (BIT(5)) DSR //Line status enable interrupt bit,
1:enable;0:disable
Clear interrupt status:
After dealing with the corresponding error,clear the interrupt status bit.
Espressif
(BIT(6))
(BIT(5))
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11. UART Introduction
2016.05