Espressif ESP8266 Technical Reference page 75

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Definition: When enable receive overflow to interrupt and the length of the receive queue is
greater than the total length of the queue (128 Bytes), it will trigger the interrupt signal.
Trigger scene: Generally, it's only under the case of unset flow control,because there will not
occur overflow when has flow control.Different from the full interrupt is artificially set the
threshold and the data will not lose,overflow interrupt triggering will usually has data loss.
Can be used for debugging and error checking.
Set enable to interrupt:
In UART_INT_ENA register
#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) //Overflow interrupt enable bit: 1: enable; 0:
disable
Clear interrupt status:
Read queue value to make the queue length less than 128, then set the clear interrupt
status register.
Receive timeout interrupt
Interrupt status bit: UART_RXFIFO_TOUT_INT_ST
Definition:When configure threshold value of tout,enable interrupts and UART begin to
receive data, it will triggered tout interrupt once stop transmission time exceeds the set
threshold.
Applications: more applied in handling serial commands or data, process the data directly,
or post a message, or turn into deposited buffer.
Configure threshold and function enable:
Tout interrupt threshold (or threshold) in UART_CONF1 register.
Tout unit threshold is about 8 data bits uart time (approximately one byte).
#define UART_RX_TOUT_EN (BIT(31)) //Timeout function enable bit: 1: enable;0: disable
#define UART_RX_TOUT_THRHD 0x0000007F //Timeout threshold configuration bits, a
total of seven and range 0 ~ 127
#define UART_RX_TOUT_THRHD_S 24 //Register offset is 24 (start from 24th bit)
Set enable to interrupt:
In UART_INT_ENA register
#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) tout // Interrupt enable bit:1: enable;0:
disable
Clear interrupt status:
Like full interrupts,tout interrupt also need to firstly read out all received fifo data,then clear
interrupt status register.Otherwise, interrupt status bit will still be set after exiting.
Please see details in examples of interrupt handling.
Espressif 66 86 ! /!
11. UART Introduction
2016.05