Hardware Specifications - ICP DAS USA mPAC-7186EXD-CAN User Manual

1.3 Hardware Specifications

System
 CPU: 80186, 80MHz (for μPAC-7186EXD-CAN)

CPU: 80188, 40MHz (for I-7188XBD-CAN)

SRAM: 512K bytes

Build-in Flash Memory, EEPROM, NVSRAM, Real Time Clock

Built-in Watchdog Timer

16-bit Timer
Flash Memory

512K bytes

Minimum erase unit is one sector (64K bytes)

100,000 erase/write cycles
EEPROM

16K bytes (64 blocks, each block has 256 bytes)

Data retention >100 years

1,000,000 erase/write cycles
Real Time Clock

Year-2000 compliance

Second, minute, hour, date of the month

Month, year, valid up from 1980 to 2079

NVSRAM: 31 bytes, battery backup, data valid up to 10 years
CAN port

Philip SJA1000 CAN controller

Philip 82C250 CAN transceiver

1000 voltage protection on CAN side

120Ω terminal resister selected by jumper

16M Hz clock
COM1

RS-232 or RS-485 Interface

RS-232: TXD, RXD, RTS, CTS, GND

Communication speed: 115200 Max.

Program download port
I-7188XBD-CAN/μPAC-7186EXD-CAN user manual (ver.1.0.3, May/09/2014) 7